drivers/pinctrl/tegra/pinctrl-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for the NVIDIA Tegra pinmux
   4  *
   5  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Derived from code:
   8  * Copyright (C) 2010 Google, Inc.
   9  * Copyright (C) 2010 NVIDIA Corporation
  10  * Copyright (C) 2009-2011 ST-Ericsson AB
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/slab.h>
  20
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinconf.h>
  23 #include <linux/pinctrl/pinctrl.h>
  24 #include <linux/pinctrl/pinmux.h>
  25
  26 #include "../core.h"
  27 #include "../pinctrl-utils.h"
  28 #include "pinctrl-tegra.h"
  29
  30 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  31 {
  32         return readl(pmx->regs[bank] + reg);
  33 }
  34
  35 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  36 {
  37         writel_relaxed(val, pmx->regs[bank] + reg);
  38         /* make sure pinmux register write completed */
  39         pmx_readl(pmx, bank, reg);
  40 }
  41
  42 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  43 {
  44         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  45
  46         return pmx->soc->ngroups;
  47 }
  48
  49 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  50                                                 unsigned group)
  51 {
  52         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  53
  54         return pmx->soc->groups[group].name;
  55 }
  56
  57 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  58                                         unsigned group,
  59                                         const unsigned **pins,
  60                                         unsigned *num_pins)
  61 {
  62         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  63
  64         *pins = pmx->soc->groups[group].pins;
  65         *num_pins = pmx->soc->groups[group].npins;
  66
  67         return 0;
  68 }
  69
  70 #ifdef CONFIG_DEBUG_FS
  71 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  72                                        struct seq_file *s,
  73                                        unsigned offset)
  74 {
  75         seq_printf(s, " %s", dev_name(pctldev->dev));
  76 }
  77 #endif
  78
  79 static const struct cfg_param {
  80         const char *property;
  81         enum tegra_pinconf_param param;
  82 } cfg_params[] = {
  83         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
  84         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
  85         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
  86         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
  87         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
  88         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
  89         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
  90         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
  91         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
  92         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
  93         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
  94         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
  95         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
  96         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
  97         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
  98         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
  99 };
 100
 101 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 102                                            struct device_node *np,
 103                                            struct pinctrl_map **map,
 104                                            unsigned *reserved_maps,
 105                                            unsigned *num_maps)
 106 {
 107         struct device *dev = pctldev->dev;
 108         int ret, i;
 109         const char *function;
 110         u32 val;
 111         unsigned long config;
 112         unsigned long *configs = NULL;
 113         unsigned num_configs = 0;
 114         unsigned reserve;
 115         struct property *prop;
 116         const char *group;
 117
 118         ret = of_property_read_string(np, "nvidia,function", &function);
 119         if (ret < 0) {
 120                 /* EINVAL=missing, which is fine since it's optional */
 121                 if (ret != -EINVAL)
 122                         dev_err(dev,
 123                                 "%pOF: could not parse property nvidia,function\n", np);
 124                 function = NULL;
 125         }
 126
 127         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 128                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 129                 if (!ret) {
 130                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 131                         ret = pinctrl_utils_add_config(pctldev, &configs,
 132                                         &num_configs, config);
 133                         if (ret < 0)
 134                                 goto exit;
 135                 /* EINVAL=missing, which is fine since it's optional */
 136                 } else if (ret != -EINVAL) {
 137                         dev_err(dev, "%pOF: could not parse property %s\n",
 138                                 np, cfg_params[i].property);
 139                 }
 140         }
 141
 142         reserve = 0;
 143         if (function != NULL)
 144                 reserve++;
 145         if (num_configs)
 146                 reserve++;
 147         ret = of_property_count_strings(np, "nvidia,pins");
 148         if (ret < 0) {
 149                 dev_err(dev, "%pOF: could not parse property nvidia,pins\n", np);
 150                 goto exit;
 151         }
 152         reserve *= ret;
 153
 154         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
 155                                         num_maps, reserve);
 156         if (ret < 0)
 157                 goto exit;
 158
 159         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 160                 if (function) {
 161                         ret = pinctrl_utils_add_map_mux(pctldev, map,
 162                                         reserved_maps, num_maps, group,
 163                                         function);
 164                         if (ret < 0)
 165                                 goto exit;
 166                 }
 167
 168                 if (num_configs) {
 169                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 170                                         reserved_maps, num_maps, group,
 171                                         configs, num_configs,
 172                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 173                         if (ret < 0)
 174                                 goto exit;
 175                 }
 176         }
 177
 178         ret = 0;
 179
 180 exit:
 181         kfree(configs);
 182         return ret;
 183 }
 184
 185 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 186                                         struct device_node *np_config,
 187                                         struct pinctrl_map **map,
 188                                         unsigned *num_maps)
 189 {
 190         unsigned reserved_maps;
 191         int ret;
 192
 193         reserved_maps = 0;
 194         *map = NULL;
 195         *num_maps = 0;
 196
 197         for_each_child_of_node_scoped(np_config, np) {
 198                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
 199                                                       &reserved_maps, num_maps);
 200                 if (ret < 0) {
 201                         pinctrl_utils_free_map(pctldev, *map,
 202                                 *num_maps);
 203                         return ret;
 204                 }
 205         }
 206
 207         return 0;
 208 }
 209
 210 static const struct pinctrl_ops tegra_pinctrl_ops = {
 211         .get_groups_count = tegra_pinctrl_get_groups_count,
 212         .get_group_name = tegra_pinctrl_get_group_name,
 213         .get_group_pins = tegra_pinctrl_get_group_pins,
 214 #ifdef CONFIG_DEBUG_FS
 215         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 216 #endif
 217         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 218         .dt_free_map = pinctrl_utils_free_map,
 219 };
 220
 221 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 222 {
 223         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 224
 225         return pmx->soc->nfunctions;
 226 }
 227
 228 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 229                                                unsigned function)
 230 {
 231         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 232
 233         return pmx->functions[function].name;
 234 }
 235
 236 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 237                                          unsigned function,
 238                                          const char * const **groups,
 239                                          unsigned * const num_groups)
 240 {
 241         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 242
 243         *groups = pmx->functions[function].groups;
 244         *num_groups = pmx->functions[function].ngroups;
 245
 246         return 0;
 247 }
 248
 249 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 250                                  unsigned function,
 251                                  unsigned group)
 252 {
 253         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 254         const struct tegra_pingroup *g;
 255         int i;
 256         u32 val;
 257
 258         g = &pmx->soc->groups[group];
 259
 260         if (WARN_ON(g->mux_reg < 0))
 261                 return -EINVAL;
 262
 263         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 264                 if (g->funcs[i] == function)
 265                         break;
 266         }
 267         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 268                 return -EINVAL;
 269
 270         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 271         val &= ~(0x3 << g->mux_bit);
 272         val |= i << g->mux_bit;
 273         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 274
 275         return 0;
 276 }
 277
 278 static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev,
 279                                         unsigned int offset)
 280 {
 281         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 282         unsigned int group, num_pins, j;
 283         const unsigned int *pins;
 284         int ret;
 285
 286         for (group = 0; group < pmx->soc->ngroups; ++group) {
 287                 ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins);
 288                 if (ret < 0)
 289                         continue;
 290                 for (j = 0; j < num_pins; j++) {
 291                         if (offset == pins[j])
 292                                 return &pmx->soc->groups[group];
 293                 }
 294         }
 295
 296         dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset);
 297         return NULL;
 298 }
 299
 300 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
 301                                              struct pinctrl_gpio_range *range,
 302                                              unsigned int offset)
 303 {
 304         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 305         const struct tegra_pingroup *group;
 306         u32 value;
 307
 308         if (!pmx->soc->sfsel_in_mux)
 309                 return 0;
 310
 311         group = tegra_pinctrl_get_group(pctldev, offset);
 312
 313         if (!group)
 314                 return -EINVAL;
 315
 316         if (group->mux_reg < 0 || group->sfsel_bit < 0)
 317                 return -EINVAL;
 318
 319         value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
 320         value &= ~BIT(group->sfsel_bit);
 321         pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
 322
 323         return 0;
 324 }
 325
 326 static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
 327                                             struct pinctrl_gpio_range *range,
 328                                             unsigned int offset)
 329 {
 330         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 331         const struct tegra_pingroup *group;
 332         u32 value;
 333
 334         if (!pmx->soc->sfsel_in_mux)
 335                 return;
 336
 337         group = tegra_pinctrl_get_group(pctldev, offset);
 338
 339         if (!group)
 340                 return;
 341
 342         if (group->mux_reg < 0 || group->sfsel_bit < 0)
 343                 return;
 344
 345         value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
 346         value |= BIT(group->sfsel_bit);
 347         pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
 348 }
 349
 350 static const struct pinmux_ops tegra_pinmux_ops = {
 351         .get_functions_count = tegra_pinctrl_get_funcs_count,
 352         .get_function_name = tegra_pinctrl_get_func_name,
 353         .get_function_groups = tegra_pinctrl_get_func_groups,
 354         .set_mux = tegra_pinctrl_set_mux,
 355         .gpio_request_enable = tegra_pinctrl_gpio_request_enable,
 356         .gpio_disable_free = tegra_pinctrl_gpio_disable_free,
 357 };
 358
 359 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 360                              const struct tegra_pingroup *g,
 361                              enum tegra_pinconf_param param,
 362                              bool report_err,
 363                              s8 *bank, s32 *reg, s8 *bit, s8 *width)
 364 {
 365         switch (param) {
 366         case TEGRA_PINCONF_PARAM_PULL:
 367                 *bank = g->pupd_bank;
 368                 *reg = g->pupd_reg;
 369                 *bit = g->pupd_bit;
 370                 *width = 2;
 371                 break;
 372         case TEGRA_PINCONF_PARAM_TRISTATE:
 373                 *bank = g->tri_bank;
 374                 *reg = g->tri_reg;
 375                 *bit = g->tri_bit;
 376                 *width = 1;
 377                 break;
 378         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 379                 *bank = g->mux_bank;
 380                 *reg = g->mux_reg;
 381                 *bit = g->einput_bit;
 382                 *width = 1;
 383                 break;
 384         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 385                 *bank = g->mux_bank;
 386                 *reg = g->mux_reg;
 387                 *bit = g->odrain_bit;
 388                 *width = 1;
 389                 break;
 390         case TEGRA_PINCONF_PARAM_LOCK:
 391                 *bank = g->mux_bank;
 392                 *reg = g->mux_reg;
 393                 *bit = g->lock_bit;
 394                 *width = 1;
 395                 break;
 396         case TEGRA_PINCONF_PARAM_IORESET:
 397                 *bank = g->mux_bank;
 398                 *reg = g->mux_reg;
 399                 *bit = g->ioreset_bit;
 400                 *width = 1;
 401                 break;
 402         case TEGRA_PINCONF_PARAM_RCV_SEL:
 403                 *bank = g->mux_bank;
 404                 *reg = g->mux_reg;
 405                 *bit = g->rcv_sel_bit;
 406                 *width = 1;
 407                 break;
 408         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 409                 if (pmx->soc->hsm_in_mux) {
 410                         *bank = g->mux_bank;
 411                         *reg = g->mux_reg;
 412                 } else {
 413                         *bank = g->drv_bank;
 414                         *reg = g->drv_reg;
 415                 }
 416                 *bit = g->hsm_bit;
 417                 *width = 1;
 418                 break;
 419         case TEGRA_PINCONF_PARAM_SCHMITT:
 420                 if (pmx->soc->schmitt_in_mux) {
 421                         *bank = g->mux_bank;
 422                         *reg = g->mux_reg;
 423                 } else {
 424                         *bank = g->drv_bank;
 425                         *reg = g->drv_reg;
 426                 }
 427                 *bit = g->schmitt_bit;
 428                 *width = 1;
 429                 break;
 430         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 431                 *bank = g->drv_bank;
 432                 *reg = g->drv_reg;
 433                 *bit = g->lpmd_bit;
 434                 *width = 2;
 435                 break;
 436         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 437                 *bank = g->drv_bank;
 438                 *reg = g->drv_reg;
 439                 *bit = g->drvdn_bit;
 440                 *width = g->drvdn_width;
 441                 break;
 442         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 443                 *bank = g->drv_bank;
 444                 *reg = g->drv_reg;
 445                 *bit = g->drvup_bit;
 446                 *width = g->drvup_width;
 447                 break;
 448         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 449                 *bank = g->drv_bank;
 450                 *reg = g->drv_reg;
 451                 *bit = g->slwf_bit;
 452                 *width = g->slwf_width;
 453                 break;
 454         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 455                 *bank = g->drv_bank;
 456                 *reg = g->drv_reg;
 457                 *bit = g->slwr_bit;
 458                 *width = g->slwr_width;
 459                 break;
 460         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 461                 if (pmx->soc->drvtype_in_mux) {
 462                         *bank = g->mux_bank;
 463                         *reg = g->mux_reg;
 464                 } else {
 465                         *bank = g->drv_bank;
 466                         *reg = g->drv_reg;
 467                 }
 468                 *bit = g->drvtype_bit;
 469                 *width = 2;
 470                 break;
 471         default:
 472                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 473                 return -ENOTSUPP;
 474         }
 475
 476         if (*reg < 0 || *bit < 0)  {
 477                 if (report_err) {
 478                         const char *prop = "unknown";
 479                         int i;
 480
 481                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 482                                 if (cfg_params[i].param == param) {
 483                                         prop = cfg_params[i].property;
 484                                         break;
 485                                 }
 486                         }
 487
 488                         dev_err(pmx->dev,
 489                                 "Config param %04x (%s) not supported on group %s\n",
 490                                 param, prop, g->name);
 491                 }
 492                 return -ENOTSUPP;
 493         }
 494
 495         return 0;
 496 }
 497
 498 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 499                              unsigned pin, unsigned long *config)
 500 {
 501         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 502         return -ENOTSUPP;
 503 }
 504
 505 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 506                              unsigned pin, unsigned long *configs,
 507                              unsigned num_configs)
 508 {
 509         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 510         return -ENOTSUPP;
 511 }
 512
 513 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 514                                    unsigned group, unsigned long *config)
 515 {
 516         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 517         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 518         u16 arg;
 519         const struct tegra_pingroup *g;
 520         int ret;
 521         s8 bank, bit, width;
 522         s32 reg;
 523         u32 val, mask;
 524
 525         g = &pmx->soc->groups[group];
 526
 527         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 528                                 &width);
 529         if (ret < 0)
 530                 return ret;
 531
 532         val = pmx_readl(pmx, bank, reg);
 533         mask = (1 << width) - 1;
 534         arg = (val >> bit) & mask;
 535
 536         *config = TEGRA_PINCONF_PACK(param, arg);
 537
 538         return 0;
 539 }
 540
 541 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 542                                    unsigned group, unsigned long *configs,
 543                                    unsigned num_configs)
 544 {
 545         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 546         enum tegra_pinconf_param param;
 547         u16 arg;
 548         const struct tegra_pingroup *g;
 549         int ret, i;
 550         s8 bank, bit, width;
 551         s32 reg;
 552         u32 val, mask;
 553
 554         g = &pmx->soc->groups[group];
 555
 556         for (i = 0; i < num_configs; i++) {
 557                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
 558                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
 559
 560                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 561                                         &width);
 562                 if (ret < 0)
 563                         return ret;
 564
 565                 val = pmx_readl(pmx, bank, reg);
 566
 567                 /* LOCK can't be cleared */
 568                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
 569                         if ((val & BIT(bit)) && !arg) {
 570                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 571                                 return -EINVAL;
 572                         }
 573                 }
 574
 575                 /* Special-case Boolean values; allow any non-zero as true */
 576                 if (width == 1)
 577                         arg = !!arg;
 578
 579                 /* Range-check user-supplied value */
 580                 mask = (1 << width) - 1;
 581                 if (arg & ~mask) {
 582                         dev_err(pctldev->dev,
 583                                 "config %lx: %x too big for %d bit register\n",
 584                                 configs[i], arg, width);
 585                         return -EINVAL;
 586                 }
 587
 588                 /* Update register */
 589                 val &= ~(mask << bit);
 590                 val |= arg << bit;
 591                 pmx_writel(pmx, val, bank, reg);
 592         } /* for each config */
 593
 594         return 0;
 595 }
 596
 597 #ifdef CONFIG_DEBUG_FS
 598 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 599                                    struct seq_file *s, unsigned offset)
 600 {
 601 }
 602
 603 static const char *strip_prefix(const char *s)
 604 {
 605         const char *comma = strchr(s, ',');
 606         if (!comma)
 607                 return s;
 608
 609         return comma + 1;
 610 }
 611
 612 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 613                                          struct seq_file *s, unsigned group)
 614 {
 615         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 616         const struct tegra_pingroup *g;
 617         int i, ret;
 618         s8 bank, bit, width;
 619         s32 reg;
 620         u32 val;
 621
 622         g = &pmx->soc->groups[group];
 623
 624         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 625                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 626                                         &bank, &reg, &bit, &width);
 627                 if (ret < 0)
 628                         continue;
 629
 630                 val = pmx_readl(pmx, bank, reg);
 631                 val >>= bit;
 632                 val &= (1 << width) - 1;
 633
 634                 seq_printf(s, "\n\t%s=%u",
 635                            strip_prefix(cfg_params[i].property), val);
 636         }
 637
 638         if (g->mux_reg >= 0) {
 639                 /* read pinmux function and dump to seq_file */
 640                 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 641                 val = g->funcs[(val >> g->mux_bit) & 0x3];
 642
 643                 seq_printf(s, "\n\tfunction=%s", pmx->functions[val].name);
 644         }
 645 }
 646
 647 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 648                                           struct seq_file *s,
 649                                           unsigned long config)
 650 {
 651         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 652         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 653         const char *pname = "unknown";
 654         int i;
 655
 656         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 657                 if (cfg_params[i].param == param) {
 658                         pname = cfg_params[i].property;
 659                         break;
 660                 }
 661         }
 662
 663         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 664 }
 665 #endif
 666
 667 static const struct pinconf_ops tegra_pinconf_ops = {
 668         .pin_config_get = tegra_pinconf_get,
 669         .pin_config_set = tegra_pinconf_set,
 670         .pin_config_group_get = tegra_pinconf_group_get,
 671         .pin_config_group_set = tegra_pinconf_group_set,
 672 #ifdef CONFIG_DEBUG_FS
 673         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 674         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 675         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 676 #endif
 677 };
 678
 679 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
 680 {
 681         int i = 0;
 682         const struct tegra_pingroup *g;
 683         u32 val;
 684
 685         for (i = 0; i < pmx->soc->ngroups; ++i) {
 686                 g = &pmx->soc->groups[i];
 687                 if (g->parked_bitmask > 0) {
 688                         unsigned int bank, reg;
 689
 690                         if (g->mux_reg != -1) {
 691                                 bank = g->mux_bank;
 692                                 reg = g->mux_reg;
 693                         } else {
 694                                 bank = g->drv_bank;
 695                                 reg = g->drv_reg;
 696                         }
 697
 698                         val = pmx_readl(pmx, bank, reg);
 699                         val &= ~g->parked_bitmask;
 700                         pmx_writel(pmx, val, bank, reg);
 701                 }
 702         }
 703 }
 704
 705 static size_t tegra_pinctrl_get_bank_size(struct device *dev,
 706                                           unsigned int bank_id)
 707 {
 708         struct platform_device *pdev = to_platform_device(dev);
 709         struct resource *res;
 710
 711         res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
 712
 713         return resource_size(res) / 4;
 714 }
 715
 716 static int tegra_pinctrl_suspend(struct device *dev)
 717 {
 718         struct tegra_pmx *pmx = dev_get_drvdata(dev);
 719         u32 *backup_regs = pmx->backup_regs;
 720         u32 __iomem *regs;
 721         size_t bank_size;
 722         unsigned int i, k;
 723
 724         for (i = 0; i < pmx->nbanks; i++) {
 725                 bank_size = tegra_pinctrl_get_bank_size(dev, i);
 726                 regs = pmx->regs[i];
 727                 for (k = 0; k < bank_size; k++)
 728                         *backup_regs++ = readl_relaxed(regs++);
 729         }
 730
 731         return pinctrl_force_sleep(pmx->pctl);
 732 }
 733
 734 static int tegra_pinctrl_resume(struct device *dev)
 735 {
 736         struct tegra_pmx *pmx = dev_get_drvdata(dev);
 737         u32 *backup_regs = pmx->backup_regs;
 738         u32 __iomem *regs;
 739         size_t bank_size;
 740         unsigned int i, k;
 741
 742         for (i = 0; i < pmx->nbanks; i++) {
 743                 bank_size = tegra_pinctrl_get_bank_size(dev, i);
 744                 regs = pmx->regs[i];
 745                 for (k = 0; k < bank_size; k++)
 746                         writel_relaxed(*backup_regs++, regs++);
 747         }
 748
 749         /* flush all the prior writes */
 750         readl_relaxed(pmx->regs[0]);
 751         /* wait for pinctrl register read to complete */
 752         rmb();
 753         return 0;
 754 }
 755
 756 DEFINE_NOIRQ_DEV_PM_OPS(tegra_pinctrl_pm, tegra_pinctrl_suspend, tegra_pinctrl_resume);
 757
 758 static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
 759 {
 760         struct device_node *np;
 761         bool has_prop = false;
 762
 763         np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
 764         if (!np)
 765                 return has_prop;
 766
 767         has_prop = of_find_property(np, "gpio-ranges", NULL);
 768
 769         of_node_put(np);
 770
 771         return has_prop;
 772 }
 773
 774 int tegra_pinctrl_probe(struct platform_device *pdev,
 775                         const struct tegra_pinctrl_soc_data *soc_data)
 776 {
 777         struct tegra_pmx *pmx;
 778         struct resource *res;
 779         int i;
 780         const char **group_pins;
 781         int fn, gn, gfn;
 782         unsigned long backup_regs_size = 0;
 783
 784         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 785         if (!pmx)
 786                 return -ENOMEM;
 787
 788         pmx->dev = &pdev->dev;
 789         pmx->soc = soc_data;
 790
 791         /*
 792          * Each mux group will appear in 4 functions' list of groups.
 793          * This over-allocates slightly, since not all groups are mux groups.
 794          */
 795         pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4,
 796                                        sizeof(*pmx->group_pins), GFP_KERNEL);
 797         if (!pmx->group_pins)
 798                 return -ENOMEM;
 799
 800         pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions,
 801                                       sizeof(*pmx->functions), GFP_KERNEL);
 802         if (!pmx->functions)
 803                 return -ENOMEM;
 804
 805         group_pins = pmx->group_pins;
 806
 807         for (fn = 0; fn < pmx->soc->nfunctions; fn++) {
 808                 struct tegra_function *func = &pmx->functions[fn];
 809
 810                 func->name = pmx->soc->functions[fn];
 811                 func->groups = group_pins;
 812
 813                 for (gn = 0; gn < pmx->soc->ngroups; gn++) {
 814                         const struct tegra_pingroup *g = &pmx->soc->groups[gn];
 815
 816                         if (g->mux_reg == -1)
 817                                 continue;
 818
 819                         for (gfn = 0; gfn < 4; gfn++)
 820                                 if (g->funcs[gfn] == fn)
 821                                         break;
 822                         if (gfn == 4)
 823                                 continue;
 824
 825                         BUG_ON(group_pins - pmx->group_pins >=
 826                                 pmx->soc->ngroups * 4);
 827                         *group_pins++ = g->name;
 828                         func->ngroups++;
 829                 }
 830         }
 831
 832         pmx->gpio_range.name = "Tegra GPIOs";
 833         pmx->gpio_range.id = 0;
 834         pmx->gpio_range.base = 0;
 835         pmx->gpio_range.npins = pmx->soc->ngpios;
 836
 837         pmx->desc.pctlops = &tegra_pinctrl_ops;
 838         pmx->desc.pmxops = &tegra_pinmux_ops;
 839         pmx->desc.confops = &tegra_pinconf_ops;
 840         pmx->desc.owner = THIS_MODULE;
 841         pmx->desc.name = dev_name(&pdev->dev);
 842         pmx->desc.pins = pmx->soc->pins;
 843         pmx->desc.npins = pmx->soc->npins;
 844
 845         for (i = 0; ; i++) {
 846                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 847                 if (!res)
 848                         break;
 849                 backup_regs_size += resource_size(res);
 850         }
 851         pmx->nbanks = i;
 852
 853         pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
 854                                  GFP_KERNEL);
 855         if (!pmx->regs)
 856                 return -ENOMEM;
 857
 858         pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
 859                                         GFP_KERNEL);
 860         if (!pmx->backup_regs)
 861                 return -ENOMEM;
 862
 863         for (i = 0; i < pmx->nbanks; i++) {
 864                 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
 865                 if (IS_ERR(pmx->regs[i]))
 866                         return PTR_ERR(pmx->regs[i]);
 867         }
 868
 869         pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx);
 870         if (IS_ERR(pmx->pctl)) {
 871                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 872                 return PTR_ERR(pmx->pctl);
 873         }
 874
 875         tegra_pinctrl_clear_parked_bits(pmx);
 876
 877         if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
 878                 pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range);
 879
 880         platform_set_drvdata(pdev, pmx);
 881
 882         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 883
 884         return 0;
 885 }