drivers/platform/x86/p2sb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Primary to Sideband (P2SB) bridge access support
   4  *
   5  * Copyright (c) 2017, 2021-2022 Intel Corporation.
   6  *
   7  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   8  *          Jonathan Yong <jonathan.yong@intel.com>
   9  */
  10
  11 #include <linux/bits.h>
  12 #include <linux/export.h>
  13 #include <linux/pci.h>
  14 #include <linux/platform_data/x86/p2sb.h>
  15
  16 #include <asm/cpu_device_id.h>
  17 #include <asm/intel-family.h>
  18
  19 #define P2SBC                   0xe0
  20 #define P2SBC_HIDE              BIT(8)
  21
  22 #define P2SB_DEVFN_DEFAULT      PCI_DEVFN(31, 1)
  23 #define P2SB_DEVFN_GOLDMONT     PCI_DEVFN(13, 0)
  24 #define SPI_DEVFN_GOLDMONT      PCI_DEVFN(13, 2)
  25
  26 static const struct x86_cpu_id p2sb_cpu_ids[] = {
  27         X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT),
  28         X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, P2SB_DEVFN_GOLDMONT),
  29         {}
  30 };
  31
  32 /*
  33  * Cache BAR0 of P2SB device functions 0 to 7.
  34  * TODO: The constant 8 is the number of functions that PCI specification
  35  *       defines. Same definitions exist tree-wide. Unify this definition and
  36  *       the other definitions then move to include/uapi/linux/pci.h.
  37  */
  38 #define NR_P2SB_RES_CACHE 8
  39
  40 struct p2sb_res_cache {
  41         u32 bus_dev_id;
  42         struct resource res;
  43 };
  44
  45 static struct p2sb_res_cache p2sb_resources[NR_P2SB_RES_CACHE];
  46
  47 static void p2sb_get_devfn(unsigned int *devfn)
  48 {
  49         unsigned int fn = P2SB_DEVFN_DEFAULT;
  50         const struct x86_cpu_id *id;
  51
  52         id = x86_match_cpu(p2sb_cpu_ids);
  53         if (id)
  54                 fn = (unsigned int)id->driver_data;
  55
  56         *devfn = fn;
  57 }
  58
  59 static bool p2sb_valid_resource(const struct resource *res)
  60 {
  61         return res->flags & ~IORESOURCE_UNSET;
  62 }
  63
  64 /* Copy resource from the first BAR of the device in question */
  65 static void p2sb_read_bar0(struct pci_dev *pdev, struct resource *mem)
  66 {
  67         struct resource *bar0 = pci_resource_n(pdev, 0);
  68
  69         /* Make sure we have no dangling pointers in the output */
  70         memset(mem, 0, sizeof(*mem));
  71
  72         /*
  73          * We copy only selected fields from the original resource.
  74          * Because a PCI device will be removed soon, we may not use
  75          * any allocated data, hence we may not copy any pointers.
  76          */
  77         mem->start = bar0->start;
  78         mem->end = bar0->end;
  79         mem->flags = bar0->flags;
  80         mem->desc = bar0->desc;
  81 }
  82
  83 static void p2sb_scan_and_cache_devfn(struct pci_bus *bus, unsigned int devfn)
  84 {
  85         struct p2sb_res_cache *cache = &p2sb_resources[PCI_FUNC(devfn)];
  86         struct pci_dev *pdev;
  87
  88         pdev = pci_scan_single_device(bus, devfn);
  89         if (!pdev)
  90                 return;
  91
  92         p2sb_read_bar0(pdev, &cache->res);
  93         cache->bus_dev_id = bus->dev.id;
  94
  95         pci_stop_and_remove_bus_device(pdev);
  96 }
  97
  98 static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn)
  99 {
 100         /* Scan the P2SB device and cache its BAR0 */
 101         p2sb_scan_and_cache_devfn(bus, devfn);
 102
 103         /* On Goldmont p2sb_bar() also gets called for the SPI controller */
 104         if (devfn == P2SB_DEVFN_GOLDMONT)
 105                 p2sb_scan_and_cache_devfn(bus, SPI_DEVFN_GOLDMONT);
 106
 107         if (!p2sb_valid_resource(&p2sb_resources[PCI_FUNC(devfn)].res))
 108                 return -ENOENT;
 109
 110         return 0;
 111 }
 112
 113 static struct pci_bus *p2sb_get_bus(struct pci_bus *bus)
 114 {
 115         static struct pci_bus *p2sb_bus;
 116
 117         bus = bus ?: p2sb_bus;
 118         if (bus)
 119                 return bus;
 120
 121         /* Assume P2SB is on the bus 0 in domain 0 */
 122         p2sb_bus = pci_find_bus(0, 0);
 123         return p2sb_bus;
 124 }
 125
 126 static int p2sb_cache_resources(void)
 127 {
 128         unsigned int devfn_p2sb;
 129         u32 value = P2SBC_HIDE;
 130         struct pci_bus *bus;
 131         u16 class;
 132         int ret;
 133
 134         /* Get devfn for P2SB device itself */
 135         p2sb_get_devfn(&devfn_p2sb);
 136
 137         bus = p2sb_get_bus(NULL);
 138         if (!bus)
 139                 return -ENODEV;
 140
 141         /*
 142          * When a device with same devfn exists and its device class is not
 143          * PCI_CLASS_MEMORY_OTHER for P2SB, do not touch it.
 144          */
 145         pci_bus_read_config_word(bus, devfn_p2sb, PCI_CLASS_DEVICE, &class);
 146         if (!PCI_POSSIBLE_ERROR(class) && class != PCI_CLASS_MEMORY_OTHER)
 147                 return -ENODEV;
 148
 149         /*
 150          * Prevent concurrent PCI bus scan from seeing the P2SB device and
 151          * removing via sysfs while it is temporarily exposed.
 152          */
 153         pci_lock_rescan_remove();
 154
 155         /*
 156          * The BIOS prevents the P2SB device from being enumerated by the PCI
 157          * subsystem, so we need to unhide and hide it back to lookup the BAR.
 158          * Unhide the P2SB device here, if needed.
 159          */
 160         pci_bus_read_config_dword(bus, devfn_p2sb, P2SBC, &value);
 161         if (value & P2SBC_HIDE)
 162                 pci_bus_write_config_dword(bus, devfn_p2sb, P2SBC, 0);
 163
 164         ret = p2sb_scan_and_cache(bus, devfn_p2sb);
 165
 166         /* Hide the P2SB device, if it was hidden */
 167         if (value & P2SBC_HIDE)
 168                 pci_bus_write_config_dword(bus, devfn_p2sb, P2SBC, P2SBC_HIDE);
 169
 170         pci_unlock_rescan_remove();
 171
 172         return ret;
 173 }
 174
 175 /**
 176  * p2sb_bar - Get Primary to Sideband (P2SB) bridge device BAR
 177  * @bus: PCI bus to communicate with
 178  * @devfn: PCI slot and function to communicate with
 179  * @mem: memory resource to be filled in
 180  *
 181  * If @bus is NULL, the bus 0 in domain 0 will be used.
 182  * If @devfn is 0, it will be replaced by devfn of the P2SB device.
 183  *
 184  * Caller must provide a valid pointer to @mem.
 185  *
 186  * Return:
 187  * 0 on success or appropriate errno value on error.
 188  */
 189 int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem)
 190 {
 191         struct p2sb_res_cache *cache;
 192
 193         bus = p2sb_get_bus(bus);
 194         if (!bus)
 195                 return -ENODEV;
 196
 197         if (!devfn)
 198                 p2sb_get_devfn(&devfn);
 199
 200         cache = &p2sb_resources[PCI_FUNC(devfn)];
 201         if (cache->bus_dev_id != bus->dev.id)
 202                 return -ENODEV;
 203
 204         if (!p2sb_valid_resource(&cache->res))
 205                 return -ENOENT;
 206
 207         memcpy(mem, &cache->res, sizeof(*mem));
 208         return 0;
 209 }
 210 EXPORT_SYMBOL_GPL(p2sb_bar);
 211
 212 static int __init p2sb_fs_init(void)
 213 {
 214         return p2sb_cache_resources();
 215 }
 216
 217 /*
 218  * pci_rescan_remove_lock() can not be locked in sysfs PCI bus rescan path
 219  * because of deadlock. To avoid the deadlock, access P2SB devices with the lock
 220  * at an early step in kernel initialization and cache required resources.
 221  *
 222  * We want to run as early as possible. If the P2SB was assigned a bad BAR,
 223  * we'll need to wait on pcibios_assign_resources() to fix it. So, our list of
 224  * initcall dependencies looks something like this:
 225  *
 226  * ...
 227  * subsys_initcall (pci_subsys_init)
 228  * fs_initcall     (pcibios_assign_resources)
 229  */
 230 fs_initcall_sync(p2sb_fs_init);