drivers/pmdomain/renesas/r8a779a0-sysc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas R-Car V3U System Controller
   4  *
   5  * Copyright (C) 2020 Renesas Electronics Corp.
   6  */
   7
   8 #include <linux/kernel.h>
   9
  10 #include <dt-bindings/power/r8a779a0-sysc.h>
  11
  12 #include "rcar-gen4-sysc.h"
  13
  14 static struct rcar_gen4_sysc_area r8a779a0_areas[] __initdata = {
  15         { "always-on",  R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
  16         { "a3e0",       R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
  17         { "a3e1",       R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU },
  18         { "a2e0d0",     R8A779A0_PD_A2E0D0, R8A779A0_PD_A3E0, PD_SCU },
  19         { "a2e0d1",     R8A779A0_PD_A2E0D1, R8A779A0_PD_A3E0, PD_SCU },
  20         { "a2e1d0",     R8A779A0_PD_A2E1D0, R8A779A0_PD_A3E1, PD_SCU },
  21         { "a2e1d1",     R8A779A0_PD_A2E1D1, R8A779A0_PD_A3E1, PD_SCU },
  22         { "a1e0d0c0",   R8A779A0_PD_A1E0D0C0, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
  23         { "a1e0d0c1",   R8A779A0_PD_A1E0D0C1, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
  24         { "a1e0d1c0",   R8A779A0_PD_A1E0D1C0, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
  25         { "a1e0d1c1",   R8A779A0_PD_A1E0D1C1, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
  26         { "a1e1d0c0",   R8A779A0_PD_A1E1D0C0, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
  27         { "a1e1d0c1",   R8A779A0_PD_A1E1D0C1, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
  28         { "a1e1d1c0",   R8A779A0_PD_A1E1D1C0, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
  29         { "a1e1d1c1",   R8A779A0_PD_A1E1D1C1, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
  30         { "3dg-a",      R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
  31         { "3dg-b",      R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
  32         { "a3vip0",     R8A779A0_PD_A3VIP0, R8A779A0_PD_ALWAYS_ON },
  33         { "a3vip1",     R8A779A0_PD_A3VIP1, R8A779A0_PD_ALWAYS_ON },
  34         { "a3vip3",     R8A779A0_PD_A3VIP3, R8A779A0_PD_ALWAYS_ON },
  35         { "a3vip2",     R8A779A0_PD_A3VIP2, R8A779A0_PD_ALWAYS_ON },
  36         { "a3isp01",    R8A779A0_PD_A3ISP01, R8A779A0_PD_ALWAYS_ON },
  37         { "a3isp23",    R8A779A0_PD_A3ISP23, R8A779A0_PD_ALWAYS_ON },
  38         { "a3ir",       R8A779A0_PD_A3IR, R8A779A0_PD_ALWAYS_ON },
  39         { "a2cn0",      R8A779A0_PD_A2CN0, R8A779A0_PD_A3IR },
  40         { "a2imp01",    R8A779A0_PD_A2IMP01, R8A779A0_PD_A3IR },
  41         { "a2dp0",      R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
  42         { "a2cv0",      R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
  43         { "a2cv1",      R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
  44         { "a2cv4",      R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
  45         { "a2cv6",      R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
  46         { "a2cn2",      R8A779A0_PD_A2CN2, R8A779A0_PD_A3IR },
  47         { "a2imp23",    R8A779A0_PD_A2IMP23, R8A779A0_PD_A3IR },
  48         { "a2dp1",      R8A779A0_PD_A2DP1, R8A779A0_PD_A3IR },
  49         { "a2cv2",      R8A779A0_PD_A2CV2, R8A779A0_PD_A3IR },
  50         { "a2cv3",      R8A779A0_PD_A2CV3, R8A779A0_PD_A3IR },
  51         { "a2cv5",      R8A779A0_PD_A2CV5, R8A779A0_PD_A3IR },
  52         { "a2cv7",      R8A779A0_PD_A2CV7, R8A779A0_PD_A3IR },
  53         { "a2cn1",      R8A779A0_PD_A2CN1, R8A779A0_PD_A3IR },
  54         { "a1cnn0",     R8A779A0_PD_A1CNN0, R8A779A0_PD_A2CN0 },
  55         { "a1cnn2",     R8A779A0_PD_A1CNN2, R8A779A0_PD_A2CN2 },
  56         { "a1dsp0",     R8A779A0_PD_A1DSP0, R8A779A0_PD_A2CN2 },
  57         { "a1cnn1",     R8A779A0_PD_A1CNN1, R8A779A0_PD_A2CN1 },
  58         { "a1dsp1",     R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 },
  59 };
  60
  61 const struct rcar_gen4_sysc_info r8a779a0_sysc_info __initconst = {
  62         .areas = r8a779a0_areas,
  63         .num_areas = ARRAY_SIZE(r8a779a0_areas),
  64 };