drivers/pmdomain/renesas/r8a779h0-sysc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas R-Car V4M System Controller
   4  *
   5  * Copyright (C) 2023 Renesas Electronics Corp
   6  */
   7
   8 #include <linux/kernel.h>
   9
  10 #include <dt-bindings/power/renesas,r8a779h0-sysc.h>
  11
  12 #include "rcar-gen4-sysc.h"
  13
  14 static struct rcar_gen4_sysc_area r8a779h0_areas[] __initdata = {
  15         { "always-on",  R8A779H0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
  16         { "c4",         R8A779H0_PD_C4, R8A779H0_PD_ALWAYS_ON },
  17         { "a2e0d0",     R8A779H0_PD_A2E0D0, R8A779H0_PD_C4, PD_SCU },
  18         { "a1e0d0c0",   R8A779H0_PD_A1E0D0C0, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
  19         { "a1e0d0c1",   R8A779H0_PD_A1E0D0C1, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
  20         { "a1e0d0c2",   R8A779H0_PD_A1E0D0C2, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
  21         { "a1e0d0c3",   R8A779H0_PD_A1E0D0C3, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
  22         { "a3cr0",      R8A779H0_PD_A3CR0, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR },
  23         { "a3cr1",      R8A779H0_PD_A3CR1, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR },
  24         { "a3cr2",      R8A779H0_PD_A3CR2, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR },
  25         { "a33dga",     R8A779H0_PD_A33DGA, R8A779H0_PD_C4 },
  26         { "a23dgb",     R8A779H0_PD_A23DGB, R8A779H0_PD_A33DGA },
  27         { "a3vip0",     R8A779H0_PD_A3VIP0, R8A779H0_PD_C4 },
  28         { "a3vip2",     R8A779H0_PD_A3VIP2, R8A779H0_PD_C4 },
  29         { "a3dul",      R8A779H0_PD_A3DUL, R8A779H0_PD_C4 },
  30         { "a3isp0",     R8A779H0_PD_A3ISP0, R8A779H0_PD_C4 },
  31         { "a2cn0",      R8A779H0_PD_A2CN0, R8A779H0_PD_C4 },
  32         { "a1cn0",      R8A779H0_PD_A1CN0, R8A779H0_PD_A2CN0 },
  33         { "a1dsp0",     R8A779H0_PD_A1DSP0, R8A779H0_PD_A2CN0 },
  34         { "a1dsp1",     R8A779H0_PD_A1DSP1, R8A779H0_PD_A2CN0 },
  35         { "a2imp01",    R8A779H0_PD_A2IMP01, R8A779H0_PD_C4 },
  36         { "a2psc",      R8A779H0_PD_A2PSC, R8A779H0_PD_C4 },
  37         { "a2dma",      R8A779H0_PD_A2DMA, R8A779H0_PD_C4 },
  38         { "a2cv0",      R8A779H0_PD_A2CV0, R8A779H0_PD_C4 },
  39         { "a2cv1",      R8A779H0_PD_A2CV1, R8A779H0_PD_C4 },
  40         { "a2cv2",      R8A779H0_PD_A2CV2, R8A779H0_PD_C4 },
  41         { "a2cv3",      R8A779H0_PD_A2CV3, R8A779H0_PD_C4 },
  42         { "a3imr0",     R8A779H0_PD_A3IMR0, R8A779H0_PD_C4 },
  43         { "a3imr1",     R8A779H0_PD_A3IMR1, R8A779H0_PD_C4 },
  44         { "a3imr2",     R8A779H0_PD_A3IMR2, R8A779H0_PD_C4 },
  45         { "a3imr3",     R8A779H0_PD_A3IMR3, R8A779H0_PD_C4 },
  46         { "a3vc",       R8A779H0_PD_A3VC, R8A779H0_PD_C4 },
  47         { "a3pci",      R8A779H0_PD_A3PCI, R8A779H0_PD_C4 },
  48         { "a2pciphy",   R8A779H0_PD_A2PCIPHY, R8A779H0_PD_A3PCI },
  49 };
  50
  51 const struct rcar_gen4_sysc_info r8a779h0_sysc_info __initconst = {
  52         .areas = r8a779h0_areas,
  53         .num_areas = ARRAY_SIZE(r8a779h0_areas),
  54 };