1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.
4 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <linux/delay.h>
9 #include <linux/firmware.h>
10 #include <linux/interrupt.h>
12 #include <linux/iommu.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/remoteproc.h>
24 #include <linux/reset.h>
25 #include <linux/soc/qcom/mdt_loader.h>
26 #include <linux/soc/qcom/smem.h>
27 #include <linux/soc/qcom/smem_state.h>
29 #include "qcom_common.h"
30 #include "qcom_pil_info.h"
31 #include "qcom_q6v5.h"
32 #include "remoteproc_internal.h"
35 #define ACK_TIMEOUT 1000
36 #define ACK_TIMEOUT_US 1000000
37 #define BOOT_FSM_TIMEOUT 10000
39 #define EVB_MASK GENMASK(27, 4)
40 /*QDSP6SS register offsets*/
41 #define RST_EVB_REG 0x10
42 #define CORE_START_REG 0x400
43 #define BOOT_CMD_REG 0x404
44 #define BOOT_STATUS_REG 0x408
45 #define RET_CFG_REG 0x1C
46 /*TCSR register offsets*/
47 #define LPASS_MASTER_IDLE_REG 0x8
48 #define LPASS_HALTACK_REG 0x4
49 #define LPASS_PWR_ON_REG 0x10
50 #define LPASS_HALTREQ_REG 0x0
52 #define SID_MASK_DEFAULT 0xF
54 #define QDSP6SS_XO_CBCR 0x38
55 #define QDSP6SS_CORE_CBCR 0x20
56 #define QDSP6SS_SLEEP_CBCR 0x3c
58 #define LPASS_BOOT_CORE_START BIT(0)
59 #define LPASS_BOOT_CMD_START BIT(0)
60 #define LPASS_EFUSE_Q6SS_EVB_SEL 0x0
62 struct adsp_pil_data
{
63 int crash_reason_smem
;
64 const char *firmware_name
;
67 const char *sysmon_name
;
75 const char **pd_names
;
77 const char *load_state
;
84 struct qcom_q6v5 q6v5
;
89 struct clk_bulk_data
*clks
;
91 void __iomem
*qdsp6ss_base
;
92 void __iomem
*lpass_efuse
;
94 struct reset_control
*pdc_sync_reset
;
95 struct reset_control
*restart
;
97 struct regmap
*halt_map
;
98 unsigned int halt_lpass
;
100 int crash_reason_smem
;
101 const char *info_name
;
103 struct completion start_done
;
104 struct completion stop_done
;
106 phys_addr_t mem_phys
;
107 phys_addr_t mem_reloc
;
112 struct dev_pm_domain_list
*pd_list
;
114 struct qcom_rproc_glink glink_subdev
;
115 struct qcom_rproc_pdm pdm_subdev
;
116 struct qcom_rproc_ssr ssr_subdev
;
117 struct qcom_sysmon
*sysmon
;
119 int (*shutdown
)(struct qcom_adsp
*adsp
);
122 static int qcom_rproc_pds_attach(struct qcom_adsp
*adsp
, const char **pd_names
,
123 unsigned int num_pds
)
125 struct device
*dev
= adsp
->dev
;
126 struct dev_pm_domain_attach_data pd_data
= {
127 .pd_names
= pd_names
,
128 .num_pd_names
= num_pds
,
132 /* Handle single power domain */
139 ret
= dev_pm_domain_attach_list(dev
, &pd_data
, &adsp
->pd_list
);
144 pm_runtime_enable(dev
);
148 static void qcom_rproc_pds_detach(struct qcom_adsp
*adsp
)
150 struct device
*dev
= adsp
->dev
;
151 struct dev_pm_domain_list
*pds
= adsp
->pd_list
;
153 dev_pm_domain_detach_list(pds
);
155 if (dev
->pm_domain
|| pds
)
156 pm_runtime_disable(adsp
->dev
);
159 static int qcom_rproc_pds_enable(struct qcom_adsp
*adsp
)
161 struct device
*dev
= adsp
->dev
;
162 struct dev_pm_domain_list
*pds
= adsp
->pd_list
;
165 if (!dev
->pm_domain
&& !pds
)
169 dev_pm_genpd_set_performance_state(dev
, INT_MAX
);
171 while (pds
&& i
< pds
->num_pds
) {
172 dev_pm_genpd_set_performance_state(pds
->pd_devs
[i
], INT_MAX
);
176 ret
= pm_runtime_resume_and_get(dev
);
178 while (pds
&& i
> 0) {
180 dev_pm_genpd_set_performance_state(pds
->pd_devs
[i
], 0);
184 dev_pm_genpd_set_performance_state(dev
, 0);
190 static void qcom_rproc_pds_disable(struct qcom_adsp
*adsp
)
192 struct device
*dev
= adsp
->dev
;
193 struct dev_pm_domain_list
*pds
= adsp
->pd_list
;
196 if (!dev
->pm_domain
&& !pds
)
200 dev_pm_genpd_set_performance_state(dev
, 0);
202 while (pds
&& i
< pds
->num_pds
) {
203 dev_pm_genpd_set_performance_state(pds
->pd_devs
[i
], 0);
210 static int qcom_wpss_shutdown(struct qcom_adsp
*adsp
)
214 regmap_write(adsp
->halt_map
, adsp
->halt_lpass
+ LPASS_HALTREQ_REG
, 1);
216 /* Wait for halt ACK from QDSP6 */
217 regmap_read_poll_timeout(adsp
->halt_map
,
218 adsp
->halt_lpass
+ LPASS_HALTACK_REG
, val
,
219 val
, 1000, ACK_TIMEOUT_US
);
221 /* Assert the WPSS PDC Reset */
222 reset_control_assert(adsp
->pdc_sync_reset
);
224 /* Place the WPSS processor into reset */
225 reset_control_assert(adsp
->restart
);
227 /* wait after asserting subsystem restart from AOSS */
228 usleep_range(200, 205);
230 /* Remove the WPSS reset */
231 reset_control_deassert(adsp
->restart
);
233 /* De-assert the WPSS PDC Reset */
234 reset_control_deassert(adsp
->pdc_sync_reset
);
236 usleep_range(100, 105);
238 clk_bulk_disable_unprepare(adsp
->num_clks
, adsp
->clks
);
240 regmap_write(adsp
->halt_map
, adsp
->halt_lpass
+ LPASS_HALTREQ_REG
, 0);
242 /* Wait for halt ACK from QDSP6 */
243 regmap_read_poll_timeout(adsp
->halt_map
,
244 adsp
->halt_lpass
+ LPASS_HALTACK_REG
, val
,
245 !val
, 1000, ACK_TIMEOUT_US
);
250 static int qcom_adsp_shutdown(struct qcom_adsp
*adsp
)
252 unsigned long timeout
;
256 /* Reset the retention logic */
257 val
= readl(adsp
->qdsp6ss_base
+ RET_CFG_REG
);
259 writel(val
, adsp
->qdsp6ss_base
+ RET_CFG_REG
);
261 clk_bulk_disable_unprepare(adsp
->num_clks
, adsp
->clks
);
263 /* QDSP6 master port needs to be explicitly halted */
264 ret
= regmap_read(adsp
->halt_map
,
265 adsp
->halt_lpass
+ LPASS_PWR_ON_REG
, &val
);
269 ret
= regmap_read(adsp
->halt_map
,
270 adsp
->halt_lpass
+ LPASS_MASTER_IDLE_REG
,
275 regmap_write(adsp
->halt_map
,
276 adsp
->halt_lpass
+ LPASS_HALTREQ_REG
, 1);
278 /* Wait for halt ACK from QDSP6 */
279 timeout
= jiffies
+ msecs_to_jiffies(ACK_TIMEOUT
);
281 ret
= regmap_read(adsp
->halt_map
,
282 adsp
->halt_lpass
+ LPASS_HALTACK_REG
, &val
);
283 if (ret
|| val
|| time_after(jiffies
, timeout
))
286 usleep_range(1000, 1100);
289 ret
= regmap_read(adsp
->halt_map
,
290 adsp
->halt_lpass
+ LPASS_MASTER_IDLE_REG
, &val
);
292 dev_err(adsp
->dev
, "port failed halt\n");
295 /* Assert the LPASS PDC Reset */
296 reset_control_assert(adsp
->pdc_sync_reset
);
297 /* Place the LPASS processor into reset */
298 reset_control_assert(adsp
->restart
);
299 /* wait after asserting subsystem restart from AOSS */
300 usleep_range(200, 300);
302 /* Clear the halt request for the AXIM and AHBM for Q6 */
303 regmap_write(adsp
->halt_map
, adsp
->halt_lpass
+ LPASS_HALTREQ_REG
, 0);
305 /* De-assert the LPASS PDC Reset */
306 reset_control_deassert(adsp
->pdc_sync_reset
);
307 /* Remove the LPASS reset */
308 reset_control_deassert(adsp
->restart
);
309 /* wait after de-asserting subsystem restart from AOSS */
310 usleep_range(200, 300);
315 static int adsp_load(struct rproc
*rproc
, const struct firmware
*fw
)
317 struct qcom_adsp
*adsp
= rproc
->priv
;
320 ret
= qcom_mdt_load_no_init(adsp
->dev
, fw
, rproc
->firmware
, 0,
321 adsp
->mem_region
, adsp
->mem_phys
,
322 adsp
->mem_size
, &adsp
->mem_reloc
);
326 qcom_pil_info_store(adsp
->info_name
, adsp
->mem_phys
, adsp
->mem_size
);
331 static void adsp_unmap_carveout(struct rproc
*rproc
)
333 struct qcom_adsp
*adsp
= rproc
->priv
;
336 iommu_unmap(rproc
->domain
, adsp
->mem_phys
, adsp
->mem_size
);
339 static int adsp_map_carveout(struct rproc
*rproc
)
341 struct qcom_adsp
*adsp
= rproc
->priv
;
342 struct of_phandle_args args
;
347 if (!adsp
->has_iommu
)
353 ret
= of_parse_phandle_with_args(adsp
->dev
->of_node
, "iommus", "#iommu-cells", 0, &args
);
357 sid
= args
.args
[0] & SID_MASK_DEFAULT
;
359 /* Add SID configuration for ADSP Firmware to SMMU */
360 iova
= adsp
->mem_phys
| (sid
<< 32);
362 ret
= iommu_map(rproc
->domain
, iova
, adsp
->mem_phys
,
363 adsp
->mem_size
, IOMMU_READ
| IOMMU_WRITE
,
366 dev_err(adsp
->dev
, "Unable to map ADSP Physical Memory\n");
373 static int adsp_start(struct rproc
*rproc
)
375 struct qcom_adsp
*adsp
= rproc
->priv
;
379 ret
= qcom_q6v5_prepare(&adsp
->q6v5
);
383 ret
= adsp_map_carveout(rproc
);
385 dev_err(adsp
->dev
, "ADSP smmu mapping failed\n");
389 ret
= clk_prepare_enable(adsp
->xo
);
391 goto adsp_smmu_unmap
;
393 ret
= qcom_rproc_pds_enable(adsp
);
397 ret
= clk_bulk_prepare_enable(adsp
->num_clks
, adsp
->clks
);
399 dev_err(adsp
->dev
, "adsp clk_enable failed\n");
400 goto disable_power_domain
;
403 /* Enable the XO clock */
404 writel(1, adsp
->qdsp6ss_base
+ QDSP6SS_XO_CBCR
);
406 /* Enable the QDSP6SS sleep clock */
407 writel(1, adsp
->qdsp6ss_base
+ QDSP6SS_SLEEP_CBCR
);
409 /* Enable the QDSP6 core clock */
410 writel(1, adsp
->qdsp6ss_base
+ QDSP6SS_CORE_CBCR
);
412 /* Program boot address */
413 writel(adsp
->mem_phys
>> 4, adsp
->qdsp6ss_base
+ RST_EVB_REG
);
415 if (adsp
->lpass_efuse
)
416 writel(LPASS_EFUSE_Q6SS_EVB_SEL
, adsp
->lpass_efuse
);
418 /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
419 writel(LPASS_BOOT_CORE_START
, adsp
->qdsp6ss_base
+ CORE_START_REG
);
421 /* Trigger boot FSM to start QDSP6 */
422 writel(LPASS_BOOT_CMD_START
, adsp
->qdsp6ss_base
+ BOOT_CMD_REG
);
424 /* Wait for core to come out of reset */
425 ret
= readl_poll_timeout(adsp
->qdsp6ss_base
+ BOOT_STATUS_REG
,
426 val
, (val
& BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT
);
428 dev_err(adsp
->dev
, "failed to bootup adsp\n");
429 goto disable_adsp_clks
;
432 ret
= qcom_q6v5_wait_for_start(&adsp
->q6v5
, msecs_to_jiffies(5 * HZ
));
433 if (ret
== -ETIMEDOUT
) {
434 dev_err(adsp
->dev
, "start timed out\n");
435 goto disable_adsp_clks
;
441 clk_bulk_disable_unprepare(adsp
->num_clks
, adsp
->clks
);
442 disable_power_domain
:
443 qcom_rproc_pds_disable(adsp
);
445 clk_disable_unprepare(adsp
->xo
);
447 adsp_unmap_carveout(rproc
);
449 qcom_q6v5_unprepare(&adsp
->q6v5
);
454 static void qcom_adsp_pil_handover(struct qcom_q6v5
*q6v5
)
456 struct qcom_adsp
*adsp
= container_of(q6v5
, struct qcom_adsp
, q6v5
);
458 clk_disable_unprepare(adsp
->xo
);
459 qcom_rproc_pds_disable(adsp
);
462 static int adsp_stop(struct rproc
*rproc
)
464 struct qcom_adsp
*adsp
= rproc
->priv
;
468 ret
= qcom_q6v5_request_stop(&adsp
->q6v5
, adsp
->sysmon
);
469 if (ret
== -ETIMEDOUT
)
470 dev_err(adsp
->dev
, "timed out on wait\n");
472 ret
= adsp
->shutdown(adsp
);
474 dev_err(adsp
->dev
, "failed to shutdown: %d\n", ret
);
476 adsp_unmap_carveout(rproc
);
478 handover
= qcom_q6v5_unprepare(&adsp
->q6v5
);
480 qcom_adsp_pil_handover(&adsp
->q6v5
);
485 static void *adsp_da_to_va(struct rproc
*rproc
, u64 da
, size_t len
, bool *is_iomem
)
487 struct qcom_adsp
*adsp
= rproc
->priv
;
490 offset
= da
- adsp
->mem_reloc
;
491 if (offset
< 0 || offset
+ len
> adsp
->mem_size
)
494 return adsp
->mem_region
+ offset
;
497 static int adsp_parse_firmware(struct rproc
*rproc
, const struct firmware
*fw
)
499 struct qcom_adsp
*adsp
= rproc
->priv
;
502 ret
= qcom_register_dump_segments(rproc
, fw
);
504 dev_err(&rproc
->dev
, "Error in registering dump segments\n");
508 if (adsp
->has_iommu
) {
509 ret
= rproc_elf_load_rsc_table(rproc
, fw
);
511 dev_err(&rproc
->dev
, "Error in loading resource table\n");
518 static unsigned long adsp_panic(struct rproc
*rproc
)
520 struct qcom_adsp
*adsp
= rproc
->priv
;
522 return qcom_q6v5_panic(&adsp
->q6v5
);
525 static const struct rproc_ops adsp_ops
= {
528 .da_to_va
= adsp_da_to_va
,
529 .parse_fw
= adsp_parse_firmware
,
534 static int adsp_init_clock(struct qcom_adsp
*adsp
, const char **clk_ids
)
539 adsp
->xo
= devm_clk_get(adsp
->dev
, "xo");
540 if (IS_ERR(adsp
->xo
))
541 return dev_err_probe(adsp
->dev
, PTR_ERR(adsp
->xo
), "failed to get xo clock");
543 for (i
= 0; clk_ids
[i
]; i
++)
546 adsp
->num_clks
= num_clks
;
547 adsp
->clks
= devm_kcalloc(adsp
->dev
, adsp
->num_clks
,
548 sizeof(*adsp
->clks
), GFP_KERNEL
);
552 for (i
= 0; i
< adsp
->num_clks
; i
++)
553 adsp
->clks
[i
].id
= clk_ids
[i
];
555 return devm_clk_bulk_get(adsp
->dev
, adsp
->num_clks
, adsp
->clks
);
558 static int adsp_init_reset(struct qcom_adsp
*adsp
)
560 adsp
->pdc_sync_reset
= devm_reset_control_get_optional_exclusive(adsp
->dev
,
562 if (IS_ERR(adsp
->pdc_sync_reset
)) {
563 dev_err(adsp
->dev
, "failed to acquire pdc_sync reset\n");
564 return PTR_ERR(adsp
->pdc_sync_reset
);
567 adsp
->restart
= devm_reset_control_get_optional_exclusive(adsp
->dev
, "restart");
569 /* Fall back to the old "cc_lpass" if "restart" is absent */
571 adsp
->restart
= devm_reset_control_get_exclusive(adsp
->dev
, "cc_lpass");
573 if (IS_ERR(adsp
->restart
)) {
574 dev_err(adsp
->dev
, "failed to acquire restart\n");
575 return PTR_ERR(adsp
->restart
);
581 static int adsp_init_mmio(struct qcom_adsp
*adsp
,
582 struct platform_device
*pdev
)
584 struct resource
*efuse_region
;
585 struct device_node
*syscon
;
588 adsp
->qdsp6ss_base
= devm_platform_ioremap_resource(pdev
, 0);
589 if (IS_ERR(adsp
->qdsp6ss_base
)) {
590 dev_err(adsp
->dev
, "failed to map QDSP6SS registers\n");
591 return PTR_ERR(adsp
->qdsp6ss_base
);
594 efuse_region
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
596 adsp
->lpass_efuse
= NULL
;
597 dev_dbg(adsp
->dev
, "failed to get efuse memory region\n");
599 adsp
->lpass_efuse
= devm_ioremap_resource(&pdev
->dev
, efuse_region
);
600 if (IS_ERR(adsp
->lpass_efuse
)) {
601 dev_err(adsp
->dev
, "failed to map efuse registers\n");
602 return PTR_ERR(adsp
->lpass_efuse
);
605 syscon
= of_parse_phandle(pdev
->dev
.of_node
, "qcom,halt-regs", 0);
607 dev_err(&pdev
->dev
, "failed to parse qcom,halt-regs\n");
611 adsp
->halt_map
= syscon_node_to_regmap(syscon
);
613 if (IS_ERR(adsp
->halt_map
))
614 return PTR_ERR(adsp
->halt_map
);
616 ret
= of_property_read_u32_index(pdev
->dev
.of_node
, "qcom,halt-regs",
617 1, &adsp
->halt_lpass
);
619 dev_err(&pdev
->dev
, "no offset in syscon\n");
626 static int adsp_alloc_memory_region(struct qcom_adsp
*adsp
)
628 struct reserved_mem
*rmem
= NULL
;
629 struct device_node
*node
;
631 node
= of_parse_phandle(adsp
->dev
->of_node
, "memory-region", 0);
633 rmem
= of_reserved_mem_lookup(node
);
637 dev_err(adsp
->dev
, "unable to resolve memory-region\n");
641 adsp
->mem_phys
= adsp
->mem_reloc
= rmem
->base
;
642 adsp
->mem_size
= rmem
->size
;
643 adsp
->mem_region
= devm_ioremap_wc(adsp
->dev
,
644 adsp
->mem_phys
, adsp
->mem_size
);
645 if (!adsp
->mem_region
) {
646 dev_err(adsp
->dev
, "unable to map memory region: %pa+%zx\n",
647 &rmem
->base
, adsp
->mem_size
);
654 static int adsp_probe(struct platform_device
*pdev
)
656 const struct adsp_pil_data
*desc
;
657 const char *firmware_name
;
658 struct qcom_adsp
*adsp
;
662 desc
= of_device_get_match_data(&pdev
->dev
);
666 firmware_name
= desc
->firmware_name
;
667 ret
= of_property_read_string(pdev
->dev
.of_node
, "firmware-name",
669 if (ret
< 0 && ret
!= -EINVAL
) {
670 dev_err(&pdev
->dev
, "unable to read firmware-name\n");
674 rproc
= devm_rproc_alloc(&pdev
->dev
, pdev
->name
, &adsp_ops
,
675 firmware_name
, sizeof(*adsp
));
677 dev_err(&pdev
->dev
, "unable to allocate remoteproc\n");
681 rproc
->auto_boot
= desc
->auto_boot
;
682 rproc
->has_iommu
= desc
->has_iommu
;
683 rproc_coredump_set_elf_info(rproc
, ELFCLASS32
, EM_NONE
);
686 adsp
->dev
= &pdev
->dev
;
688 adsp
->info_name
= desc
->sysmon_name
;
689 adsp
->has_iommu
= desc
->has_iommu
;
691 platform_set_drvdata(pdev
, adsp
);
694 adsp
->shutdown
= qcom_wpss_shutdown
;
696 adsp
->shutdown
= qcom_adsp_shutdown
;
698 ret
= adsp_alloc_memory_region(adsp
);
702 ret
= adsp_init_clock(adsp
, desc
->clk_ids
);
706 ret
= qcom_rproc_pds_attach(adsp
, desc
->pd_names
, desc
->num_pds
);
708 return dev_err_probe(&pdev
->dev
, ret
,
709 "Failed to attach proxy power domains\n");
711 ret
= adsp_init_reset(adsp
);
715 ret
= adsp_init_mmio(adsp
, pdev
);
719 ret
= qcom_q6v5_init(&adsp
->q6v5
, pdev
, rproc
, desc
->crash_reason_smem
,
720 desc
->load_state
, qcom_adsp_pil_handover
);
724 qcom_add_glink_subdev(rproc
, &adsp
->glink_subdev
, desc
->ssr_name
);
725 qcom_add_pdm_subdev(rproc
, &adsp
->pdm_subdev
);
726 qcom_add_ssr_subdev(rproc
, &adsp
->ssr_subdev
, desc
->ssr_name
);
727 adsp
->sysmon
= qcom_add_sysmon_subdev(rproc
,
730 if (IS_ERR(adsp
->sysmon
)) {
731 ret
= PTR_ERR(adsp
->sysmon
);
732 goto deinit_remove_glink_pdm_ssr
;
735 ret
= rproc_add(rproc
);
742 qcom_remove_sysmon_subdev(adsp
->sysmon
);
743 deinit_remove_glink_pdm_ssr
:
744 qcom_q6v5_deinit(&adsp
->q6v5
);
745 qcom_remove_glink_subdev(rproc
, &adsp
->glink_subdev
);
746 qcom_remove_pdm_subdev(rproc
, &adsp
->pdm_subdev
);
747 qcom_remove_ssr_subdev(rproc
, &adsp
->ssr_subdev
);
749 qcom_rproc_pds_detach(adsp
);
754 static void adsp_remove(struct platform_device
*pdev
)
756 struct qcom_adsp
*adsp
= platform_get_drvdata(pdev
);
758 rproc_del(adsp
->rproc
);
760 qcom_q6v5_deinit(&adsp
->q6v5
);
761 qcom_remove_glink_subdev(adsp
->rproc
, &adsp
->glink_subdev
);
762 qcom_remove_pdm_subdev(adsp
->rproc
, &adsp
->pdm_subdev
);
763 qcom_remove_sysmon_subdev(adsp
->sysmon
);
764 qcom_remove_ssr_subdev(adsp
->rproc
, &adsp
->ssr_subdev
);
765 qcom_rproc_pds_detach(adsp
);
768 static const struct adsp_pil_data adsp_resource_init
= {
769 .crash_reason_smem
= 423,
770 .firmware_name
= "adsp.mdt",
772 .sysmon_name
= "adsp",
776 .clk_ids
= (const char*[]) {
777 "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",
778 "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
781 .pd_names
= (const char*[]) { "cx" },
785 static const struct adsp_pil_data adsp_sc7280_resource_init
= {
786 .crash_reason_smem
= 423,
787 .firmware_name
= "adsp.pbn",
788 .load_state
= "adsp",
790 .sysmon_name
= "adsp",
794 .clk_ids
= (const char*[]) {
795 "gcc_cfg_noc_lpass", NULL
800 static const struct adsp_pil_data cdsp_resource_init
= {
801 .crash_reason_smem
= 601,
802 .firmware_name
= "cdsp.mdt",
804 .sysmon_name
= "cdsp",
808 .clk_ids
= (const char*[]) {
809 "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",
813 .pd_names
= (const char*[]) { "cx" },
817 static const struct adsp_pil_data wpss_resource_init
= {
818 .crash_reason_smem
= 626,
819 .firmware_name
= "wpss.mdt",
821 .sysmon_name
= "wpss",
825 .load_state
= "wpss",
826 .clk_ids
= (const char*[]) {
827 "ahb_bdg", "ahb", "rscp", NULL
830 .pd_names
= (const char*[]) { "cx", "mx" },
834 static const struct of_device_id adsp_of_match
[] = {
835 { .compatible
= "qcom,qcs404-cdsp-pil", .data
= &cdsp_resource_init
},
836 { .compatible
= "qcom,sc7280-adsp-pil", .data
= &adsp_sc7280_resource_init
},
837 { .compatible
= "qcom,sc7280-wpss-pil", .data
= &wpss_resource_init
},
838 { .compatible
= "qcom,sdm845-adsp-pil", .data
= &adsp_resource_init
},
841 MODULE_DEVICE_TABLE(of
, adsp_of_match
);
843 static struct platform_driver adsp_pil_driver
= {
845 .remove
= adsp_remove
,
847 .name
= "qcom_q6v5_adsp",
848 .of_match_table
= adsp_of_match
,
852 module_platform_driver(adsp_pil_driver
);
853 MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");
854 MODULE_LICENSE("GPL v2");