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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / rtc / rtc-pcf2127.c
blob9c04c4e1a49c370ee50178b5bf7e853c62c75321
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * An I2C and SPI driver for the NXP PCF2127/29/31 RTC
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
8 * Watchdog and tamper functions
9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com>
10 *
11 * PCF2131 support
12 * Author: Hugo Villeneuve <hvilleneuve@dimonoff.com>
13 *
14 * based on the other drivers in this same directory.
15 *
16 * Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
17 * https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf
18 */
19
20 #include <linux/i2c.h>
21 #include <linux/spi/spi.h>
22 #include <linux/bcd.h>
23 #include <linux/rtc.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_device.h>
29 #include <linux/regmap.h>
30 #include <linux/watchdog.h>
31
32 /* Control register 1 */
33 #define PCF2127_REG_CTRL1 0x00
34 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3)
35 #define PCF2127_BIT_CTRL1_TSF1 BIT(4)
36 #define PCF2127_BIT_CTRL1_STOP BIT(5)
37 /* Control register 2 */
38 #define PCF2127_REG_CTRL2 0x01
39 #define PCF2127_BIT_CTRL2_AIE BIT(1)
40 #define PCF2127_BIT_CTRL2_TSIE BIT(2)
41 #define PCF2127_BIT_CTRL2_AF BIT(4)
42 #define PCF2127_BIT_CTRL2_TSF2 BIT(5)
43 #define PCF2127_BIT_CTRL2_WDTF BIT(6)
44 /* Control register 3 */
45 #define PCF2127_REG_CTRL3 0x02
46 #define PCF2127_BIT_CTRL3_BLIE BIT(0)
47 #define PCF2127_BIT_CTRL3_BIE BIT(1)
48 #define PCF2127_BIT_CTRL3_BLF BIT(2)
49 #define PCF2127_BIT_CTRL3_BF BIT(3)
50 #define PCF2127_BIT_CTRL3_BTSE BIT(4)
51 /* Time and date registers */
52 #define PCF2127_REG_TIME_BASE 0x03
53 #define PCF2127_BIT_SC_OSF BIT(7)
54 /* Alarm registers */
55 #define PCF2127_REG_ALARM_BASE 0x0A
56 #define PCF2127_BIT_ALARM_AE BIT(7)
57 /* CLKOUT control register */
58 #define PCF2127_REG_CLKOUT 0x0f
59 #define PCF2127_BIT_CLKOUT_OTPR BIT(5)
60 /* Watchdog registers */
61 #define PCF2127_REG_WD_CTL 0x10
62 #define PCF2127_BIT_WD_CTL_TF0 BIT(0)
63 #define PCF2127_BIT_WD_CTL_TF1 BIT(1)
64 #define PCF2127_BIT_WD_CTL_CD0 BIT(6)
65 #define PCF2127_BIT_WD_CTL_CD1 BIT(7)
66 #define PCF2127_REG_WD_VAL 0x11
67 /* Tamper timestamp1 registers */
68 #define PCF2127_REG_TS1_BASE 0x12
69 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
70 #define PCF2127_BIT_TS_CTRL_TSM BIT(7)
71 /*
72 * RAM registers
73 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
74 * battery backed and can survive a power outage.
75 * PCF2129/31 doesn't have this feature.
76 */
77 #define PCF2127_REG_RAM_ADDR_MSB 0x1A
78 #define PCF2127_REG_RAM_WRT_CMD 0x1C
79 #define PCF2127_REG_RAM_RD_CMD 0x1D
80
81 /* Watchdog timer value constants */
82 #define PCF2127_WD_VAL_STOP 0
83 /* PCF2127/29 watchdog timer value constants */
84 #define PCF2127_WD_CLOCK_HZ_X1000 1000 /* 1Hz */
85 #define PCF2127_WD_MIN_HW_HEARTBEAT_MS 500
86 /* PCF2131 watchdog timer value constants */
87 #define PCF2131_WD_CLOCK_HZ_X1000 250 /* 1/4Hz */
88 #define PCF2131_WD_MIN_HW_HEARTBEAT_MS 4000
89
90 #define PCF2127_WD_DEFAULT_TIMEOUT_S 60
91
92 /* Mask for currently enabled interrupts */
93 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
94 #define PCF2127_CTRL2_IRQ_MASK ( \
95 PCF2127_BIT_CTRL2_AF | \
96 PCF2127_BIT_CTRL2_WDTF | \
97 PCF2127_BIT_CTRL2_TSF2)
98
99 #define PCF2127_MAX_TS_SUPPORTED 4
100
101 /* Control register 4 */
102 #define PCF2131_REG_CTRL4 0x03
103 #define PCF2131_BIT_CTRL4_TSF4 BIT(4)
104 #define PCF2131_BIT_CTRL4_TSF3 BIT(5)
105 #define PCF2131_BIT_CTRL4_TSF2 BIT(6)
106 #define PCF2131_BIT_CTRL4_TSF1 BIT(7)
107 /* Control register 5 */
108 #define PCF2131_REG_CTRL5 0x04
109 #define PCF2131_BIT_CTRL5_TSIE4 BIT(4)
110 #define PCF2131_BIT_CTRL5_TSIE3 BIT(5)
111 #define PCF2131_BIT_CTRL5_TSIE2 BIT(6)
112 #define PCF2131_BIT_CTRL5_TSIE1 BIT(7)
113 /* Software reset register */
114 #define PCF2131_REG_SR_RESET 0x05
115 #define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5))
116 #define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7))
117 /* Time and date registers */
118 #define PCF2131_REG_TIME_BASE 0x07
119 /* Alarm registers */
120 #define PCF2131_REG_ALARM_BASE 0x0E
121 /* CLKOUT control register */
122 #define PCF2131_REG_CLKOUT 0x13
123 /* Watchdog registers */
124 #define PCF2131_REG_WD_CTL 0x35
125 #define PCF2131_REG_WD_VAL 0x36
126 /* Tamper timestamp1 registers */
127 #define PCF2131_REG_TS1_BASE 0x14
128 /* Tamper timestamp2 registers */
129 #define PCF2131_REG_TS2_BASE 0x1B
130 /* Tamper timestamp3 registers */
131 #define PCF2131_REG_TS3_BASE 0x22
132 /* Tamper timestamp4 registers */
133 #define PCF2131_REG_TS4_BASE 0x29
134 /* Interrupt mask registers */
135 #define PCF2131_REG_INT_A_MASK1 0x31
136 #define PCF2131_REG_INT_A_MASK2 0x32
137 #define PCF2131_REG_INT_B_MASK1 0x33
138 #define PCF2131_REG_INT_B_MASK2 0x34
139 #define PCF2131_BIT_INT_BLIE BIT(0)
140 #define PCF2131_BIT_INT_BIE BIT(1)
141 #define PCF2131_BIT_INT_AIE BIT(2)
142 #define PCF2131_BIT_INT_WD_CD BIT(3)
143 #define PCF2131_BIT_INT_SI BIT(4)
144 #define PCF2131_BIT_INT_MI BIT(5)
145 #define PCF2131_CTRL2_IRQ_MASK ( \
146 PCF2127_BIT_CTRL2_AF | \
147 PCF2127_BIT_CTRL2_WDTF)
148 #define PCF2131_CTRL4_IRQ_MASK ( \
149 PCF2131_BIT_CTRL4_TSF4 | \
150 PCF2131_BIT_CTRL4_TSF3 | \
151 PCF2131_BIT_CTRL4_TSF2 | \
152 PCF2131_BIT_CTRL4_TSF1)
153
154 enum pcf21xx_type {
155 PCF2127,
156 PCF2129,
157 PCF2131,
158 PCF21XX_LAST_ID
159 };
160
161 struct pcf21xx_ts_config {
162 u8 reg_base; /* Base register to read timestamp values. */
163
164 /*
165 * If the TS input pin is driven to GND, an interrupt can be generated
166 * (supported by all variants).
167 */
168 u8 gnd_detect_reg; /* Interrupt control register address. */
169 u8 gnd_detect_bit; /* Interrupt bit. */
170
171 /*
172 * If the TS input pin is driven to an intermediate level between GND
173 * and supply, an interrupt can be generated (optional feature depending
174 * on variant).
175 */
176 u8 inter_detect_reg; /* Interrupt control register address. */
177 u8 inter_detect_bit; /* Interrupt bit. */
178
179 u8 ie_reg; /* Interrupt enable control register. */
180 u8 ie_bit; /* Interrupt enable bit. */
181 };
182
183 struct pcf21xx_config {
184 int type; /* IC variant */
185 int max_register;
186 unsigned int has_nvmem:1;
187 unsigned int has_bit_wd_ctl_cd0:1;
188 unsigned int wd_val_reg_readable:1; /* If watchdog value register can be read. */
189 unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */
190 u8 reg_time_base; /* Time/date base register. */
191 u8 regs_alarm_base; /* Alarm function base registers. */
192 u8 reg_wd_ctl; /* Watchdog control register. */
193 u8 reg_wd_val; /* Watchdog value register. */
194 u8 reg_clkout; /* Clkout register. */
195 int wdd_clock_hz_x1000; /* Watchdog clock in Hz multiplicated by 1000 */
196 int wdd_min_hw_heartbeat_ms;
197 unsigned int ts_count;
198 struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED];
199 struct attribute_group attribute_group;
200 };
201
202 struct pcf2127 {
203 struct rtc_device *rtc;
204 struct watchdog_device wdd;
205 struct regmap *regmap;
206 const struct pcf21xx_config *cfg;
207 bool irq_enabled;
208 time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */
209 bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */
210 };
211
212 /*
213 * In the routines that deal directly with the pcf2127 hardware, we use
214 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
215 */
216 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
217 {
218 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
219 unsigned char buf[7];
220 int ret;
221
222 /*
223 * Avoid reading CTRL2 register as it causes WD_VAL register
224 * value to reset to 0 which means watchdog is stopped.
225 */
226 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base,
227 buf, sizeof(buf));
228 if (ret) {
229 dev_err(dev, "%s: read error\n", __func__);
230 return ret;
231 }
232
233 /* Clock integrity is not guaranteed when OSF flag is set. */
234 if (buf[0] & PCF2127_BIT_SC_OSF) {
235 /*
236 * no need clear the flag here,
237 * it will be cleared once the new date is saved
238 */
239 dev_warn(dev,
240 "oscillator stop detected, date/time is not reliable\n");
241 return -EINVAL;
242 }
243
244 dev_dbg(dev,
245 "%s: raw data is sec=%02x, min=%02x, hr=%02x, "
246 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n",
247 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
248
249 tm->tm_sec = bcd2bin(buf[0] & 0x7F);
250 tm->tm_min = bcd2bin(buf[1] & 0x7F);
251 tm->tm_hour = bcd2bin(buf[2] & 0x3F);
252 tm->tm_mday = bcd2bin(buf[3] & 0x3F);
253 tm->tm_wday = buf[4] & 0x07;
254 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1;
255 tm->tm_year = bcd2bin(buf[6]);
256 tm->tm_year += 100;
257
258 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
259 "mday=%d, mon=%d, year=%d, wday=%d\n",
260 __func__,
261 tm->tm_sec, tm->tm_min, tm->tm_hour,
262 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
263
264 return 0;
265 }
266
267 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
268 {
269 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
270 unsigned char buf[7];
271 int i = 0, err;
272
273 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
274 "mday=%d, mon=%d, year=%d, wday=%d\n",
275 __func__,
276 tm->tm_sec, tm->tm_min, tm->tm_hour,
277 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
278
279 /* hours, minutes and seconds */
280 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */
281 buf[i++] = bin2bcd(tm->tm_min);
282 buf[i++] = bin2bcd(tm->tm_hour);
283 buf[i++] = bin2bcd(tm->tm_mday);
284 buf[i++] = tm->tm_wday & 0x07;
285
286 /* month, 1 - 12 */
287 buf[i++] = bin2bcd(tm->tm_mon + 1);
288
289 /* year */
290 buf[i++] = bin2bcd(tm->tm_year - 100);
291
292 /* Write access to time registers:
293 * PCF2127/29: no special action required.
294 * PCF2131: requires setting the STOP and CPR bits. STOP bit needs to
295 * be cleared after time registers are updated.
296 */
297 if (pcf2127->cfg->type == PCF2131) {
298 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
299 PCF2127_BIT_CTRL1_STOP,
300 PCF2127_BIT_CTRL1_STOP);
301 if (err) {
302 dev_dbg(dev, "setting STOP bit failed\n");
303 return err;
304 }
305
306 err = regmap_write(pcf2127->regmap, PCF2131_REG_SR_RESET,
307 PCF2131_SR_RESET_CPR_CMD);
308 if (err) {
309 dev_dbg(dev, "sending CPR cmd failed\n");
310 return err;
311 }
312 }
313
314 /* write time register's data */
315 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i);
316 if (err) {
317 dev_dbg(dev, "%s: err=%d", __func__, err);
318 return err;
319 }
320
321 if (pcf2127->cfg->type == PCF2131) {
322 /* Clear STOP bit (PCF2131 only) after write is completed. */
323 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
324 PCF2127_BIT_CTRL1_STOP, 0);
325 if (err) {
326 dev_dbg(dev, "clearing STOP bit failed\n");
327 return err;
328 }
329 }
330
331 return 0;
332 }
333
334 static int pcf2127_rtc_ioctl(struct device *dev,
335 unsigned int cmd, unsigned long arg)
336 {
337 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
338 int val, touser = 0;
339 int ret;
340
341 switch (cmd) {
342 case RTC_VL_READ:
343 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val);
344 if (ret)
345 return ret;
346
347 if (val & PCF2127_BIT_CTRL3_BLF)
348 touser |= RTC_VL_BACKUP_LOW;
349
350 if (val & PCF2127_BIT_CTRL3_BF)
351 touser |= RTC_VL_BACKUP_SWITCH;
352
353 return put_user(touser, (unsigned int __user *)arg);
354
355 case RTC_VL_CLR:
356 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
357 PCF2127_BIT_CTRL3_BF, 0);
358
359 default:
360 return -ENOIOCTLCMD;
361 }
362 }
363
364 static int pcf2127_nvmem_read(void *priv, unsigned int offset,
365 void *val, size_t bytes)
366 {
367 struct pcf2127 *pcf2127 = priv;
368 int ret;
369 unsigned char offsetbuf[] = { offset >> 8, offset };
370
371 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
372 offsetbuf, 2);
373 if (ret)
374 return ret;
375
376 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD,
377 val, bytes);
378 }
379
380 static int pcf2127_nvmem_write(void *priv, unsigned int offset,
381 void *val, size_t bytes)
382 {
383 struct pcf2127 *pcf2127 = priv;
384 int ret;
385 unsigned char offsetbuf[] = { offset >> 8, offset };
386
387 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
388 offsetbuf, 2);
389 if (ret)
390 return ret;
391
392 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD,
393 val, bytes);
394 }
395
396 /* watchdog driver */
397
398 static int pcf2127_wdt_ping(struct watchdog_device *wdd)
399 {
400 int wd_val;
401 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
402
403 /*
404 * Compute counter value of WATCHDG_TIM_VAL to obtain desired period
405 * in seconds, depending on the source clock frequency.
406 */
407 wd_val = ((wdd->timeout * pcf2127->cfg->wdd_clock_hz_x1000) / 1000) + 1;
408
409 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wd_val);
410 }
411
412 /*
413 * Restart watchdog timer if feature is active.
414 *
415 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
416 * since register also contain control/status flags for other features.
417 * Always call this function after reading CTRL2 register.
418 */
419 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd)
420 {
421 int ret = 0;
422
423 if (watchdog_active(wdd)) {
424 ret = pcf2127_wdt_ping(wdd);
425 if (ret)
426 dev_err(wdd->parent,
427 "%s: watchdog restart failed, ret=%d\n",
428 __func__, ret);
429 }
430
431 return ret;
432 }
433
434 static int pcf2127_wdt_start(struct watchdog_device *wdd)
435 {
436 return pcf2127_wdt_ping(wdd);
437 }
438
439 static int pcf2127_wdt_stop(struct watchdog_device *wdd)
440 {
441 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
442
443 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
444 PCF2127_WD_VAL_STOP);
445 }
446
447 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
448 unsigned int new_timeout)
449 {
450 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
451 new_timeout, wdd->timeout);
452
453 wdd->timeout = new_timeout;
454
455 return pcf2127_wdt_active_ping(wdd);
456 }
457
458 static const struct watchdog_info pcf2127_wdt_info = {
459 .identity = "NXP PCF2127/PCF2129 Watchdog",
460 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
461 };
462
463 static const struct watchdog_ops pcf2127_watchdog_ops = {
464 .owner = THIS_MODULE,
465 .start = pcf2127_wdt_start,
466 .stop = pcf2127_wdt_stop,
467 .ping = pcf2127_wdt_ping,
468 .set_timeout = pcf2127_wdt_set_timeout,
469 };
470
471 /*
472 * Compute watchdog period, t, in seconds, from the WATCHDG_TIM_VAL register
473 * value, n, and the clock frequency, f1000, in Hz x 1000.
474 *
475 * The PCF2127/29 datasheet gives t as:
476 * t = n / f
477 * The PCF2131 datasheet gives t as:
478 * t = (n - 1) / f
479 * For both variants, the watchdog is triggered when the WATCHDG_TIM_VAL reaches
480 * the value 1, and not zero. Consequently, the equation from the PCF2131
481 * datasheet seems to be the correct one for both variants.
482 */
483 static int pcf2127_watchdog_get_period(int n, int f1000)
484 {
485 return (1000 * (n - 1)) / f1000;
486 }
487
488 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
489 {
490 int ret;
491
492 if (!IS_ENABLED(CONFIG_WATCHDOG) ||
493 !device_property_read_bool(dev, "reset-source"))
494 return 0;
495
496 pcf2127->wdd.parent = dev;
497 pcf2127->wdd.info = &pcf2127_wdt_info;
498 pcf2127->wdd.ops = &pcf2127_watchdog_ops;
499
500 pcf2127->wdd.min_timeout =
501 pcf2127_watchdog_get_period(
502 2, pcf2127->cfg->wdd_clock_hz_x1000);
503 pcf2127->wdd.max_timeout =
504 pcf2127_watchdog_get_period(
505 255, pcf2127->cfg->wdd_clock_hz_x1000);
506 pcf2127->wdd.timeout = PCF2127_WD_DEFAULT_TIMEOUT_S;
507
508 dev_dbg(dev, "%s clock = %d Hz / 1000\n", __func__,
509 pcf2127->cfg->wdd_clock_hz_x1000);
510
511 pcf2127->wdd.min_hw_heartbeat_ms = pcf2127->cfg->wdd_min_hw_heartbeat_ms;
512 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
513
514 watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
515
516 /* Test if watchdog timer is started by bootloader */
517 if (pcf2127->cfg->wd_val_reg_readable) {
518 u32 wdd_timeout;
519
520 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
521 &wdd_timeout);
522 if (ret)
523 return ret;
524
525 if (wdd_timeout)
526 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
527 }
528
529 return devm_watchdog_register_device(dev, &pcf2127->wdd);
530 }
531
532 /* Alarm */
533 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
534 {
535 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
536 u8 buf[5];
537 unsigned int ctrl2;
538 int ret;
539
540 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
541 if (ret)
542 return ret;
543
544 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
545 if (ret)
546 return ret;
547
548 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base,
549 buf, sizeof(buf));
550 if (ret)
551 return ret;
552
553 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE;
554 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF;
555
556 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
557 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F);
558 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F);
559 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F);
560
561 return 0;
562 }
563
564 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable)
565 {
566 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
567 int ret;
568
569 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
570 PCF2127_BIT_CTRL2_AIE,
571 enable ? PCF2127_BIT_CTRL2_AIE : 0);
572 if (ret)
573 return ret;
574
575 return pcf2127_wdt_active_ping(&pcf2127->wdd);
576 }
577
578 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
579 {
580 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
581 uint8_t buf[5];
582 int ret;
583
584 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
585 PCF2127_BIT_CTRL2_AF, 0);
586 if (ret)
587 return ret;
588
589 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
590 if (ret)
591 return ret;
592
593 buf[0] = bin2bcd(alrm->time.tm_sec);
594 buf[1] = bin2bcd(alrm->time.tm_min);
595 buf[2] = bin2bcd(alrm->time.tm_hour);
596 buf[3] = bin2bcd(alrm->time.tm_mday);
597 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */
598
599 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base,
600 buf, sizeof(buf));
601 if (ret)
602 return ret;
603
604 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
605 }
606
607 /*
608 * This function reads one timestamp function data, caller is responsible for
609 * calling pcf2127_wdt_active_ping()
610 */
611 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts,
612 int ts_id)
613 {
614 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
615 struct rtc_time tm;
616 int ret;
617 unsigned char data[7];
618
619 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base,
620 data, sizeof(data));
621 if (ret) {
622 dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
623 return ret;
624 }
625
626 dev_dbg(dev,
627 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
628 __func__, data[1], data[2], data[3], data[4], data[5], data[6]);
629
630 tm.tm_sec = bcd2bin(data[1] & 0x7F);
631 tm.tm_min = bcd2bin(data[2] & 0x7F);
632 tm.tm_hour = bcd2bin(data[3] & 0x3F);
633 tm.tm_mday = bcd2bin(data[4] & 0x3F);
634 /* TS_MO register (month) value range: 1-12 */
635 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
636 tm.tm_year = bcd2bin(data[6]);
637 if (tm.tm_year < 70)
638 tm.tm_year += 100; /* assume we are in 1970...2069 */
639
640 ret = rtc_valid_tm(&tm);
641 if (ret) {
642 dev_err(dev, "Invalid timestamp. ret=%d\n", ret);
643 return ret;
644 }
645
646 *ts = rtc_tm_to_time64(&tm);
647 return 0;
648 };
649
650 static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id)
651 {
652 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
653 int ret;
654
655 if (ts_id >= pcf2127->cfg->ts_count)
656 return;
657
658 /* Let userspace read the first timestamp */
659 if (pcf2127->ts_valid[ts_id])
660 return;
661
662 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id);
663 if (!ret)
664 pcf2127->ts_valid[ts_id] = true;
665 }
666
667 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
668 {
669 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
670 unsigned int ctrl2;
671 int ret = 0;
672
673 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
674 if (ret)
675 return IRQ_NONE;
676
677 if (pcf2127->cfg->ts_count == 1) {
678 /* PCF2127/29 */
679 unsigned int ctrl1;
680
681 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
682 if (ret)
683 return IRQ_NONE;
684
685 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
686 return IRQ_NONE;
687
688 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
689 pcf2127_rtc_ts_snapshot(dev, 0);
690
691 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
692 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
693 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
694
695 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
696 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
697 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
698 } else {
699 /* PCF2131. */
700 unsigned int ctrl4;
701
702 ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4);
703 if (ret)
704 return IRQ_NONE;
705
706 if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK))
707 return IRQ_NONE;
708
709 if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) {
710 int i;
711 int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */
712
713 for (i = 0; i < pcf2127->cfg->ts_count; i++) {
714 if (ctrl4 & tsf_bit)
715 pcf2127_rtc_ts_snapshot(dev, i);
716
717 tsf_bit = tsf_bit >> 1;
718 }
719
720 regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4,
721 ctrl4 & ~PCF2131_CTRL4_IRQ_MASK);
722 }
723
724 if (ctrl2 & PCF2131_CTRL2_IRQ_MASK)
725 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
726 ctrl2 & ~PCF2131_CTRL2_IRQ_MASK);
727 }
728
729 if (ctrl2 & PCF2127_BIT_CTRL2_AF)
730 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
731
732 pcf2127_wdt_active_ping(&pcf2127->wdd);
733
734 return IRQ_HANDLED;
735 }
736
737 static const struct rtc_class_ops pcf2127_rtc_ops = {
738 .ioctl = pcf2127_rtc_ioctl,
739 .read_time = pcf2127_rtc_read_time,
740 .set_time = pcf2127_rtc_set_time,
741 .read_alarm = pcf2127_rtc_read_alarm,
742 .set_alarm = pcf2127_rtc_set_alarm,
743 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
744 };
745
746 /* sysfs interface */
747
748 static ssize_t timestamp_store(struct device *dev,
749 struct device_attribute *attr,
750 const char *buf, size_t count, int ts_id)
751 {
752 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
753 int ret;
754
755 if (ts_id >= pcf2127->cfg->ts_count)
756 return 0;
757
758 if (pcf2127->irq_enabled) {
759 pcf2127->ts_valid[ts_id] = false;
760 } else {
761 /* Always clear GND interrupt bit. */
762 ret = regmap_update_bits(pcf2127->regmap,
763 pcf2127->cfg->ts[ts_id].gnd_detect_reg,
764 pcf2127->cfg->ts[ts_id].gnd_detect_bit,
765 0);
766
767 if (ret) {
768 dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret);
769 return ret;
770 }
771
772 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
773 /* Clear intermediate level interrupt bit if supported. */
774 ret = regmap_update_bits(pcf2127->regmap,
775 pcf2127->cfg->ts[ts_id].inter_detect_reg,
776 pcf2127->cfg->ts[ts_id].inter_detect_bit,
777 0);
778 if (ret) {
779 dev_err(dev, "%s: update TS intermediate level detect ret=%d\n",
780 __func__, ret);
781 return ret;
782 }
783 }
784
785 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
786 if (ret)
787 return ret;
788 }
789
790 return count;
791 }
792
793 static ssize_t timestamp0_store(struct device *dev,
794 struct device_attribute *attr,
795 const char *buf, size_t count)
796 {
797 return timestamp_store(dev, attr, buf, count, 0);
798 };
799
800 static ssize_t timestamp1_store(struct device *dev,
801 struct device_attribute *attr,
802 const char *buf, size_t count)
803 {
804 return timestamp_store(dev, attr, buf, count, 1);
805 };
806
807 static ssize_t timestamp2_store(struct device *dev,
808 struct device_attribute *attr,
809 const char *buf, size_t count)
810 {
811 return timestamp_store(dev, attr, buf, count, 2);
812 };
813
814 static ssize_t timestamp3_store(struct device *dev,
815 struct device_attribute *attr,
816 const char *buf, size_t count)
817 {
818 return timestamp_store(dev, attr, buf, count, 3);
819 };
820
821 static ssize_t timestamp_show(struct device *dev,
822 struct device_attribute *attr, char *buf,
823 int ts_id)
824 {
825 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
826 int ret;
827 time64_t ts;
828
829 if (ts_id >= pcf2127->cfg->ts_count)
830 return 0;
831
832 if (pcf2127->irq_enabled) {
833 if (!pcf2127->ts_valid[ts_id])
834 return 0;
835 ts = pcf2127->ts[ts_id];
836 } else {
837 u8 valid_low = 0;
838 u8 valid_inter = 0;
839 unsigned int ctrl;
840
841 /* Check if TS input pin is driven to GND, supported by all
842 * variants.
843 */
844 ret = regmap_read(pcf2127->regmap,
845 pcf2127->cfg->ts[ts_id].gnd_detect_reg,
846 &ctrl);
847 if (ret)
848 return 0;
849
850 valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit;
851
852 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
853 /* Check if TS input pin is driven to intermediate level
854 * between GND and supply, if supported by variant.
855 */
856 ret = regmap_read(pcf2127->regmap,
857 pcf2127->cfg->ts[ts_id].inter_detect_reg,
858 &ctrl);
859 if (ret)
860 return 0;
861
862 valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit;
863 }
864
865 if (!valid_low && !valid_inter)
866 return 0;
867
868 ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id);
869 if (ret)
870 return 0;
871
872 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
873 if (ret)
874 return ret;
875 }
876 return sprintf(buf, "%llu\n", (unsigned long long)ts);
877 }
878
879 static ssize_t timestamp0_show(struct device *dev,
880 struct device_attribute *attr, char *buf)
881 {
882 return timestamp_show(dev, attr, buf, 0);
883 };
884
885 static ssize_t timestamp1_show(struct device *dev,
886 struct device_attribute *attr, char *buf)
887 {
888 return timestamp_show(dev, attr, buf, 1);
889 };
890
891 static ssize_t timestamp2_show(struct device *dev,
892 struct device_attribute *attr, char *buf)
893 {
894 return timestamp_show(dev, attr, buf, 2);
895 };
896
897 static ssize_t timestamp3_show(struct device *dev,
898 struct device_attribute *attr, char *buf)
899 {
900 return timestamp_show(dev, attr, buf, 3);
901 };
902
903 static DEVICE_ATTR_RW(timestamp0);
904 static DEVICE_ATTR_RW(timestamp1);
905 static DEVICE_ATTR_RW(timestamp2);
906 static DEVICE_ATTR_RW(timestamp3);
907
908 static struct attribute *pcf2127_attrs[] = {
909 &dev_attr_timestamp0.attr,
910 NULL
911 };
912
913 static struct attribute *pcf2131_attrs[] = {
914 &dev_attr_timestamp0.attr,
915 &dev_attr_timestamp1.attr,
916 &dev_attr_timestamp2.attr,
917 &dev_attr_timestamp3.attr,
918 NULL
919 };
920
921 static struct pcf21xx_config pcf21xx_cfg[] = {
922 [PCF2127] = {
923 .type = PCF2127,
924 .max_register = 0x1d,
925 .has_nvmem = 1,
926 .has_bit_wd_ctl_cd0 = 1,
927 .wd_val_reg_readable = 1,
928 .has_int_a_b = 0,
929 .reg_time_base = PCF2127_REG_TIME_BASE,
930 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
931 .reg_wd_ctl = PCF2127_REG_WD_CTL,
932 .reg_wd_val = PCF2127_REG_WD_VAL,
933 .reg_clkout = PCF2127_REG_CLKOUT,
934 .wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000,
935 .wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS,
936 .ts_count = 1,
937 .ts[0] = {
938 .reg_base = PCF2127_REG_TS1_BASE,
939 .gnd_detect_reg = PCF2127_REG_CTRL1,
940 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
941 .inter_detect_reg = PCF2127_REG_CTRL2,
942 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
943 .ie_reg = PCF2127_REG_CTRL2,
944 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
945 },
946 .attribute_group = {
947 .attrs = pcf2127_attrs,
948 },
949 },
950 [PCF2129] = {
951 .type = PCF2129,
952 .max_register = 0x19,
953 .has_nvmem = 0,
954 .has_bit_wd_ctl_cd0 = 0,
955 .wd_val_reg_readable = 1,
956 .has_int_a_b = 0,
957 .reg_time_base = PCF2127_REG_TIME_BASE,
958 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
959 .reg_wd_ctl = PCF2127_REG_WD_CTL,
960 .reg_wd_val = PCF2127_REG_WD_VAL,
961 .reg_clkout = PCF2127_REG_CLKOUT,
962 .wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000,
963 .wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS,
964 .ts_count = 1,
965 .ts[0] = {
966 .reg_base = PCF2127_REG_TS1_BASE,
967 .gnd_detect_reg = PCF2127_REG_CTRL1,
968 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
969 .inter_detect_reg = PCF2127_REG_CTRL2,
970 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
971 .ie_reg = PCF2127_REG_CTRL2,
972 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
973 },
974 .attribute_group = {
975 .attrs = pcf2127_attrs,
976 },
977 },
978 [PCF2131] = {
979 .type = PCF2131,
980 .max_register = 0x36,
981 .has_nvmem = 0,
982 .has_bit_wd_ctl_cd0 = 0,
983 .wd_val_reg_readable = 0,
984 .has_int_a_b = 1,
985 .reg_time_base = PCF2131_REG_TIME_BASE,
986 .regs_alarm_base = PCF2131_REG_ALARM_BASE,
987 .reg_wd_ctl = PCF2131_REG_WD_CTL,
988 .reg_wd_val = PCF2131_REG_WD_VAL,
989 .reg_clkout = PCF2131_REG_CLKOUT,
990 .wdd_clock_hz_x1000 = PCF2131_WD_CLOCK_HZ_X1000,
991 .wdd_min_hw_heartbeat_ms = PCF2131_WD_MIN_HW_HEARTBEAT_MS,
992 .ts_count = 4,
993 .ts[0] = {
994 .reg_base = PCF2131_REG_TS1_BASE,
995 .gnd_detect_reg = PCF2131_REG_CTRL4,
996 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1,
997 .inter_detect_bit = 0,
998 .ie_reg = PCF2131_REG_CTRL5,
999 .ie_bit = PCF2131_BIT_CTRL5_TSIE1,
1000 },
1001 .ts[1] = {
1002 .reg_base = PCF2131_REG_TS2_BASE,
1003 .gnd_detect_reg = PCF2131_REG_CTRL4,
1004 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2,
1005 .inter_detect_bit = 0,
1006 .ie_reg = PCF2131_REG_CTRL5,
1007 .ie_bit = PCF2131_BIT_CTRL5_TSIE2,
1008 },
1009 .ts[2] = {
1010 .reg_base = PCF2131_REG_TS3_BASE,
1011 .gnd_detect_reg = PCF2131_REG_CTRL4,
1012 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3,
1013 .inter_detect_bit = 0,
1014 .ie_reg = PCF2131_REG_CTRL5,
1015 .ie_bit = PCF2131_BIT_CTRL5_TSIE3,
1016 },
1017 .ts[3] = {
1018 .reg_base = PCF2131_REG_TS4_BASE,
1019 .gnd_detect_reg = PCF2131_REG_CTRL4,
1020 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4,
1021 .inter_detect_bit = 0,
1022 .ie_reg = PCF2131_REG_CTRL5,
1023 .ie_bit = PCF2131_BIT_CTRL5_TSIE4,
1024 },
1025 .attribute_group = {
1026 .attrs = pcf2131_attrs,
1027 },
1028 },
1029 };
1030
1031 /*
1032 * Enable timestamp function and corresponding interrupt(s).
1033 */
1034 static int pcf2127_enable_ts(struct device *dev, int ts_id)
1035 {
1036 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
1037 int ret;
1038
1039 if (ts_id >= pcf2127->cfg->ts_count) {
1040 dev_err(dev, "%s: invalid tamper detection ID (%d)\n",
1041 __func__, ts_id);
1042 return -EINVAL;
1043 }
1044
1045 /* Enable timestamp function. */
1046 ret = regmap_update_bits(pcf2127->regmap,
1047 pcf2127->cfg->ts[ts_id].reg_base,
1048 PCF2127_BIT_TS_CTRL_TSOFF |
1049 PCF2127_BIT_TS_CTRL_TSM,
1050 PCF2127_BIT_TS_CTRL_TSM);
1051 if (ret) {
1052 dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n",
1053 __func__, ts_id);
1054 return ret;
1055 }
1056
1057 /*
1058 * Enable interrupt generation when TSF timestamp flag is set.
1059 * Interrupt signals are open-drain outputs and can be left floating if
1060 * unused.
1061 */
1062 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg,
1063 pcf2127->cfg->ts[ts_id].ie_bit,
1064 pcf2127->cfg->ts[ts_id].ie_bit);
1065 if (ret) {
1066 dev_err(dev, "%s: tamper detection TSIE%d config failed\n",
1067 __func__, ts_id);
1068 return ret;
1069 }
1070
1071 return ret;
1072 }
1073
1074 /* Route all interrupt sources to INT A pin. */
1075 static int pcf2127_configure_interrupt_pins(struct device *dev)
1076 {
1077 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
1078 int ret;
1079
1080 /* Mask bits need to be cleared to enable corresponding
1081 * interrupt source.
1082 */
1083 ret = regmap_write(pcf2127->regmap,
1084 PCF2131_REG_INT_A_MASK1, 0);
1085 if (ret)
1086 return ret;
1087
1088 ret = regmap_write(pcf2127->regmap,
1089 PCF2131_REG_INT_A_MASK2, 0);
1090 if (ret)
1091 return ret;
1092
1093 return ret;
1094 }
1095
1096 static int pcf2127_probe(struct device *dev, struct regmap *regmap,
1097 int alarm_irq, const struct pcf21xx_config *config)
1098 {
1099 struct pcf2127 *pcf2127;
1100 int ret = 0;
1101 unsigned int val;
1102
1103 dev_dbg(dev, "%s\n", __func__);
1104
1105 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL);
1106 if (!pcf2127)
1107 return -ENOMEM;
1108
1109 pcf2127->regmap = regmap;
1110 pcf2127->cfg = config;
1111
1112 dev_set_drvdata(dev, pcf2127);
1113
1114 pcf2127->rtc = devm_rtc_allocate_device(dev);
1115 if (IS_ERR(pcf2127->rtc))
1116 return PTR_ERR(pcf2127->rtc);
1117
1118 pcf2127->rtc->ops = &pcf2127_rtc_ops;
1119 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
1120 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099;
1121 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
1122
1123 /*
1124 * PCF2127/29 do not work correctly when setting alarms at 1s intervals.
1125 * PCF2131 is ok.
1126 */
1127 if (pcf2127->cfg->type == PCF2127 || pcf2127->cfg->type == PCF2129) {
1128 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features);
1129 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features);
1130 }
1131
1132 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
1133
1134 if (alarm_irq > 0) {
1135 unsigned long flags;
1136
1137 /*
1138 * If flags = 0, devm_request_threaded_irq() will use IRQ flags
1139 * obtained from device tree.
1140 */
1141 if (dev_fwnode(dev))
1142 flags = 0;
1143 else
1144 flags = IRQF_TRIGGER_LOW;
1145
1146 ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
1147 pcf2127_rtc_irq,
1148 flags | IRQF_ONESHOT,
1149 dev_name(dev), dev);
1150 if (ret) {
1151 dev_err(dev, "failed to request alarm irq\n");
1152 return ret;
1153 }
1154 pcf2127->irq_enabled = true;
1155 }
1156
1157 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
1158 device_init_wakeup(dev, true);
1159 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
1160 }
1161
1162 if (pcf2127->cfg->has_int_a_b) {
1163 /* Configure int A/B pins, independently of alarm_irq. */
1164 ret = pcf2127_configure_interrupt_pins(dev);
1165 if (ret) {
1166 dev_err(dev, "failed to configure interrupt pins\n");
1167 return ret;
1168 }
1169 }
1170
1171 if (pcf2127->cfg->has_nvmem) {
1172 struct nvmem_config nvmem_cfg = {
1173 .priv = pcf2127,
1174 .reg_read = pcf2127_nvmem_read,
1175 .reg_write = pcf2127_nvmem_write,
1176 .size = 512,
1177 };
1178
1179 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
1180 }
1181
1182 /*
1183 * The "Power-On Reset Override" facility prevents the RTC to do a reset
1184 * after power on. For normal operation the PORO must be disabled.
1185 */
1186 ret = regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
1187 PCF2127_BIT_CTRL1_POR_OVRD);
1188 if (ret < 0)
1189 return ret;
1190
1191 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val);
1192 if (ret < 0)
1193 return ret;
1194
1195 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) {
1196 ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout,
1197 PCF2127_BIT_CLKOUT_OTPR);
1198 if (ret < 0)
1199 return ret;
1200
1201 msleep(100);
1202 }
1203
1204 /*
1205 * Watchdog timer enabled and reset pin /RST activated when timed out.
1206 * Select 1Hz clock source for watchdog timer (1/4Hz for PCF2131).
1207 * Note: Countdown timer disabled and not available.
1208 * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD
1209 * of register watchdg_tim_ctl. The bit[6] is labeled
1210 * as T. Bits labeled as T must always be written with
1211 * logic 0.
1212 */
1213 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl,
1214 PCF2127_BIT_WD_CTL_CD1 |
1215 PCF2127_BIT_WD_CTL_CD0 |
1216 PCF2127_BIT_WD_CTL_TF1 |
1217 PCF2127_BIT_WD_CTL_TF0,
1218 PCF2127_BIT_WD_CTL_CD1 |
1219 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) |
1220 PCF2127_BIT_WD_CTL_TF1);
1221 if (ret) {
1222 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
1223 return ret;
1224 }
1225
1226 pcf2127_watchdog_init(dev, pcf2127);
1227
1228 /*
1229 * Disable battery low/switch-over timestamp and interrupts.
1230 * Clear battery interrupt flags which can block new trigger events.
1231 * Note: This is the default chip behaviour but added to ensure
1232 * correct tamper timestamp and interrupt function.
1233 */
1234 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
1235 PCF2127_BIT_CTRL3_BTSE |
1236 PCF2127_BIT_CTRL3_BIE |
1237 PCF2127_BIT_CTRL3_BLIE, 0);
1238 if (ret) {
1239 dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
1240 __func__);
1241 return ret;
1242 }
1243
1244 /*
1245 * Enable timestamp functions 1 to 4.
1246 */
1247 for (int i = 0; i < pcf2127->cfg->ts_count; i++) {
1248 ret = pcf2127_enable_ts(dev, i);
1249 if (ret)
1250 return ret;
1251 }
1252
1253 ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group);
1254 if (ret) {
1255 dev_err(dev, "%s: tamper sysfs registering failed\n",
1256 __func__);
1257 return ret;
1258 }
1259
1260 return devm_rtc_register_device(pcf2127->rtc);
1261 }
1262
1263 #ifdef CONFIG_OF
1264 static const struct of_device_id pcf2127_of_match[] = {
1265 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] },
1266 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] },
1267 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] },
1268 { .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] },
1269 {}
1270 };
1271 MODULE_DEVICE_TABLE(of, pcf2127_of_match);
1272 #endif
1273
1274 #if IS_ENABLED(CONFIG_I2C)
1275
1276 static int pcf2127_i2c_write(void *context, const void *data, size_t count)
1277 {
1278 struct device *dev = context;
1279 struct i2c_client *client = to_i2c_client(dev);
1280 int ret;
1281
1282 ret = i2c_master_send(client, data, count);
1283 if (ret != count)
1284 return ret < 0 ? ret : -EIO;
1285
1286 return 0;
1287 }
1288
1289 static int pcf2127_i2c_gather_write(void *context,
1290 const void *reg, size_t reg_size,
1291 const void *val, size_t val_size)
1292 {
1293 struct device *dev = context;
1294 struct i2c_client *client = to_i2c_client(dev);
1295 int ret;
1296 void *buf;
1297
1298 if (WARN_ON(reg_size != 1))
1299 return -EINVAL;
1300
1301 buf = kmalloc(val_size + 1, GFP_KERNEL);
1302 if (!buf)
1303 return -ENOMEM;
1304
1305 memcpy(buf, reg, 1);
1306 memcpy(buf + 1, val, val_size);
1307
1308 ret = i2c_master_send(client, buf, val_size + 1);
1309
1310 kfree(buf);
1311
1312 if (ret != val_size + 1)
1313 return ret < 0 ? ret : -EIO;
1314
1315 return 0;
1316 }
1317
1318 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size,
1319 void *val, size_t val_size)
1320 {
1321 struct device *dev = context;
1322 struct i2c_client *client = to_i2c_client(dev);
1323 int ret;
1324
1325 if (WARN_ON(reg_size != 1))
1326 return -EINVAL;
1327
1328 ret = i2c_master_send(client, reg, 1);
1329 if (ret != 1)
1330 return ret < 0 ? ret : -EIO;
1331
1332 ret = i2c_master_recv(client, val, val_size);
1333 if (ret != val_size)
1334 return ret < 0 ? ret : -EIO;
1335
1336 return 0;
1337 }
1338
1339 /*
1340 * The reason we need this custom regmap_bus instead of using regmap_init_i2c()
1341 * is that the STOP condition is required between set register address and
1342 * read register data when reading from registers.
1343 */
1344 static const struct regmap_bus pcf2127_i2c_regmap = {
1345 .write = pcf2127_i2c_write,
1346 .gather_write = pcf2127_i2c_gather_write,
1347 .read = pcf2127_i2c_read,
1348 };
1349
1350 static struct i2c_driver pcf2127_i2c_driver;
1351
1352 static const struct i2c_device_id pcf2127_i2c_id[] = {
1353 { "pcf2127", PCF2127 },
1354 { "pcf2129", PCF2129 },
1355 { "pca2129", PCF2129 },
1356 { "pcf2131", PCF2131 },
1357 { }
1358 };
1359 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
1360
1361 static int pcf2127_i2c_probe(struct i2c_client *client)
1362 {
1363 struct regmap *regmap;
1364 static struct regmap_config config = {
1365 .reg_bits = 8,
1366 .val_bits = 8,
1367 };
1368 const struct pcf21xx_config *variant;
1369
1370 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
1371 return -ENODEV;
1372
1373 if (client->dev.of_node) {
1374 variant = of_device_get_match_data(&client->dev);
1375 if (!variant)
1376 return -ENODEV;
1377 } else {
1378 enum pcf21xx_type type =
1379 i2c_match_id(pcf2127_i2c_id, client)->driver_data;
1380
1381 if (type >= PCF21XX_LAST_ID)
1382 return -ENODEV;
1383 variant = &pcf21xx_cfg[type];
1384 }
1385
1386 config.max_register = variant->max_register,
1387
1388 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap,
1389 &client->dev, &config);
1390 if (IS_ERR(regmap)) {
1391 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
1392 __func__, PTR_ERR(regmap));
1393 return PTR_ERR(regmap);
1394 }
1395
1396 return pcf2127_probe(&client->dev, regmap, client->irq, variant);
1397 }
1398
1399 static struct i2c_driver pcf2127_i2c_driver = {
1400 .driver = {
1401 .name = "rtc-pcf2127-i2c",
1402 .of_match_table = of_match_ptr(pcf2127_of_match),
1403 },
1404 .probe = pcf2127_i2c_probe,
1405 .id_table = pcf2127_i2c_id,
1406 };
1407
1408 static int pcf2127_i2c_register_driver(void)
1409 {
1410 return i2c_add_driver(&pcf2127_i2c_driver);
1411 }
1412
1413 static void pcf2127_i2c_unregister_driver(void)
1414 {
1415 i2c_del_driver(&pcf2127_i2c_driver);
1416 }
1417
1418 #else
1419
1420 static int pcf2127_i2c_register_driver(void)
1421 {
1422 return 0;
1423 }
1424
1425 static void pcf2127_i2c_unregister_driver(void)
1426 {
1427 }
1428
1429 #endif
1430
1431 #if IS_ENABLED(CONFIG_SPI_MASTER)
1432
1433 static struct spi_driver pcf2127_spi_driver;
1434 static const struct spi_device_id pcf2127_spi_id[];
1435
1436 static int pcf2127_spi_probe(struct spi_device *spi)
1437 {
1438 static struct regmap_config config = {
1439 .reg_bits = 8,
1440 .val_bits = 8,
1441 .read_flag_mask = 0xa0,
1442 .write_flag_mask = 0x20,
1443 };
1444 struct regmap *regmap;
1445 const struct pcf21xx_config *variant;
1446
1447 if (spi->dev.of_node) {
1448 variant = of_device_get_match_data(&spi->dev);
1449 if (!variant)
1450 return -ENODEV;
1451 } else {
1452 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data;
1453
1454 if (type >= PCF21XX_LAST_ID)
1455 return -ENODEV;
1456 variant = &pcf21xx_cfg[type];
1457 }
1458
1459 config.max_register = variant->max_register,
1460
1461 regmap = devm_regmap_init_spi(spi, &config);
1462 if (IS_ERR(regmap)) {
1463 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
1464 __func__, PTR_ERR(regmap));
1465 return PTR_ERR(regmap);
1466 }
1467
1468 return pcf2127_probe(&spi->dev, regmap, spi->irq, variant);
1469 }
1470
1471 static const struct spi_device_id pcf2127_spi_id[] = {
1472 { "pcf2127", PCF2127 },
1473 { "pcf2129", PCF2129 },
1474 { "pca2129", PCF2129 },
1475 { "pcf2131", PCF2131 },
1476 { }
1477 };
1478 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
1479
1480 static struct spi_driver pcf2127_spi_driver = {
1481 .driver = {
1482 .name = "rtc-pcf2127-spi",
1483 .of_match_table = of_match_ptr(pcf2127_of_match),
1484 },
1485 .probe = pcf2127_spi_probe,
1486 .id_table = pcf2127_spi_id,
1487 };
1488
1489 static int pcf2127_spi_register_driver(void)
1490 {
1491 return spi_register_driver(&pcf2127_spi_driver);
1492 }
1493
1494 static void pcf2127_spi_unregister_driver(void)
1495 {
1496 spi_unregister_driver(&pcf2127_spi_driver);
1497 }
1498
1499 #else
1500
1501 static int pcf2127_spi_register_driver(void)
1502 {
1503 return 0;
1504 }
1505
1506 static void pcf2127_spi_unregister_driver(void)
1507 {
1508 }
1509
1510 #endif
1511
1512 static int __init pcf2127_init(void)
1513 {
1514 int ret;
1515
1516 ret = pcf2127_i2c_register_driver();
1517 if (ret) {
1518 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret);
1519 return ret;
1520 }
1521
1522 ret = pcf2127_spi_register_driver();
1523 if (ret) {
1524 pr_err("Failed to register pcf2127 spi driver: %d\n", ret);
1525 pcf2127_i2c_unregister_driver();
1526 }
1527
1528 return ret;
1529 }
1530 module_init(pcf2127_init)
1531
1532 static void __exit pcf2127_exit(void)
1533 {
1534 pcf2127_spi_unregister_driver();
1535 pcf2127_i2c_unregister_driver();
1536 }
1537 module_exit(pcf2127_exit)
1538
1539 MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
1540 MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver");
1541 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes