drivers/rtc/rtc-pcf85063.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * An I2C driver for the PCF85063 RTC
   4  * Copyright 2014 Rose Technology
   5  *
   6  * Author: Søren Andersen <san@rosetechnology.dk>
   7  * Maintainers: http://www.nslu2-linux.org/
   8  *
   9  * Copyright (C) 2019 Micro Crystal AG
  10  * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
  11  */
  12 #include <linux/clk-provider.h>
  13 #include <linux/i2c.h>
  14 #include <linux/bcd.h>
  15 #include <linux/rtc.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/pm_wakeirq.h>
  19 #include <linux/regmap.h>
  20
  21 /*
  22  * Information for this driver was pulled from the following datasheets.
  23  *
  24  *  https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
  25  *  https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
  26  *
  27  *  PCF85063A -- Rev. 7 — 30 March 2018
  28  *  PCF85063TP -- Rev. 4 — 6 May 2015
  29  *
  30  *  https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
  31  *  RV8263 -- Rev. 1.0 — January 2019
  32  */
  33
  34 #define PCF85063_REG_CTRL1              0x00 /* status */
  35 #define PCF85063_REG_CTRL1_CAP_SEL      BIT(0)
  36 #define PCF85063_REG_CTRL1_STOP         BIT(5)
  37 #define PCF85063_REG_CTRL1_EXT_TEST     BIT(7)
  38
  39 #define PCF85063_REG_CTRL2              0x01
  40 #define PCF85063_CTRL2_AF               BIT(6)
  41 #define PCF85063_CTRL2_AIE              BIT(7)
  42
  43 #define PCF85063_REG_OFFSET             0x02
  44 #define PCF85063_OFFSET_SIGN_BIT        6       /* 2's complement sign bit */
  45 #define PCF85063_OFFSET_MODE            BIT(7)
  46 #define PCF85063_OFFSET_STEP0           4340
  47 #define PCF85063_OFFSET_STEP1           4069
  48
  49 #define PCF85063_REG_CLKO_F_MASK        0x07 /* frequency mask */
  50 #define PCF85063_REG_CLKO_F_32768HZ     0x00
  51 #define PCF85063_REG_CLKO_F_OFF         0x07
  52
  53 #define PCF85063_REG_RAM                0x03
  54
  55 #define PCF85063_REG_SC                 0x04 /* datetime */
  56 #define PCF85063_REG_SC_OS              0x80
  57
  58 #define PCF85063_REG_ALM_S              0x0b
  59 #define PCF85063_AEN                    BIT(7)
  60
  61 struct pcf85063_config {
  62         struct regmap_config regmap;
  63         unsigned has_alarms:1;
  64         unsigned force_cap_7000:1;
  65 };
  66
  67 struct pcf85063 {
  68         struct rtc_device       *rtc;
  69         struct regmap           *regmap;
  70 #ifdef CONFIG_COMMON_CLK
  71         struct clk_hw           clkout_hw;
  72 #endif
  73 };
  74
  75 static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
  76 {
  77         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
  78         int rc;
  79         u8 regs[7];
  80
  81         /*
  82          * while reading, the time/date registers are blocked and not updated
  83          * anymore until the access is finished. To not lose a second
  84          * event, the access must be finished within one second. So, read all
  85          * time/date registers in one turn.
  86          */
  87         rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
  88                               sizeof(regs));
  89         if (rc)
  90                 return rc;
  91
  92         /* if the clock has lost its power it makes no sense to use its time */
  93         if (regs[0] & PCF85063_REG_SC_OS) {
  94                 dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
  95                 return -EINVAL;
  96         }
  97
  98         tm->tm_sec = bcd2bin(regs[0] & 0x7F);
  99         tm->tm_min = bcd2bin(regs[1] & 0x7F);
 100         tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
 101         tm->tm_mday = bcd2bin(regs[3] & 0x3F);
 102         tm->tm_wday = regs[4] & 0x07;
 103         tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
 104         tm->tm_year = bcd2bin(regs[6]);
 105         tm->tm_year += 100;
 106
 107         return 0;
 108 }
 109
 110 static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
 111 {
 112         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 113         int rc;
 114         u8 regs[7];
 115
 116         /*
 117          * to accurately set the time, reset the divider chain and keep it in
 118          * reset state until all time/date registers are written
 119          */
 120         rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
 121                                 PCF85063_REG_CTRL1_EXT_TEST |
 122                                 PCF85063_REG_CTRL1_STOP,
 123                                 PCF85063_REG_CTRL1_STOP);
 124         if (rc)
 125                 return rc;
 126
 127         /* hours, minutes and seconds */
 128         regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
 129
 130         regs[1] = bin2bcd(tm->tm_min);
 131         regs[2] = bin2bcd(tm->tm_hour);
 132
 133         /* Day of month, 1 - 31 */
 134         regs[3] = bin2bcd(tm->tm_mday);
 135
 136         /* Day, 0 - 6 */
 137         regs[4] = tm->tm_wday & 0x07;
 138
 139         /* month, 1 - 12 */
 140         regs[5] = bin2bcd(tm->tm_mon + 1);
 141
 142         /* year and century */
 143         regs[6] = bin2bcd(tm->tm_year - 100);
 144
 145         /* write all registers at once */
 146         rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
 147                                regs, sizeof(regs));
 148         if (rc)
 149                 return rc;
 150
 151         /*
 152          * Write the control register as a separate action since the size of
 153          * the register space is different between the PCF85063TP and
 154          * PCF85063A devices.  The rollover point can not be used.
 155          */
 156         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
 157                                   PCF85063_REG_CTRL1_STOP, 0);
 158 }
 159
 160 static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 161 {
 162         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 163         u8 buf[4];
 164         unsigned int val;
 165         int ret;
 166
 167         ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
 168                                buf, sizeof(buf));
 169         if (ret)
 170                 return ret;
 171
 172         alrm->time.tm_sec = bcd2bin(buf[0] & 0x7f);
 173         alrm->time.tm_min = bcd2bin(buf[1] & 0x7f);
 174         alrm->time.tm_hour = bcd2bin(buf[2] & 0x3f);
 175         alrm->time.tm_mday = bcd2bin(buf[3] & 0x3f);
 176
 177         ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
 178         if (ret)
 179                 return ret;
 180
 181         alrm->enabled =  !!(val & PCF85063_CTRL2_AIE);
 182
 183         return 0;
 184 }
 185
 186 static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 187 {
 188         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 189         u8 buf[5];
 190         int ret;
 191
 192         buf[0] = bin2bcd(alrm->time.tm_sec);
 193         buf[1] = bin2bcd(alrm->time.tm_min);
 194         buf[2] = bin2bcd(alrm->time.tm_hour);
 195         buf[3] = bin2bcd(alrm->time.tm_mday);
 196         buf[4] = PCF85063_AEN; /* Do not match on week day */
 197
 198         ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 199                                  PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
 200         if (ret)
 201                 return ret;
 202
 203         ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
 204                                 buf, sizeof(buf));
 205         if (ret)
 206                 return ret;
 207
 208         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 209                                   PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
 210                                   alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
 211 }
 212
 213 static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
 214                                          unsigned int enabled)
 215 {
 216         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 217
 218         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 219                                   PCF85063_CTRL2_AIE,
 220                                   enabled ? PCF85063_CTRL2_AIE : 0);
 221 }
 222
 223 static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
 224 {
 225         struct pcf85063 *pcf85063 = dev_id;
 226         unsigned int val;
 227         int err;
 228
 229         err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
 230         if (err)
 231                 return IRQ_NONE;
 232
 233         if (val & PCF85063_CTRL2_AF) {
 234                 rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
 235                 regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 236                                    PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
 237                                    0);
 238                 return IRQ_HANDLED;
 239         }
 240
 241         return IRQ_NONE;
 242 }
 243
 244 static int pcf85063_read_offset(struct device *dev, long *offset)
 245 {
 246         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 247         long val;
 248         u32 reg;
 249         int ret;
 250
 251         ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
 252         if (ret < 0)
 253                 return ret;
 254
 255         val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
 256                             PCF85063_OFFSET_SIGN_BIT);
 257
 258         if (reg & PCF85063_OFFSET_MODE)
 259                 *offset = val * PCF85063_OFFSET_STEP1;
 260         else
 261                 *offset = val * PCF85063_OFFSET_STEP0;
 262
 263         return 0;
 264 }
 265
 266 static int pcf85063_set_offset(struct device *dev, long offset)
 267 {
 268         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 269         s8 mode0, mode1, reg;
 270         unsigned int error0, error1;
 271
 272         if (offset > PCF85063_OFFSET_STEP0 * 63)
 273                 return -ERANGE;
 274         if (offset < PCF85063_OFFSET_STEP0 * -64)
 275                 return -ERANGE;
 276
 277         mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
 278         mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
 279
 280         error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
 281         error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
 282         if (mode1 > 63 || mode1 < -64 || error0 < error1)
 283                 reg = mode0 & ~PCF85063_OFFSET_MODE;
 284         else
 285                 reg = mode1 | PCF85063_OFFSET_MODE;
 286
 287         return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
 288 }
 289
 290 static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
 291                           unsigned long arg)
 292 {
 293         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 294         int status, ret = 0;
 295
 296         switch (cmd) {
 297         case RTC_VL_READ:
 298                 ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
 299                 if (ret < 0)
 300                         return ret;
 301
 302                 status = (status & PCF85063_REG_SC_OS) ? RTC_VL_DATA_INVALID : 0;
 303
 304                 return put_user(status, (unsigned int __user *)arg);
 305
 306         default:
 307                 return -ENOIOCTLCMD;
 308         }
 309 }
 310
 311 static const struct rtc_class_ops pcf85063_rtc_ops = {
 312         .read_time      = pcf85063_rtc_read_time,
 313         .set_time       = pcf85063_rtc_set_time,
 314         .read_offset    = pcf85063_read_offset,
 315         .set_offset     = pcf85063_set_offset,
 316         .read_alarm     = pcf85063_rtc_read_alarm,
 317         .set_alarm      = pcf85063_rtc_set_alarm,
 318         .alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
 319         .ioctl          = pcf85063_ioctl,
 320 };
 321
 322 static int pcf85063_nvmem_read(void *priv, unsigned int offset,
 323                                void *val, size_t bytes)
 324 {
 325         return regmap_read(priv, PCF85063_REG_RAM, val);
 326 }
 327
 328 static int pcf85063_nvmem_write(void *priv, unsigned int offset,
 329                                 void *val, size_t bytes)
 330 {
 331         return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
 332 }
 333
 334 static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
 335                                      const struct device_node *np,
 336                                      unsigned int force_cap)
 337 {
 338         u32 load = 7000;
 339         u8 reg = 0;
 340
 341         if (force_cap)
 342                 load = force_cap;
 343         else
 344                 of_property_read_u32(np, "quartz-load-femtofarads", &load);
 345
 346         switch (load) {
 347         default:
 348                 dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
 349                          load);
 350                 fallthrough;
 351         case 7000:
 352                 break;
 353         case 12500:
 354                 reg = PCF85063_REG_CTRL1_CAP_SEL;
 355                 break;
 356         }
 357
 358         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
 359                                   PCF85063_REG_CTRL1_CAP_SEL, reg);
 360 }
 361
 362 #ifdef CONFIG_COMMON_CLK
 363 /*
 364  * Handling of the clkout
 365  */
 366
 367 #define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
 368
 369 static int clkout_rates[] = {
 370         32768,
 371         16384,
 372         8192,
 373         4096,
 374         2048,
 375         1024,
 376         1,
 377         0
 378 };
 379
 380 static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
 381                                                  unsigned long parent_rate)
 382 {
 383         struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
 384         unsigned int buf;
 385         int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
 386
 387         if (ret < 0)
 388                 return 0;
 389
 390         buf &= PCF85063_REG_CLKO_F_MASK;
 391         return clkout_rates[buf];
 392 }
 393
 394 static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
 395                                        unsigned long *prate)
 396 {
 397         int i;
 398
 399         for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
 400                 if (clkout_rates[i] <= rate)
 401                         return clkout_rates[i];
 402
 403         return 0;
 404 }
 405
 406 static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
 407                                     unsigned long parent_rate)
 408 {
 409         struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
 410         int i;
 411
 412         for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
 413                 if (clkout_rates[i] == rate)
 414                         return regmap_update_bits(pcf85063->regmap,
 415                                 PCF85063_REG_CTRL2,
 416                                 PCF85063_REG_CLKO_F_MASK, i);
 417
 418         return -EINVAL;
 419 }
 420
 421 static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
 422 {
 423         struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
 424         unsigned int buf;
 425         int ret;
 426
 427         ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
 428         if (ret < 0)
 429                 return ret;
 430         buf &= PCF85063_REG_CLKO_F_MASK;
 431
 432         if (enable) {
 433                 if (buf == PCF85063_REG_CLKO_F_OFF)
 434                         buf = PCF85063_REG_CLKO_F_32768HZ;
 435                 else
 436                         return 0;
 437         } else {
 438                 if (buf != PCF85063_REG_CLKO_F_OFF)
 439                         buf = PCF85063_REG_CLKO_F_OFF;
 440                 else
 441                         return 0;
 442         }
 443
 444         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 445                                         PCF85063_REG_CLKO_F_MASK, buf);
 446 }
 447
 448 static int pcf85063_clkout_prepare(struct clk_hw *hw)
 449 {
 450         return pcf85063_clkout_control(hw, 1);
 451 }
 452
 453 static void pcf85063_clkout_unprepare(struct clk_hw *hw)
 454 {
 455         pcf85063_clkout_control(hw, 0);
 456 }
 457
 458 static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
 459 {
 460         struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
 461         unsigned int buf;
 462         int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
 463
 464         if (ret < 0)
 465                 return 0;
 466
 467         return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
 468 }
 469
 470 static const struct clk_ops pcf85063_clkout_ops = {
 471         .prepare = pcf85063_clkout_prepare,
 472         .unprepare = pcf85063_clkout_unprepare,
 473         .is_prepared = pcf85063_clkout_is_prepared,
 474         .recalc_rate = pcf85063_clkout_recalc_rate,
 475         .round_rate = pcf85063_clkout_round_rate,
 476         .set_rate = pcf85063_clkout_set_rate,
 477 };
 478
 479 static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
 480 {
 481         struct clk *clk;
 482         struct clk_init_data init;
 483         struct device_node *node = pcf85063->rtc->dev.parent->of_node;
 484         struct device_node *fixed_clock;
 485
 486         fixed_clock = of_get_child_by_name(node, "clock");
 487         if (fixed_clock) {
 488                 /*
 489                  * skip registering square wave clock when a fixed
 490                  * clock has been registered. The fixed clock is
 491                  * registered automatically when being referenced.
 492                  */
 493                 of_node_put(fixed_clock);
 494                 return NULL;
 495         }
 496
 497         init.name = "pcf85063-clkout";
 498         init.ops = &pcf85063_clkout_ops;
 499         init.flags = 0;
 500         init.parent_names = NULL;
 501         init.num_parents = 0;
 502         pcf85063->clkout_hw.init = &init;
 503
 504         /* optional override of the clockname */
 505         of_property_read_string(node, "clock-output-names", &init.name);
 506
 507         /* register the clock */
 508         clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
 509
 510         if (!IS_ERR(clk))
 511                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 512
 513         return clk;
 514 }
 515 #endif
 516
 517 static const struct pcf85063_config config_pcf85063 = {
 518         .regmap = {
 519                 .reg_bits = 8,
 520                 .val_bits = 8,
 521                 .max_register = 0x0a,
 522         },
 523 };
 524
 525 static const struct pcf85063_config config_pcf85063tp = {
 526         .regmap = {
 527                 .reg_bits = 8,
 528                 .val_bits = 8,
 529                 .max_register = 0x0a,
 530         },
 531 };
 532
 533 static const struct pcf85063_config config_pcf85063a = {
 534         .regmap = {
 535                 .reg_bits = 8,
 536                 .val_bits = 8,
 537                 .max_register = 0x11,
 538         },
 539         .has_alarms = 1,
 540 };
 541
 542 static const struct pcf85063_config config_rv8263 = {
 543         .regmap = {
 544                 .reg_bits = 8,
 545                 .val_bits = 8,
 546                 .max_register = 0x11,
 547         },
 548         .has_alarms = 1,
 549         .force_cap_7000 = 1,
 550 };
 551
 552 static int pcf85063_probe(struct i2c_client *client)
 553 {
 554         struct pcf85063 *pcf85063;
 555         unsigned int tmp;
 556         int err;
 557         const struct pcf85063_config *config;
 558         struct nvmem_config nvmem_cfg = {
 559                 .name = "pcf85063_nvram",
 560                 .reg_read = pcf85063_nvmem_read,
 561                 .reg_write = pcf85063_nvmem_write,
 562                 .type = NVMEM_TYPE_BATTERY_BACKED,
 563                 .size = 1,
 564         };
 565
 566         dev_dbg(&client->dev, "%s\n", __func__);
 567
 568         pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
 569                                 GFP_KERNEL);
 570         if (!pcf85063)
 571                 return -ENOMEM;
 572
 573         config = i2c_get_match_data(client);
 574         if (!config)
 575                 return -ENODEV;
 576
 577         pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
 578         if (IS_ERR(pcf85063->regmap))
 579                 return PTR_ERR(pcf85063->regmap);
 580
 581         i2c_set_clientdata(client, pcf85063);
 582
 583         err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
 584         if (err) {
 585                 dev_err(&client->dev, "RTC chip is not present\n");
 586                 return err;
 587         }
 588
 589         pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
 590         if (IS_ERR(pcf85063->rtc))
 591                 return PTR_ERR(pcf85063->rtc);
 592
 593         err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
 594                                         config->force_cap_7000 ? 7000 : 0);
 595         if (err < 0)
 596                 dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
 597                          err);
 598
 599         pcf85063->rtc->ops = &pcf85063_rtc_ops;
 600         pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
 601         pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
 602         set_bit(RTC_FEATURE_ALARM_RES_2S, pcf85063->rtc->features);
 603         clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85063->rtc->features);
 604         clear_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
 605
 606         if (config->has_alarms && client->irq > 0) {
 607                 unsigned long irqflags = IRQF_TRIGGER_LOW;
 608
 609                 if (dev_fwnode(&client->dev))
 610                         irqflags = 0;
 611
 612                 err = devm_request_threaded_irq(&client->dev, client->irq,
 613                                                 NULL, pcf85063_rtc_handle_irq,
 614                                                 irqflags | IRQF_ONESHOT,
 615                                                 "pcf85063", pcf85063);
 616                 if (err) {
 617                         dev_warn(&pcf85063->rtc->dev,
 618                                  "unable to request IRQ, alarms disabled\n");
 619                 } else {
 620                         set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
 621                         device_init_wakeup(&client->dev, true);
 622                         err = dev_pm_set_wake_irq(&client->dev, client->irq);
 623                         if (err)
 624                                 dev_err(&pcf85063->rtc->dev,
 625                                         "failed to enable irq wake\n");
 626                 }
 627         }
 628
 629         nvmem_cfg.priv = pcf85063->regmap;
 630         devm_rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
 631
 632 #ifdef CONFIG_COMMON_CLK
 633         /* register clk in common clk framework */
 634         pcf85063_clkout_register_clk(pcf85063);
 635 #endif
 636
 637         return devm_rtc_register_device(pcf85063->rtc);
 638 }
 639
 640 static const struct i2c_device_id pcf85063_ids[] = {
 641         { "pca85073a", .driver_data = (kernel_ulong_t)&config_pcf85063a },
 642         { "pcf85063", .driver_data = (kernel_ulong_t)&config_pcf85063 },
 643         { "pcf85063tp", .driver_data = (kernel_ulong_t)&config_pcf85063tp },
 644         { "pcf85063a", .driver_data = (kernel_ulong_t)&config_pcf85063a },
 645         { "rv8263", .driver_data = (kernel_ulong_t)&config_rv8263 },
 646         {}
 647 };
 648 MODULE_DEVICE_TABLE(i2c, pcf85063_ids);
 649
 650 #ifdef CONFIG_OF
 651 static const struct of_device_id pcf85063_of_match[] = {
 652         { .compatible = "nxp,pca85073a", .data = &config_pcf85063a },
 653         { .compatible = "nxp,pcf85063", .data = &config_pcf85063 },
 654         { .compatible = "nxp,pcf85063tp", .data = &config_pcf85063tp },
 655         { .compatible = "nxp,pcf85063a", .data = &config_pcf85063a },
 656         { .compatible = "microcrystal,rv8263", .data = &config_rv8263 },
 657         {}
 658 };
 659 MODULE_DEVICE_TABLE(of, pcf85063_of_match);
 660 #endif
 661
 662 static struct i2c_driver pcf85063_driver = {
 663         .driver         = {
 664                 .name   = "rtc-pcf85063",
 665                 .of_match_table = of_match_ptr(pcf85063_of_match),
 666         },
 667         .probe          = pcf85063_probe,
 668         .id_table       = pcf85063_ids,
 669 };
 670
 671 module_i2c_driver(pcf85063_driver);
 672
 673 MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
 674 MODULE_DESCRIPTION("PCF85063 RTC driver");
 675 MODULE_LICENSE("GPL");