drivers/rtc/rtc-stmp3xxx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale STMP37XX/STMP378X Real Time Clock driver
   4  *
   5  * Copyright (c) 2007 Sigmatel, Inc.
   6  * Peter Hartley, <peter.hartley@sigmatel.com>
   7  *
   8  * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
   9  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  10  * Copyright 2011 Wolfram Sang, Pengutronix e.K.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/init.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/delay.h>
  19 #include <linux/rtc.h>
  20 #include <linux/slab.h>
  21 #include <linux/of.h>
  22 #include <linux/stmp_device.h>
  23 #include <linux/stmp3xxx_rtc_wdt.h>
  24
  25 #define STMP3XXX_RTC_CTRL                       0x0
  26 #define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN          0x00000001
  27 #define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN        0x00000002
  28 #define STMP3XXX_RTC_CTRL_ALARM_IRQ             0x00000004
  29 #define STMP3XXX_RTC_CTRL_WATCHDOGEN            0x00000010
  30
  31 #define STMP3XXX_RTC_STAT                       0x10
  32 #define STMP3XXX_RTC_STAT_STALE_SHIFT           16
  33 #define STMP3XXX_RTC_STAT_RTC_PRESENT           0x80000000
  34 #define STMP3XXX_RTC_STAT_XTAL32000_PRESENT     0x10000000
  35 #define STMP3XXX_RTC_STAT_XTAL32768_PRESENT     0x08000000
  36
  37 #define STMP3XXX_RTC_SECONDS                    0x30
  38
  39 #define STMP3XXX_RTC_ALARM                      0x40
  40
  41 #define STMP3XXX_RTC_WATCHDOG                   0x50
  42
  43 #define STMP3XXX_RTC_PERSISTENT0                0x60
  44 #define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE            (1 << 0)
  45 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN          (1 << 1)
  46 #define STMP3XXX_RTC_PERSISTENT0_ALARM_EN               (1 << 2)
  47 #define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP        (1 << 4)
  48 #define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP        (1 << 5)
  49 #define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ            (1 << 6)
  50 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE             (1 << 7)
  51
  52 #define STMP3XXX_RTC_PERSISTENT1                0x70
  53 /* missing bitmask in headers */
  54 #define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER  0x80000000
  55
  56 struct stmp3xxx_rtc_data {
  57         struct rtc_device *rtc;
  58         void __iomem *io;
  59         int irq_alarm;
  60 };
  61
  62 #if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
  63 /**
  64  * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
  65  * @dev: the parent device of the watchdog (= the RTC)
  66  * @timeout: the desired value for the timeout register of the watchdog.
  67  *           0 disables the watchdog
  68  *
  69  * The watchdog needs one register and two bits which are in the RTC domain.
  70  * To handle the resource conflict, the RTC driver will create another
  71  * platform_device for the watchdog driver as a child of the RTC device.
  72  * The watchdog driver is passed the below accessor function via platform_data
  73  * to configure the watchdog. Locking is not needed because accessing SET/CLR
  74  * registers is atomic.
  75  */
  76
  77 static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
  78 {
  79         struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  80
  81         if (timeout) {
  82                 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
  83                 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
  84                        rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
  85                 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
  86                        rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
  87         } else {
  88                 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
  89                        rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
  90                 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
  91                        rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
  92         }
  93 }
  94
  95 static struct stmp3xxx_wdt_pdata wdt_pdata = {
  96         .wdt_set_timeout = stmp3xxx_wdt_set_timeout,
  97 };
  98
  99 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
 100 {
 101         int rc = -1;
 102         struct platform_device *wdt_pdev =
 103                 platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
 104
 105         if (wdt_pdev) {
 106                 wdt_pdev->dev.parent = &rtc_pdev->dev;
 107                 wdt_pdev->dev.platform_data = &wdt_pdata;
 108                 rc = platform_device_add(wdt_pdev);
 109                 if (rc)
 110                         platform_device_put(wdt_pdev);
 111         }
 112
 113         if (rc)
 114                 dev_err(&rtc_pdev->dev,
 115                         "failed to register stmp3xxx_rtc_wdt\n");
 116 }
 117 #else
 118 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
 119 {
 120 }
 121 #endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
 122
 123 static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
 124 {
 125         int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
 126         /*
 127          * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
 128          * states:
 129          * | The order in which registers are updated is
 130          * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
 131          * | (This list is in bitfield order, from LSB to MSB, as they would
 132          * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
 133          * | register. For example, the Seconds register corresponds to
 134          * | STALE_REGS or NEW_REGS containing 0x80.)
 135          */
 136         do {
 137                 if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
 138                                 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
 139                         return 0;
 140                 udelay(1);
 141         } while (--timeout > 0);
 142         return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
 143                 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
 144 }
 145
 146 /* Time read/write */
 147 static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
 148 {
 149         int ret;
 150         struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 151
 152         ret = stmp3xxx_wait_time(rtc_data);
 153         if (ret)
 154                 return ret;
 155
 156         rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
 157         return 0;
 158 }
 159
 160 static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
 161 {
 162         struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 163
 164         writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
 165         return stmp3xxx_wait_time(rtc_data);
 166 }
 167
 168 /* interrupt(s) handler */
 169 static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
 170 {
 171         struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
 172         u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
 173
 174         if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
 175                 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
 176                         rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
 177                 rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
 178                 return IRQ_HANDLED;
 179         }
 180
 181         return IRQ_NONE;
 182 }
 183
 184 static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
 185 {
 186         struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 187
 188         if (enabled) {
 189                 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 190                                 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
 191                         rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
 192                                 STMP_OFFSET_REG_SET);
 193                 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
 194                         rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
 195         } else {
 196                 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 197                                 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
 198                         rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
 199                                 STMP_OFFSET_REG_CLR);
 200                 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
 201                         rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
 202         }
 203         return 0;
 204 }
 205
 206 static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
 207 {
 208         struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 209
 210         rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
 211         return 0;
 212 }
 213
 214 static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
 215 {
 216         struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 217
 218         writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
 219
 220         stmp3xxx_alarm_irq_enable(dev, alm->enabled);
 221
 222         return 0;
 223 }
 224
 225 static const struct rtc_class_ops stmp3xxx_rtc_ops = {
 226         .alarm_irq_enable =
 227                           stmp3xxx_alarm_irq_enable,
 228         .read_time      = stmp3xxx_rtc_gettime,
 229         .set_time       = stmp3xxx_rtc_settime,
 230         .read_alarm     = stmp3xxx_rtc_read_alarm,
 231         .set_alarm      = stmp3xxx_rtc_set_alarm,
 232 };
 233
 234 static void stmp3xxx_rtc_remove(struct platform_device *pdev)
 235 {
 236         struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
 237
 238         if (!rtc_data)
 239                 return;
 240
 241         writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
 242                 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
 243 }
 244
 245 static int stmp3xxx_rtc_probe(struct platform_device *pdev)
 246 {
 247         struct stmp3xxx_rtc_data *rtc_data;
 248         struct resource *r;
 249         u32 rtc_stat;
 250         u32 pers0_set, pers0_clr;
 251         u32 crystalfreq = 0;
 252         int err;
 253
 254         rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
 255         if (!rtc_data)
 256                 return -ENOMEM;
 257
 258         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 259         if (!r) {
 260                 dev_err(&pdev->dev, "failed to get resource\n");
 261                 return -ENXIO;
 262         }
 263
 264         rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 265         if (!rtc_data->io) {
 266                 dev_err(&pdev->dev, "ioremap failed\n");
 267                 return -EIO;
 268         }
 269
 270         rtc_data->irq_alarm = platform_get_irq(pdev, 0);
 271
 272         rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
 273         if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
 274                 dev_err(&pdev->dev, "no device onboard\n");
 275                 return -ENODEV;
 276         }
 277
 278         platform_set_drvdata(pdev, rtc_data);
 279
 280         /*
 281          * Resetting the rtc stops the watchdog timer that is potentially
 282          * running. So (assuming it is running on purpose) don't reset if the
 283          * watchdog is enabled.
 284          */
 285         if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
 286             STMP3XXX_RTC_CTRL_WATCHDOGEN) {
 287                 dev_info(&pdev->dev,
 288                          "Watchdog is running, skip resetting rtc\n");
 289         } else {
 290                 err = stmp_reset_block(rtc_data->io);
 291                 if (err) {
 292                         dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
 293                                 err);
 294                         return err;
 295                 }
 296         }
 297
 298         /*
 299          * Obviously the rtc needs a clock input to be able to run.
 300          * This clock can be provided by an external 32k crystal. If that one is
 301          * missing XTAL must not be disabled in suspend which consumes a
 302          * lot of power. Normally the presence and exact frequency (supported
 303          * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
 304          * proves these fuses are not blown correctly on all machines, so the
 305          * frequency can be overridden in the device tree.
 306          */
 307         if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
 308                 crystalfreq = 32000;
 309         else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
 310                 crystalfreq = 32768;
 311
 312         of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
 313                              &crystalfreq);
 314
 315         switch (crystalfreq) {
 316         case 32000:
 317                 /* keep 32kHz crystal running in low-power mode */
 318                 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
 319                         STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
 320                         STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
 321                 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
 322                 break;
 323         case 32768:
 324                 /* keep 32.768kHz crystal running in low-power mode */
 325                 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
 326                         STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
 327                 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
 328                         STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
 329                 break;
 330         default:
 331                 dev_warn(&pdev->dev,
 332                          "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
 333                 fallthrough;
 334         case 0:
 335                 /* keep XTAL on in low-power mode */
 336                 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
 337                 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
 338                         STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
 339         }
 340
 341         writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
 342                         STMP_OFFSET_REG_SET);
 343
 344         writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 345                         STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
 346                         STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
 347                 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
 348
 349         writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
 350                         STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
 351                 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
 352
 353         rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
 354         if (IS_ERR(rtc_data->rtc))
 355                 return PTR_ERR(rtc_data->rtc);
 356
 357         err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
 358                         stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
 359         if (err) {
 360                 dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
 361                         rtc_data->irq_alarm);
 362                 return err;
 363         }
 364
 365         rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
 366         rtc_data->rtc->range_max = U32_MAX;
 367
 368         err = devm_rtc_register_device(rtc_data->rtc);
 369         if (err)
 370                 return err;
 371
 372         stmp3xxx_wdt_register(pdev);
 373         return 0;
 374 }
 375
 376 #ifdef CONFIG_PM_SLEEP
 377 static int stmp3xxx_rtc_suspend(struct device *dev)
 378 {
 379         return 0;
 380 }
 381
 382 static int stmp3xxx_rtc_resume(struct device *dev)
 383 {
 384         struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 385
 386         stmp_reset_block(rtc_data->io);
 387         writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 388                         STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
 389                         STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
 390                 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
 391         return 0;
 392 }
 393 #endif
 394
 395 static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
 396                         stmp3xxx_rtc_resume);
 397
 398 static const struct of_device_id rtc_dt_ids[] = {
 399         { .compatible = "fsl,stmp3xxx-rtc", },
 400         { /* sentinel */ }
 401 };
 402 MODULE_DEVICE_TABLE(of, rtc_dt_ids);
 403
 404 static struct platform_driver stmp3xxx_rtcdrv = {
 405         .probe          = stmp3xxx_rtc_probe,
 406         .remove         = stmp3xxx_rtc_remove,
 407         .driver         = {
 408                 .name   = "stmp3xxx-rtc",
 409                 .pm     = &stmp3xxx_rtc_pm_ops,
 410                 .of_match_table = rtc_dt_ids,
 411         },
 412 };
 413
 414 module_platform_driver(stmp3xxx_rtcdrv);
 415
 416 MODULE_DESCRIPTION("STMP3xxx RTC Driver");
 417 MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
 418                 "Wolfram Sang <kernel@pengutronix.de>");
 419 MODULE_LICENSE("GPL");