drivers/scsi/mpi3mr/mpi/mpi30_transport.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  Copyright 2016-2023 Broadcom Inc. All rights reserved.
   4  */
   5 #ifndef MPI30_TRANSPORT_H
   6 #define MPI30_TRANSPORT_H     1
   7 struct mpi3_version_struct {
   8         u8         dev;
   9         u8         unit;
  10         u8         minor;
  11         u8         major;
  12 };
  13
  14 union mpi3_version_union {
  15         struct mpi3_version_struct     mpi3_version;
  16         __le32                     word;
  17 };
  18
  19 #define MPI3_VERSION_MAJOR                                              (3)
  20 #define MPI3_VERSION_MINOR                                              (0)
  21 #define MPI3_VERSION_UNIT                                               (34)
  22 #define MPI3_VERSION_DEV                                                (0)
  23 #define MPI3_DEVHANDLE_INVALID                                          (0xffff)
  24 struct mpi3_sysif_oper_queue_indexes {
  25         __le16         producer_index;
  26         __le16         reserved02;
  27         __le16         consumer_index;
  28         __le16         reserved06;
  29 };
  30
  31 struct mpi3_sysif_registers {
  32         __le64                             ioc_information;
  33         union mpi3_version_union              version;
  34         __le32                             reserved0c[2];
  35         __le32                             ioc_configuration;
  36         __le32                             reserved18;
  37         __le32                             ioc_status;
  38         __le32                             reserved20;
  39         __le32                             admin_queue_num_entries;
  40         __le64                             admin_request_queue_address;
  41         __le64                             admin_reply_queue_address;
  42         __le32                             reserved38[2];
  43         __le32                             coalesce_control;
  44         __le32                             reserved44[1007];
  45         __le16                             admin_request_queue_pi;
  46         __le16                             reserved1002;
  47         __le16                             admin_reply_queue_ci;
  48         __le16                             reserved1006;
  49         struct mpi3_sysif_oper_queue_indexes   oper_queue_indexes[383];
  50         __le32                             reserved1c00;
  51         __le32                             write_sequence;
  52         __le32                             host_diagnostic;
  53         __le32                             reserved1c0c;
  54         __le32                             fault;
  55         __le32                             fault_info[3];
  56         __le32                             reserved1c20[4];
  57         __le64                             hcb_address;
  58         __le32                             hcb_size;
  59         __le32                             reserved1c3c;
  60         __le32                             reply_free_host_index;
  61         __le32                             sense_buffer_free_host_index;
  62         __le32                             reserved1c48[2];
  63         __le64                             diag_rw_data;
  64         __le64                             diag_rw_address;
  65         __le16                             diag_rw_control;
  66         __le16                             diag_rw_status;
  67         __le32                             reserved1c64[35];
  68         __le32                             scratchpad[4];
  69         __le32                             reserved1d00[192];
  70         __le32                             device_assigned_registers[2048];
  71 };
  72
  73 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET                                  (0x00000000)
  74 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET                                 (0x00000004)
  75 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK                            (0xff000000)
  76 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT                           (24)
  77 #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED                            (0x00000001)
  78 #define MPI3_SYSIF_IOC_CONFIG_OFFSET                                    (0x00000014)
  79 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ                           (0x00f00000)
  80 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT                     (20)
  81 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ                           (0x000f0000)
  82 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT                     (16)
  83 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK                             (0x0000c000)
  84 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO                               (0x00000000)
  85 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL                           (0x00004000)
  86 #define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ                  (0x00002000)
  87 #define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE                                 (0x00000010)
  88 #define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC                                (0x00000001)
  89 #define MPI3_SYSIF_IOC_STATUS_OFFSET                                    (0x0000001c)
  90 #define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY                             (0x00000010)
  91 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK                             (0x0000000c)
  92 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT                            (0x00000002)
  93 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE                             (0x00000000)
  94 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS                      (0x00000004)
  95 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE                         (0x00000008)
  96 #define MPI3_SYSIF_IOC_STATUS_FAULT                                     (0x00000002)
  97 #define MPI3_SYSIF_IOC_STATUS_READY                                     (0x00000001)
  98 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET                           (0x00000024)
  99 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK                         (0x0fff)
 100 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET                     (0x00000026)
 101 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK                       (0x0fff0000)
 102 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT                      (16)
 103 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET                          (0x00000028)
 104 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET                         (0x0000002c)
 105 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET                        (0x00000030)
 106 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET                       (0x00000034)
 107 #define MPI3_SYSIF_COALESCE_CONTROL_OFFSET                              (0x00000040)
 108 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK                         (0xc0000000)
 109 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE                    (0x00000000)
 110 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE                      (0x40000000)
 111 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE                       (0xc0000000)
 112 #define MPI3_SYSIF_COALESCE_CONTROL_VALID                               (0x20000000)
 113 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK                       (0x01ff0000)
 114 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT                      (16)
 115 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK                        (0x0000ff00)
 116 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT                       (8)
 117 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK                          (0x000000ff)
 118 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT                         (0)
 119 #define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET                                (0x00001000)
 120 #define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET                              (0x00001004)
 121 #define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET                                 (0x00001008)
 122 #define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N)                            (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N) - 1) * 8))
 123 #define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET                               (0x0000100c)
 124 #define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N)                          (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N) - 1) * 8))
 125 #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET                                (0x00001c04)
 126 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK                        (0x0000000f)
 127 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH                       (0x0)
 128 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST                         (0xf)
 129 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND                         (0x4)
 130 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD                         (0xb)
 131 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH                         (0x2)
 132 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH                         (0x7)
 133 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH                         (0xd)
 134 #define MPI3_SYSIF_HOST_DIAG_OFFSET                                     (0x00001c08)
 135 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK                          (0x00000700)
 136 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET                      (0x00000000)
 137 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET                    (0x00000100)
 138 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET       (0x00000200)
 139 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET                (0x00000300)
 140 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT                    (0x00000700)
 141 #define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS                           (0x00000080)
 142 #define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT                                (0x00000040)
 143 #define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE                     (0x00000020)
 144 #define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE                           (0x00000010)
 145 #define MPI3_SYSIF_HOST_DIAG_HCBENABLE                                  (0x00000008)
 146 #define MPI3_SYSIF_HOST_DIAG_HCBMODE                                    (0x00000004)
 147 #define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE                             (0x00000002)
 148 #define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE                          (0x00000001)
 149 #define MPI3_SYSIF_FAULT_OFFSET                                         (0x00001c10)
 150 #define MPI3_SYSIF_FAULT_FUNC_AREA_MASK                                 (0xff000000)
 151 #define MPI3_SYSIF_FAULT_FUNC_AREA_SHIFT                                (24)
 152 #define MPI3_SYSIF_FAULT_FUNC_AREA_MPI_DEFINED                          (0x00000000)
 153 #define MPI3_SYSIF_FAULT_CODE_MASK                                      (0x0000ffff)
 154 #define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET                          (0x0000f000)
 155 #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET                       (0x0000f001)
 156 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS                    (0x0000f002)
 157 #define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED                     (0x0000f003)
 158 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED                         (0x0000f004)
 159 #define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED                      (0x0000f005)
 160 #define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED                   (0x0000f006)
 161 #define MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER               (0x0000f007)
 162 #define MPI3_SYSIF_FAULT_INFO0_OFFSET                                   (0x00001c14)
 163 #define MPI3_SYSIF_FAULT_INFO1_OFFSET                                   (0x00001c18)
 164 #define MPI3_SYSIF_FAULT_INFO2_OFFSET                                   (0x00001c1c)
 165 #define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET                               (0x00001c30)
 166 #define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET                              (0x00001c34)
 167 #define MPI3_SYSIF_HCB_SIZE_OFFSET                                      (0x00001c38)
 168 #define MPI3_SYSIF_HCB_SIZE_SIZE_MASK                                   (0xfffff000)
 169 #define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT                                  (12)
 170 #define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE                                 (0x00000001)
 171 #define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET                         (0x00001c40)
 172 #define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET                     (0x00001c44)
 173 #define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET                              (0x00001c50)
 174 #define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET                             (0x00001c54)
 175 #define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET                           (0x00001c58)
 176 #define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET                          (0x00001c5c)
 177 #define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET                               (0x00001c60)
 178 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK                             (0x00000030)
 179 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE                            (0x00000000)
 180 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES                           (0x00000010)
 181 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES                           (0x00000020)
 182 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES                           (0x00000030)
 183 #define MPI3_SYSIF_DIAG_RW_CONTROL_RESET                                (0x00000004)
 184 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK                             (0x00000002)
 185 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ                             (0x00000000)
 186 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE                            (0x00000002)
 187 #define MPI3_SYSIF_DIAG_RW_CONTROL_START                                (0x00000001)
 188 #define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET                                (0x00001c62)
 189 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK                           (0x0000000e)
 190 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS                        (0x00000000)
 191 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR                       (0x00000002)
 192 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR                        (0x00000004)
 193 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR                        (0x00000006)
 194 #define MPI3_SYSIF_DIAG_RW_STATUS_BUSY                                  (0x00000001)
 195 #define MPI3_SYSIF_SCRATCHPAD0_OFFSET                                   (0x00001cf0)
 196 #define MPI3_SYSIF_SCRATCHPAD1_OFFSET                                   (0x00001cf4)
 197 #define MPI3_SYSIF_SCRATCHPAD2_OFFSET                                   (0x00001cf8)
 198 #define MPI3_SYSIF_SCRATCHPAD3_OFFSET                                   (0x00001cfc)
 199 #define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET                          (0x00002000)
 200 #define MPI3_SYSIF_DIAG_SAVE_TIMEOUT                                    (60)
 201 struct mpi3_default_reply_descriptor {
 202         __le32             descriptor_type_dependent1[2];
 203         __le16             request_queue_ci;
 204         __le16             request_queue_id;
 205         __le16             descriptor_type_dependent2;
 206         __le16             reply_flags;
 207 };
 208
 209 #define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK                       (0x0001)
 210 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK                        (0xf000)
 211 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY               (0x0000)
 212 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS                     (0x1000)
 213 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER       (0x2000)
 214 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS                      (0x3000)
 215 #define MPI3_REPLY_DESCRIPT_REQUEST_QUEUE_ID_INVALID               (0xffff)
 216 struct mpi3_address_reply_descriptor {
 217         __le64             reply_frame_address;
 218         __le16             request_queue_ci;
 219         __le16             request_queue_id;
 220         __le16             reserved0c;
 221         __le16             reply_flags;
 222 };
 223
 224 struct mpi3_success_reply_descriptor {
 225         __le32             reserved00[2];
 226         __le16             request_queue_ci;
 227         __le16             request_queue_id;
 228         __le16             host_tag;
 229         __le16             reply_flags;
 230 };
 231
 232 struct mpi3_target_command_buffer_reply_descriptor {
 233         __le32             reserved00;
 234         __le16             initiator_dev_handle;
 235         u8                 phy_num;
 236         u8                 reserved07;
 237         __le16             request_queue_ci;
 238         __le16             request_queue_id;
 239         __le16             io_index;
 240         __le16             reply_flags;
 241 };
 242
 243 struct mpi3_status_reply_descriptor {
 244         __le16             ioc_status;
 245         __le16             reserved02;
 246         __le32             ioc_log_info;
 247         __le16             request_queue_ci;
 248         __le16             request_queue_id;
 249         __le16             host_tag;
 250         __le16             reply_flags;
 251 };
 252
 253 #define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL               (0x8000)
 254 #define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK                (0x7fff)
 255 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_MASK                 (0xf0000000)
 256 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_NO_INFO              (0x00000000)
 257 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_SAS                  (0x30000000)
 258 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_DATA_MASK                 (0x0fffffff)
 259 union mpi3_reply_descriptors_union {
 260         struct mpi3_default_reply_descriptor               default_reply;
 261         struct mpi3_address_reply_descriptor               address_reply;
 262         struct mpi3_success_reply_descriptor               success;
 263         struct mpi3_target_command_buffer_reply_descriptor target_command_buffer;
 264         struct mpi3_status_reply_descriptor                status;
 265         __le32                                         words[4];
 266 };
 267
 268 struct mpi3_sge_common {
 269         __le64             address;
 270         __le32             length;
 271         u8                 reserved0c[3];
 272         u8                 flags;
 273 };
 274
 275 struct mpi3_sge_bit_bucket {
 276         __le64             reserved00;
 277         __le32             length;
 278         u8                 reserved0c[3];
 279         u8                 flags;
 280 };
 281
 282 struct mpi3_sge_extended_eedp {
 283         u8                 user_data_size;
 284         u8                 reserved01;
 285         __le16             eedp_flags;
 286         __le32             secondary_reference_tag;
 287         __le16             secondary_application_tag;
 288         __le16             application_tag_translation_mask;
 289         __le16             reserved0c;
 290         u8                 extended_operation;
 291         u8                 flags;
 292 };
 293
 294 union mpi3_sge_union {
 295         struct mpi3_sge_common                 simple;
 296         struct mpi3_sge_common                  chain;
 297         struct mpi3_sge_common             last_chain;
 298         struct mpi3_sge_bit_bucket             bit_bucket;
 299         struct mpi3_sge_extended_eedp          eedp;
 300         __le32                             words[4];
 301 };
 302
 303 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK        (0xf0)
 304 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE      (0x00)
 305 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET  (0x10)
 306 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN       (0x20)
 307 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN  (0x30)
 308 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED    (0xf0)
 309 #define MPI3_SGE_FLAGS_END_OF_LIST              (0x08)
 310 #define MPI3_SGE_FLAGS_END_OF_BUFFER            (0x04)
 311 #define MPI3_SGE_FLAGS_DLAS_MASK                (0x03)
 312 #define MPI3_SGE_FLAGS_DLAS_SYSTEM              (0x00)
 313 #define MPI3_SGE_FLAGS_DLAS_IOC_UDP             (0x01)
 314 #define MPI3_SGE_FLAGS_DLAS_IOC_CTL             (0x02)
 315 #define MPI3_SGE_EXT_OPER_EEDP                  (0x00)
 316 #define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG             (0x8000)
 317 #define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG             (0x4000)
 318 #define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG             (0x2000)
 319 #define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG             (0x1000)
 320 #define MPI3_EEDPFLAGS_ESC_PASSTHROUGH              (0x0800)
 321 #define MPI3_EEDPFLAGS_CHK_REF_TAG                  (0x0400)
 322 #define MPI3_EEDPFLAGS_CHK_APP_TAG                  (0x0200)
 323 #define MPI3_EEDPFLAGS_CHK_GUARD                    (0x0100)
 324 #define MPI3_EEDPFLAGS_ESC_MODE_MASK                (0x00c0)
 325 #define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE      (0x0040)
 326 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE      (0x0080)
 327 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE   (0x00c0)
 328 #define MPI3_EEDPFLAGS_HOST_GUARD_MASK              (0x0030)
 329 #define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC           (0x0000)
 330 #define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM         (0x0010)
 331 #define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC      (0x0020)
 332 #define MPI3_EEDPFLAGS_PT_REF_TAG                   (0x0008)
 333 #define MPI3_EEDPFLAGS_EEDP_OP_MASK                 (0x0007)
 334 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK                (0x0001)
 335 #define MPI3_EEDPFLAGS_EEDP_OP_STRIP                (0x0002)
 336 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE         (0x0003)
 337 #define MPI3_EEDPFLAGS_EEDP_OP_INSERT               (0x0004)
 338 #define MPI3_EEDPFLAGS_EEDP_OP_REPLACE              (0x0006)
 339 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN          (0x0007)
 340 #define MPI3_EEDP_UDS_512                           (0x01)
 341 #define MPI3_EEDP_UDS_520                           (0x02)
 342 #define MPI3_EEDP_UDS_4080                          (0x03)
 343 #define MPI3_EEDP_UDS_4088                          (0x04)
 344 #define MPI3_EEDP_UDS_4096                          (0x05)
 345 #define MPI3_EEDP_UDS_4104                          (0x06)
 346 #define MPI3_EEDP_UDS_4160                          (0x07)
 347 struct mpi3_request_header {
 348         __le16             host_tag;
 349         u8                 ioc_use_only02;
 350         u8                 function;
 351         __le16             ioc_use_only04;
 352         u8                 ioc_use_only06;
 353         u8                 msg_flags;
 354         __le16             change_count;
 355         __le16             function_dependent;
 356 };
 357
 358 struct mpi3_default_reply {
 359         __le16             host_tag;
 360         u8                 ioc_use_only02;
 361         u8                 function;
 362         __le16             ioc_use_only04;
 363         u8                 ioc_use_only06;
 364         u8                 msg_flags;
 365         __le16             ioc_use_only08;
 366         __le16             ioc_status;
 367         __le32             ioc_log_info;
 368 };
 369
 370 #define MPI3_HOST_TAG_INVALID                       (0xffff)
 371 #define MPI3_FUNCTION_IOC_FACTS                     (0x01)
 372 #define MPI3_FUNCTION_IOC_INIT                      (0x02)
 373 #define MPI3_FUNCTION_PORT_ENABLE                   (0x03)
 374 #define MPI3_FUNCTION_EVENT_NOTIFICATION            (0x04)
 375 #define MPI3_FUNCTION_EVENT_ACK                     (0x05)
 376 #define MPI3_FUNCTION_CI_DOWNLOAD                   (0x06)
 377 #define MPI3_FUNCTION_CI_UPLOAD                     (0x07)
 378 #define MPI3_FUNCTION_IO_UNIT_CONTROL               (0x08)
 379 #define MPI3_FUNCTION_PERSISTENT_EVENT_LOG          (0x09)
 380 #define MPI3_FUNCTION_MGMT_PASSTHROUGH              (0x0a)
 381 #define MPI3_FUNCTION_CONFIG                        (0x10)
 382 #define MPI3_FUNCTION_SCSI_IO                       (0x20)
 383 #define MPI3_FUNCTION_SCSI_TASK_MGMT                (0x21)
 384 #define MPI3_FUNCTION_SMP_PASSTHROUGH               (0x22)
 385 #define MPI3_FUNCTION_NVME_ENCAPSULATED             (0x24)
 386 #define MPI3_FUNCTION_TARGET_ASSIST                 (0x30)
 387 #define MPI3_FUNCTION_TARGET_STATUS_SEND            (0x31)
 388 #define MPI3_FUNCTION_TARGET_MODE_ABORT             (0x32)
 389 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE      (0x33)
 390 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST      (0x34)
 391 #define MPI3_FUNCTION_CREATE_REQUEST_QUEUE          (0x70)
 392 #define MPI3_FUNCTION_DELETE_REQUEST_QUEUE          (0x71)
 393 #define MPI3_FUNCTION_CREATE_REPLY_QUEUE            (0x72)
 394 #define MPI3_FUNCTION_DELETE_REPLY_QUEUE            (0x73)
 395 #define MPI3_FUNCTION_TOOLBOX                       (0x80)
 396 #define MPI3_FUNCTION_DIAG_BUFFER_POST              (0x81)
 397 #define MPI3_FUNCTION_DIAG_BUFFER_MANAGE            (0x82)
 398 #define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD            (0x83)
 399 #define MPI3_FUNCTION_MIN_IOC_USE_ONLY              (0xc0)
 400 #define MPI3_FUNCTION_MAX_IOC_USE_ONLY              (0xef)
 401 #define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC          (0xf0)
 402 #define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC          (0xff)
 403 #define MPI3_IOCSTATUS_LOG_INFO_AVAIL_MASK          (0x8000)
 404 #define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE           (0x8000)
 405 #define MPI3_IOCSTATUS_STATUS_MASK                  (0x7fff)
 406 #define MPI3_IOCSTATUS_SUCCESS                      (0x0000)
 407 #define MPI3_IOCSTATUS_INVALID_FUNCTION             (0x0001)
 408 #define MPI3_IOCSTATUS_BUSY                         (0x0002)
 409 #define MPI3_IOCSTATUS_INVALID_SGL                  (0x0003)
 410 #define MPI3_IOCSTATUS_INTERNAL_ERROR               (0x0004)
 411 #define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES       (0x0006)
 412 #define MPI3_IOCSTATUS_INVALID_FIELD                (0x0007)
 413 #define MPI3_IOCSTATUS_INVALID_STATE                (0x0008)
 414 #define MPI3_IOCSTATUS_SHUTDOWN_ACTIVE              (0x0009)
 415 #define MPI3_IOCSTATUS_INSUFFICIENT_POWER           (0x000a)
 416 #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT         (0x000b)
 417 #define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK            (0x000c)
 418 #define MPI3_IOCSTATUS_SUPERVISOR_ONLY              (0x000d)
 419 #define MPI3_IOCSTATUS_FAILURE                      (0x001f)
 420 #define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION        (0x0020)
 421 #define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE          (0x0021)
 422 #define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE          (0x0022)
 423 #define MPI3_IOCSTATUS_CONFIG_INVALID_DATA          (0x0023)
 424 #define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS           (0x0024)
 425 #define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT           (0x0025)
 426 #define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR         (0x0040)
 427 #define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED        (0x0041)
 428 #define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE       (0x0042)
 429 #define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE        (0x0043)
 430 #define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN            (0x0044)
 431 #define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN           (0x0045)
 432 #define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR           (0x0046)
 433 #define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR          (0x0047)
 434 #define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED         (0x0048)
 435 #define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH       (0x0049)
 436 #define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED        (0x004a)
 437 #define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED          (0x004b)
 438 #define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED          (0x004c)
 439 #define MPI3_IOCSTATUS_EEDP_GUARD_ERROR             (0x004d)
 440 #define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR           (0x004e)
 441 #define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR           (0x004f)
 442 #define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX      (0x0062)
 443 #define MPI3_IOCSTATUS_TARGET_ABORTED               (0x0063)
 444 #define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE     (0x0064)
 445 #define MPI3_IOCSTATUS_TARGET_NO_CONNECTION         (0x0065)
 446 #define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH   (0x006a)
 447 #define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR     (0x006d)
 448 #define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA   (0x006e)
 449 #define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT          (0x006f)
 450 #define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT       (0x0070)
 451 #define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED          (0x0071)
 452 #define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED       (0x0090)
 453 #define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN         (0x0091)
 454 #define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED          (0x00a0)
 455 #define MPI3_IOCSTATUS_CI_UNSUPPORTED               (0x00b0)
 456 #define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE           (0x00b1)
 457 #define MPI3_IOCSTATUS_CI_VALIDATION_FAILED         (0x00b2)
 458 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING        (0x00b3)
 459 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE   (0x00b4)
 460 #define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED        (0x00c0)
 461 #define MPI3_IOCSTATUS_SECURITY_VIOLATION           (0x00c1)
 462 #define MPI3_IOCSTATUS_INVALID_QUEUE_ID             (0x0f00)
 463 #define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE           (0x0f01)
 464 #define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR          (0x0f02)
 465 #define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID       (0x0f03)
 466 #define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION       (0x0f04)
 467 #define MPI3_IOCLOGINFO_TYPE_MASK               (0xf0000000)
 468 #define MPI3_IOCLOGINFO_TYPE_SHIFT              (28)
 469 #define MPI3_IOCLOGINFO_TYPE_NONE               (0x0)
 470 #define MPI3_IOCLOGINFO_TYPE_SAS                (0x3)
 471 #define MPI3_IOCLOGINFO_LOG_DATA_MASK           (0x0fffffff)
 472 #endif