1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
4 #ifndef __SDW_INTEL_LOCAL_H
5 #define __SDW_INTEL_LOCAL_H
10 * struct sdw_intel_link_res - Soundwire Intel link resource structure,
11 * typically populated by the controller driver.
12 * @hw_ops: platform-specific ops
13 * @mmio_base: mmio base of SoundWire registers
14 * @registers: Link IO registers base
15 * @ip_offset: offset for MCP_IP registers
16 * @shim: Audio shim pointer
17 * @shim_vs: Audio vendor-specific shim pointer
18 * @alh: ALH (Audio Link Hub) pointer
19 * @irq: Interrupt line
20 * @ops: Shim callback ops
21 * @dev: device implementing hw_params and free callbacks
22 * @shim_lock: mutex to handle access to shared SHIM registers
23 * @shim_mask: global pointer to check SHIM register initialization
24 * @clock_stop_quirks: mask defining requested behavior on pm_suspend
25 * @link_mask: global mask needed for power-up/down sequences
26 * @cdns: Cadence master descriptor
27 * @list: used to walk-through all masters exposed by the same controller
28 * @hbus: hdac_bus pointer, needed for power management
30 struct sdw_intel_link_res
{
31 const struct sdw_intel_hw_ops
*hw_ops
;
33 void __iomem
*mmio_base
; /* not strictly needed, useful for debug */
34 void __iomem
*registers
;
37 void __iomem
*shim_vs
;
40 const struct sdw_intel_ops
*ops
;
42 struct mutex
*shim_lock
; /* protect shared registers */
44 u32 clock_stop_quirks
;
46 struct sdw_cdns
*cdns
;
47 struct list_head list
;
48 struct hdac_bus
*hbus
;
54 struct sdw_intel_link_res
*link_res
;
56 #ifdef CONFIG_DEBUG_FS
57 struct dentry
*debugfs
;
61 struct sdw_intel_prop
{
80 * Read, write helpers for HW registers
82 static inline int intel_readl(void __iomem
*base
, int offset
)
84 return readl(base
+ offset
);
87 static inline void intel_writel(void __iomem
*base
, int offset
, int value
)
89 writel(value
, base
+ offset
);
92 static inline u16
intel_readw(void __iomem
*base
, int offset
)
94 return readw(base
+ offset
);
97 static inline void intel_writew(void __iomem
*base
, int offset
, u16 value
)
99 writew(value
, base
+ offset
);
102 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
104 #define INTEL_MASTER_RESET_ITERATIONS 10
106 #define SDW_INTEL_DELAYED_ENUMERATION_MS 100
108 #define SDW_INTEL_CHECK_OPS(sdw, cb) ((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \
109 (sdw)->link_res->hw_ops->cb)
110 #define SDW_INTEL_OPS(sdw, cb) ((sdw)->link_res->hw_ops->cb)
112 #ifdef CONFIG_DEBUG_FS
113 void intel_ace2x_debugfs_init(struct sdw_intel
*sdw
);
114 void intel_ace2x_debugfs_exit(struct sdw_intel
*sdw
);
116 static inline void intel_ace2x_debugfs_init(struct sdw_intel
*sdw
) {}
117 static inline void intel_ace2x_debugfs_exit(struct sdw_intel
*sdw
) {}
120 static inline void sdw_intel_debugfs_init(struct sdw_intel
*sdw
)
122 if (SDW_INTEL_CHECK_OPS(sdw
, debugfs_init
))
123 SDW_INTEL_OPS(sdw
, debugfs_init
)(sdw
);
126 static inline void sdw_intel_debugfs_exit(struct sdw_intel
*sdw
)
128 if (SDW_INTEL_CHECK_OPS(sdw
, debugfs_exit
))
129 SDW_INTEL_OPS(sdw
, debugfs_exit
)(sdw
);
132 static inline int sdw_intel_register_dai(struct sdw_intel
*sdw
)
134 if (SDW_INTEL_CHECK_OPS(sdw
, register_dai
))
135 return SDW_INTEL_OPS(sdw
, register_dai
)(sdw
);
139 static inline void sdw_intel_check_clock_stop(struct sdw_intel
*sdw
)
141 if (SDW_INTEL_CHECK_OPS(sdw
, check_clock_stop
))
142 SDW_INTEL_OPS(sdw
, check_clock_stop
)(sdw
);
145 static inline int sdw_intel_start_bus(struct sdw_intel
*sdw
)
147 if (SDW_INTEL_CHECK_OPS(sdw
, start_bus
))
148 return SDW_INTEL_OPS(sdw
, start_bus
)(sdw
);
152 static inline int sdw_intel_start_bus_after_reset(struct sdw_intel
*sdw
)
154 if (SDW_INTEL_CHECK_OPS(sdw
, start_bus_after_reset
))
155 return SDW_INTEL_OPS(sdw
, start_bus_after_reset
)(sdw
);
159 static inline int sdw_intel_start_bus_after_clock_stop(struct sdw_intel
*sdw
)
161 if (SDW_INTEL_CHECK_OPS(sdw
, start_bus_after_clock_stop
))
162 return SDW_INTEL_OPS(sdw
, start_bus_after_clock_stop
)(sdw
);
166 static inline int sdw_intel_stop_bus(struct sdw_intel
*sdw
, bool clock_stop
)
168 if (SDW_INTEL_CHECK_OPS(sdw
, stop_bus
))
169 return SDW_INTEL_OPS(sdw
, stop_bus
)(sdw
, clock_stop
);
173 static inline int sdw_intel_link_power_up(struct sdw_intel
*sdw
)
175 if (SDW_INTEL_CHECK_OPS(sdw
, link_power_up
))
176 return SDW_INTEL_OPS(sdw
, link_power_up
)(sdw
);
180 static inline int sdw_intel_link_power_down(struct sdw_intel
*sdw
)
182 if (SDW_INTEL_CHECK_OPS(sdw
, link_power_down
))
183 return SDW_INTEL_OPS(sdw
, link_power_down
)(sdw
);
187 static inline int sdw_intel_shim_check_wake(struct sdw_intel
*sdw
)
189 if (SDW_INTEL_CHECK_OPS(sdw
, shim_check_wake
))
190 return SDW_INTEL_OPS(sdw
, shim_check_wake
)(sdw
);
194 static inline void sdw_intel_shim_wake(struct sdw_intel
*sdw
, bool wake_enable
)
196 if (SDW_INTEL_CHECK_OPS(sdw
, shim_wake
))
197 SDW_INTEL_OPS(sdw
, shim_wake
)(sdw
, wake_enable
);
200 static inline void sdw_intel_sync_arm(struct sdw_intel
*sdw
)
202 if (SDW_INTEL_CHECK_OPS(sdw
, sync_arm
))
203 SDW_INTEL_OPS(sdw
, sync_arm
)(sdw
);
206 static inline int sdw_intel_sync_go_unlocked(struct sdw_intel
*sdw
)
208 if (SDW_INTEL_CHECK_OPS(sdw
, sync_go_unlocked
))
209 return SDW_INTEL_OPS(sdw
, sync_go_unlocked
)(sdw
);
213 static inline int sdw_intel_sync_go(struct sdw_intel
*sdw
)
215 if (SDW_INTEL_CHECK_OPS(sdw
, sync_go
))
216 return SDW_INTEL_OPS(sdw
, sync_go
)(sdw
);
220 static inline bool sdw_intel_sync_check_cmdsync_unlocked(struct sdw_intel
*sdw
)
222 if (SDW_INTEL_CHECK_OPS(sdw
, sync_check_cmdsync_unlocked
))
223 return SDW_INTEL_OPS(sdw
, sync_check_cmdsync_unlocked
)(sdw
);
227 static inline int sdw_intel_get_link_count(struct sdw_intel
*sdw
)
229 if (SDW_INTEL_CHECK_OPS(sdw
, get_link_count
))
230 return SDW_INTEL_OPS(sdw
, get_link_count
)(sdw
);
231 return 4; /* default on older generations */
234 /* common bus management */
235 int intel_start_bus(struct sdw_intel
*sdw
);
236 int intel_start_bus_after_reset(struct sdw_intel
*sdw
);
237 void intel_check_clock_stop(struct sdw_intel
*sdw
);
238 int intel_start_bus_after_clock_stop(struct sdw_intel
*sdw
);
239 int intel_stop_bus(struct sdw_intel
*sdw
, bool clock_stop
);
241 /* common bank switch routines */
242 int intel_pre_bank_switch(struct sdw_intel
*sdw
);
243 int intel_post_bank_switch(struct sdw_intel
*sdw
);
245 #endif /* __SDW_INTEL_LOCAL_H */