drivers/spi/spi-dln2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for the Diolan DLN-2 USB-SPI adapter
   4  *
   5  * Copyright (c) 2014 Intel Corporation
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/property.h>
  12 #include <linux/mfd/dln2.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/unaligned.h>
  16
  17 #define DLN2_SPI_MODULE_ID              0x02
  18 #define DLN2_SPI_CMD(cmd)               DLN2_CMD(cmd, DLN2_SPI_MODULE_ID)
  19
  20 /* SPI commands */
  21 #define DLN2_SPI_GET_PORT_COUNT                 DLN2_SPI_CMD(0x00)
  22 #define DLN2_SPI_ENABLE                         DLN2_SPI_CMD(0x11)
  23 #define DLN2_SPI_DISABLE                        DLN2_SPI_CMD(0x12)
  24 #define DLN2_SPI_IS_ENABLED                     DLN2_SPI_CMD(0x13)
  25 #define DLN2_SPI_SET_MODE                       DLN2_SPI_CMD(0x14)
  26 #define DLN2_SPI_GET_MODE                       DLN2_SPI_CMD(0x15)
  27 #define DLN2_SPI_SET_FRAME_SIZE                 DLN2_SPI_CMD(0x16)
  28 #define DLN2_SPI_GET_FRAME_SIZE                 DLN2_SPI_CMD(0x17)
  29 #define DLN2_SPI_SET_FREQUENCY                  DLN2_SPI_CMD(0x18)
  30 #define DLN2_SPI_GET_FREQUENCY                  DLN2_SPI_CMD(0x19)
  31 #define DLN2_SPI_READ_WRITE                     DLN2_SPI_CMD(0x1A)
  32 #define DLN2_SPI_READ                           DLN2_SPI_CMD(0x1B)
  33 #define DLN2_SPI_WRITE                          DLN2_SPI_CMD(0x1C)
  34 #define DLN2_SPI_SET_DELAY_BETWEEN_SS           DLN2_SPI_CMD(0x20)
  35 #define DLN2_SPI_GET_DELAY_BETWEEN_SS           DLN2_SPI_CMD(0x21)
  36 #define DLN2_SPI_SET_DELAY_AFTER_SS             DLN2_SPI_CMD(0x22)
  37 #define DLN2_SPI_GET_DELAY_AFTER_SS             DLN2_SPI_CMD(0x23)
  38 #define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES       DLN2_SPI_CMD(0x24)
  39 #define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES       DLN2_SPI_CMD(0x25)
  40 #define DLN2_SPI_SET_SS                         DLN2_SPI_CMD(0x26)
  41 #define DLN2_SPI_GET_SS                         DLN2_SPI_CMD(0x27)
  42 #define DLN2_SPI_RELEASE_SS                     DLN2_SPI_CMD(0x28)
  43 #define DLN2_SPI_SS_VARIABLE_ENABLE             DLN2_SPI_CMD(0x2B)
  44 #define DLN2_SPI_SS_VARIABLE_DISABLE            DLN2_SPI_CMD(0x2C)
  45 #define DLN2_SPI_SS_VARIABLE_IS_ENABLED         DLN2_SPI_CMD(0x2D)
  46 #define DLN2_SPI_SS_AAT_ENABLE                  DLN2_SPI_CMD(0x2E)
  47 #define DLN2_SPI_SS_AAT_DISABLE                 DLN2_SPI_CMD(0x2F)
  48 #define DLN2_SPI_SS_AAT_IS_ENABLED              DLN2_SPI_CMD(0x30)
  49 #define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE       DLN2_SPI_CMD(0x31)
  50 #define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE      DLN2_SPI_CMD(0x32)
  51 #define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED   DLN2_SPI_CMD(0x33)
  52 #define DLN2_SPI_SET_CPHA                       DLN2_SPI_CMD(0x34)
  53 #define DLN2_SPI_GET_CPHA                       DLN2_SPI_CMD(0x35)
  54 #define DLN2_SPI_SET_CPOL                       DLN2_SPI_CMD(0x36)
  55 #define DLN2_SPI_GET_CPOL                       DLN2_SPI_CMD(0x37)
  56 #define DLN2_SPI_SS_MULTI_ENABLE                DLN2_SPI_CMD(0x38)
  57 #define DLN2_SPI_SS_MULTI_DISABLE               DLN2_SPI_CMD(0x39)
  58 #define DLN2_SPI_SS_MULTI_IS_ENABLED            DLN2_SPI_CMD(0x3A)
  59 #define DLN2_SPI_GET_SUPPORTED_MODES            DLN2_SPI_CMD(0x40)
  60 #define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES      DLN2_SPI_CMD(0x41)
  61 #define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES      DLN2_SPI_CMD(0x42)
  62 #define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES      DLN2_SPI_CMD(0x43)
  63 #define DLN2_SPI_GET_SS_COUNT                   DLN2_SPI_CMD(0x44)
  64 #define DLN2_SPI_GET_MIN_FREQUENCY              DLN2_SPI_CMD(0x45)
  65 #define DLN2_SPI_GET_MAX_FREQUENCY              DLN2_SPI_CMD(0x46)
  66 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS       DLN2_SPI_CMD(0x47)
  67 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS       DLN2_SPI_CMD(0x48)
  68 #define DLN2_SPI_GET_MIN_DELAY_AFTER_SS         DLN2_SPI_CMD(0x49)
  69 #define DLN2_SPI_GET_MAX_DELAY_AFTER_SS         DLN2_SPI_CMD(0x4A)
  70 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES   DLN2_SPI_CMD(0x4B)
  71 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES   DLN2_SPI_CMD(0x4C)
  72
  73 #define DLN2_SPI_MAX_XFER_SIZE                  256
  74 #define DLN2_SPI_BUF_SIZE                       (DLN2_SPI_MAX_XFER_SIZE + 16)
  75 #define DLN2_SPI_ATTR_LEAVE_SS_LOW              BIT(0)
  76 #define DLN2_TRANSFERS_WAIT_COMPLETE            1
  77 #define DLN2_TRANSFERS_CANCEL                   0
  78 #define DLN2_RPM_AUTOSUSPEND_TIMEOUT            2000
  79
  80 struct dln2_spi {
  81         struct platform_device *pdev;
  82         struct spi_controller *host;
  83         u8 port;
  84
  85         /*
  86          * This buffer will be used mainly for read/write operations. Since
  87          * they're quite large, we cannot use the stack. Protection is not
  88          * needed because all SPI communication is serialized by the SPI core.
  89          */
  90         void *buf;
  91
  92         u8 bpw;
  93         u32 speed;
  94         u16 mode;
  95         u8 cs;
  96 };
  97
  98 /*
  99  * Enable/Disable SPI module. The disable command will wait for transfers to
 100  * complete first.
 101  */
 102 static int dln2_spi_enable(struct dln2_spi *dln2, bool enable)
 103 {
 104         u16 cmd;
 105         struct {
 106                 u8 port;
 107                 u8 wait_for_completion;
 108         } tx;
 109         unsigned len = sizeof(tx);
 110
 111         tx.port = dln2->port;
 112
 113         if (enable) {
 114                 cmd = DLN2_SPI_ENABLE;
 115                 len -= sizeof(tx.wait_for_completion);
 116         } else {
 117                 tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE;
 118                 cmd = DLN2_SPI_DISABLE;
 119         }
 120
 121         return dln2_transfer_tx(dln2->pdev, cmd, &tx, len);
 122 }
 123
 124 /*
 125  * Select/unselect multiple CS lines. The selected lines will be automatically
 126  * toggled LOW/HIGH by the board firmware during transfers, provided they're
 127  * enabled first.
 128  *
 129  * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation
 130  *                       will toggle the lines LOW/HIGH automatically.
 131  */
 132 static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask)
 133 {
 134         struct {
 135                 u8 port;
 136                 u8 cs;
 137         } tx;
 138
 139         tx.port = dln2->port;
 140
 141         /*
 142          * According to Diolan docs, "a slave device can be selected by changing
 143          * the corresponding bit value to 0". The rest must be set to 1. Hence
 144          * the bitwise NOT in front.
 145          */
 146         tx.cs = ~cs_mask;
 147
 148         return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx));
 149 }
 150
 151 /*
 152  * Select one CS line. The other lines will be un-selected.
 153  */
 154 static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs)
 155 {
 156         return dln2_spi_cs_set(dln2, BIT(cs));
 157 }
 158
 159 /*
 160  * Enable/disable CS lines for usage. The module has to be disabled first.
 161  */
 162 static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
 163 {
 164         struct {
 165                 u8 port;
 166                 u8 cs;
 167         } tx;
 168         u16 cmd;
 169
 170         tx.port = dln2->port;
 171         tx.cs = cs_mask;
 172         cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE;
 173
 174         return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx));
 175 }
 176
 177 static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
 178 {
 179         u8 cs_mask = GENMASK(dln2->host->num_chipselect - 1, 0);
 180
 181         return dln2_spi_cs_enable(dln2, cs_mask, enable);
 182 }
 183
 184 static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num)
 185 {
 186         int ret;
 187         struct {
 188                 u8 port;
 189         } tx;
 190         struct {
 191                 __le16 cs_count;
 192         } rx;
 193         unsigned rx_len = sizeof(rx);
 194
 195         tx.port = dln2->port;
 196         ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx),
 197                             &rx, &rx_len);
 198         if (ret < 0)
 199                 return ret;
 200         if (rx_len < sizeof(rx))
 201                 return -EPROTO;
 202
 203         *cs_num = le16_to_cpu(rx.cs_count);
 204
 205         dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num);
 206
 207         return 0;
 208 }
 209
 210 static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq)
 211 {
 212         int ret;
 213         struct {
 214                 u8 port;
 215         } tx;
 216         struct {
 217                 __le32 speed;
 218         } rx;
 219         unsigned rx_len = sizeof(rx);
 220
 221         tx.port = dln2->port;
 222
 223         ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len);
 224         if (ret < 0)
 225                 return ret;
 226         if (rx_len < sizeof(rx))
 227                 return -EPROTO;
 228
 229         *freq = le32_to_cpu(rx.speed);
 230
 231         return 0;
 232 }
 233
 234 /*
 235  * Get bus min/max frequencies.
 236  */
 237 static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax)
 238 {
 239         int ret;
 240
 241         ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin);
 242         if (ret < 0)
 243                 return ret;
 244
 245         ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax);
 246         if (ret < 0)
 247                 return ret;
 248
 249         dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n",
 250                 *fmin, *fmax);
 251
 252         return 0;
 253 }
 254
 255 /*
 256  * Set the bus speed. The module will automatically round down to the closest
 257  * available frequency and returns it. The module has to be disabled first.
 258  */
 259 static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed)
 260 {
 261         int ret;
 262         struct {
 263                 u8 port;
 264                 __le32 speed;
 265         } __packed tx;
 266         struct {
 267                 __le32 speed;
 268         } rx;
 269         int rx_len = sizeof(rx);
 270
 271         tx.port = dln2->port;
 272         tx.speed = cpu_to_le32(speed);
 273
 274         ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx),
 275                             &rx, &rx_len);
 276         if (ret < 0)
 277                 return ret;
 278         if (rx_len < sizeof(rx))
 279                 return -EPROTO;
 280
 281         return 0;
 282 }
 283
 284 /*
 285  * Change CPOL & CPHA. The module has to be disabled first.
 286  */
 287 static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode)
 288 {
 289         struct {
 290                 u8 port;
 291                 u8 mode;
 292         } tx;
 293
 294         tx.port = dln2->port;
 295         tx.mode = mode;
 296
 297         return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx));
 298 }
 299
 300 /*
 301  * Change frame size. The module has to be disabled first.
 302  */
 303 static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw)
 304 {
 305         struct {
 306                 u8 port;
 307                 u8 bpw;
 308         } tx;
 309
 310         tx.port = dln2->port;
 311         tx.bpw = bpw;
 312
 313         return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE,
 314                                 &tx, sizeof(tx));
 315 }
 316
 317 static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2,
 318                                               u32 *bpw_mask)
 319 {
 320         int ret;
 321         struct {
 322                 u8 port;
 323         } tx;
 324         struct {
 325                 u8 count;
 326                 u8 frame_sizes[36];
 327         } *rx = dln2->buf;
 328         unsigned rx_len = sizeof(*rx);
 329         int i;
 330
 331         tx.port = dln2->port;
 332
 333         ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES,
 334                             &tx, sizeof(tx), rx, &rx_len);
 335         if (ret < 0)
 336                 return ret;
 337         if (rx_len < sizeof(*rx))
 338                 return -EPROTO;
 339         if (rx->count > ARRAY_SIZE(rx->frame_sizes))
 340                 return -EPROTO;
 341
 342         *bpw_mask = 0;
 343         for (i = 0; i < rx->count; i++)
 344                 *bpw_mask |= BIT(rx->frame_sizes[i] - 1);
 345
 346         dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask);
 347
 348         return 0;
 349 }
 350
 351 /*
 352  * Copy the data to DLN2 buffer and change the byte order to LE, requested by
 353  * DLN2 module. SPI core makes sure that the data length is a multiple of word
 354  * size.
 355  */
 356 static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw)
 357 {
 358 #ifdef __LITTLE_ENDIAN
 359         memcpy(dln2_buf, src, len);
 360 #else
 361         if (bpw <= 8) {
 362                 memcpy(dln2_buf, src, len);
 363         } else if (bpw <= 16) {
 364                 __le16 *d = (__le16 *)dln2_buf;
 365                 u16 *s = (u16 *)src;
 366
 367                 len = len / 2;
 368                 while (len--)
 369                         *d++ = cpu_to_le16p(s++);
 370         } else {
 371                 __le32 *d = (__le32 *)dln2_buf;
 372                 u32 *s = (u32 *)src;
 373
 374                 len = len / 4;
 375                 while (len--)
 376                         *d++ = cpu_to_le32p(s++);
 377         }
 378 #endif
 379
 380         return 0;
 381 }
 382
 383 /*
 384  * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2
 385  * buffer is LE ordered. SPI core makes sure that the data length is a multiple
 386  * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make
 387  * sure we avoid unaligned accesses for 32 bit case.
 388  */
 389 static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw)
 390 {
 391 #ifdef __LITTLE_ENDIAN
 392         memcpy(dest, dln2_buf, len);
 393 #else
 394         if (bpw <= 8) {
 395                 memcpy(dest, dln2_buf, len);
 396         } else if (bpw <= 16) {
 397                 u16 *d = (u16 *)dest;
 398                 __le16 *s = (__le16 *)dln2_buf;
 399
 400                 len = len / 2;
 401                 while (len--)
 402                         *d++ = le16_to_cpup(s++);
 403         } else {
 404                 u32 *d = (u32 *)dest;
 405                 __le32 *s = (__le32 *)dln2_buf;
 406
 407                 len = len / 4;
 408                 while (len--)
 409                         *d++ = get_unaligned_le32(s++);
 410         }
 411 #endif
 412
 413         return 0;
 414 }
 415
 416 /*
 417  * Perform one write operation.
 418  */
 419 static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data,
 420                               u16 data_len, u8 attr)
 421 {
 422         struct {
 423                 u8 port;
 424                 __le16 size;
 425                 u8 attr;
 426                 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
 427         } __packed *tx = dln2->buf;
 428         unsigned tx_len;
 429
 430         BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE);
 431
 432         if (data_len > DLN2_SPI_MAX_XFER_SIZE)
 433                 return -EINVAL;
 434
 435         tx->port = dln2->port;
 436         tx->size = cpu_to_le16(data_len);
 437         tx->attr = attr;
 438
 439         dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw);
 440
 441         tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
 442         return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len);
 443 }
 444
 445 /*
 446  * Perform one read operation.
 447  */
 448 static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data,
 449                              u16 data_len, u8 attr)
 450 {
 451         int ret;
 452         struct {
 453                 u8 port;
 454                 __le16 size;
 455                 u8 attr;
 456         } __packed tx;
 457         struct {
 458                 __le16 size;
 459                 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
 460         } __packed *rx = dln2->buf;
 461         unsigned rx_len = sizeof(*rx);
 462
 463         BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE);
 464
 465         if (data_len > DLN2_SPI_MAX_XFER_SIZE)
 466                 return -EINVAL;
 467
 468         tx.port = dln2->port;
 469         tx.size = cpu_to_le16(data_len);
 470         tx.attr = attr;
 471
 472         ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx),
 473                             rx, &rx_len);
 474         if (ret < 0)
 475                 return ret;
 476         if (rx_len < sizeof(rx->size) + data_len)
 477                 return -EPROTO;
 478         if (le16_to_cpu(rx->size) != data_len)
 479                 return -EPROTO;
 480
 481         dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw);
 482
 483         return 0;
 484 }
 485
 486 /*
 487  * Perform one write & read operation.
 488  */
 489 static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data,
 490                                    u8 *rx_data, u16 data_len, u8 attr)
 491 {
 492         int ret;
 493         struct {
 494                 u8 port;
 495                 __le16 size;
 496                 u8 attr;
 497                 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
 498         } __packed *tx;
 499         struct {
 500                 __le16 size;
 501                 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
 502         } __packed *rx;
 503         unsigned tx_len, rx_len;
 504
 505         BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE ||
 506                      sizeof(*rx) > DLN2_SPI_BUF_SIZE);
 507
 508         if (data_len > DLN2_SPI_MAX_XFER_SIZE)
 509                 return -EINVAL;
 510
 511         /*
 512          * Since this is a pseudo full-duplex communication, we're perfectly
 513          * safe to use the same buffer for both tx and rx. When DLN2 sends the
 514          * response back, with the rx data, we don't need the tx buffer anymore.
 515          */
 516         tx = dln2->buf;
 517         rx = dln2->buf;
 518
 519         tx->port = dln2->port;
 520         tx->size = cpu_to_le16(data_len);
 521         tx->attr = attr;
 522
 523         dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw);
 524
 525         tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
 526         rx_len = sizeof(*rx);
 527
 528         ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len,
 529                             rx, &rx_len);
 530         if (ret < 0)
 531                 return ret;
 532         if (rx_len < sizeof(rx->size) + data_len)
 533                 return -EPROTO;
 534         if (le16_to_cpu(rx->size) != data_len)
 535                 return -EPROTO;
 536
 537         dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw);
 538
 539         return 0;
 540 }
 541
 542 /*
 543  * Read/Write wrapper. It will automatically split an operation into multiple
 544  * single ones due to device buffer constraints.
 545  */
 546 static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
 547                          u8 *rx_data, u16 data_len, u8 attr)
 548 {
 549         int ret;
 550         u16 len;
 551         u8 temp_attr;
 552         u16 remaining = data_len;
 553         u16 offset;
 554
 555         do {
 556                 if (remaining > DLN2_SPI_MAX_XFER_SIZE) {
 557                         len = DLN2_SPI_MAX_XFER_SIZE;
 558                         temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
 559                 } else {
 560                         len = remaining;
 561                         temp_attr = attr;
 562                 }
 563
 564                 offset = data_len - remaining;
 565
 566                 if (tx_data && rx_data) {
 567                         ret = dln2_spi_read_write_one(dln2,
 568                                                       tx_data + offset,
 569                                                       rx_data + offset,
 570                                                       len, temp_attr);
 571                 } else if (tx_data) {
 572                         ret = dln2_spi_write_one(dln2,
 573                                                  tx_data + offset,
 574                                                  len, temp_attr);
 575                 } else if (rx_data) {
 576                         ret = dln2_spi_read_one(dln2,
 577                                                 rx_data + offset,
 578                                                 len, temp_attr);
 579                  } else {
 580                         return -EINVAL;
 581                  }
 582
 583                 if (ret < 0)
 584                         return ret;
 585
 586                 remaining -= len;
 587         } while (remaining);
 588
 589         return 0;
 590 }
 591
 592 static int dln2_spi_prepare_message(struct spi_controller *host,
 593                                     struct spi_message *message)
 594 {
 595         int ret;
 596         struct dln2_spi *dln2 = spi_controller_get_devdata(host);
 597         struct spi_device *spi = message->spi;
 598
 599         if (dln2->cs != spi_get_chipselect(spi, 0)) {
 600                 ret = dln2_spi_cs_set_one(dln2, spi_get_chipselect(spi, 0));
 601                 if (ret < 0)
 602                         return ret;
 603
 604                 dln2->cs = spi_get_chipselect(spi, 0);
 605         }
 606
 607         return 0;
 608 }
 609
 610 static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
 611                                    u8 bpw, u8 mode)
 612 {
 613         int ret;
 614         bool bus_setup_change;
 615
 616         bus_setup_change = dln2->speed != speed || dln2->mode != mode ||
 617                            dln2->bpw != bpw;
 618
 619         if (!bus_setup_change)
 620                 return 0;
 621
 622         ret = dln2_spi_enable(dln2, false);
 623         if (ret < 0)
 624                 return ret;
 625
 626         if (dln2->speed != speed) {
 627                 ret = dln2_spi_set_speed(dln2, speed);
 628                 if (ret < 0)
 629                         return ret;
 630
 631                 dln2->speed = speed;
 632         }
 633
 634         if (dln2->mode != mode) {
 635                 ret = dln2_spi_set_mode(dln2, mode & 0x3);
 636                 if (ret < 0)
 637                         return ret;
 638
 639                 dln2->mode = mode;
 640         }
 641
 642         if (dln2->bpw != bpw) {
 643                 ret = dln2_spi_set_bpw(dln2, bpw);
 644                 if (ret < 0)
 645                         return ret;
 646
 647                 dln2->bpw = bpw;
 648         }
 649
 650         return dln2_spi_enable(dln2, true);
 651 }
 652
 653 static int dln2_spi_transfer_one(struct spi_controller *host,
 654                                  struct spi_device *spi,
 655                                  struct spi_transfer *xfer)
 656 {
 657         struct dln2_spi *dln2 = spi_controller_get_devdata(host);
 658         int status;
 659         u8 attr = 0;
 660
 661         status = dln2_spi_transfer_setup(dln2, xfer->speed_hz,
 662                                          xfer->bits_per_word,
 663                                          spi->mode);
 664         if (status < 0) {
 665                 dev_err(&dln2->pdev->dev, "Cannot setup transfer\n");
 666                 return status;
 667         }
 668
 669         if (!xfer->cs_change && !spi_transfer_is_last(host, xfer))
 670                 attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
 671
 672         status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
 673                                xfer->len, attr);
 674         if (status < 0)
 675                 dev_err(&dln2->pdev->dev, "write/read failed!\n");
 676
 677         return status;
 678 }
 679
 680 static int dln2_spi_probe(struct platform_device *pdev)
 681 {
 682         struct spi_controller *host;
 683         struct dln2_spi *dln2;
 684         struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
 685         struct device *dev = &pdev->dev;
 686         int ret;
 687
 688         host = spi_alloc_host(&pdev->dev, sizeof(*dln2));
 689         if (!host)
 690                 return -ENOMEM;
 691
 692         device_set_node(&host->dev, dev_fwnode(dev));
 693
 694         platform_set_drvdata(pdev, host);
 695
 696         dln2 = spi_controller_get_devdata(host);
 697
 698         dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
 699         if (!dln2->buf) {
 700                 ret = -ENOMEM;
 701                 goto exit_free_host;
 702         }
 703
 704         dln2->host = host;
 705         dln2->pdev = pdev;
 706         dln2->port = pdata->port;
 707         /* cs/mode can never be 0xff, so the first transfer will set them */
 708         dln2->cs = 0xff;
 709         dln2->mode = 0xff;
 710
 711         /* disable SPI module before continuing with the setup */
 712         ret = dln2_spi_enable(dln2, false);
 713         if (ret < 0) {
 714                 dev_err(&pdev->dev, "Failed to disable SPI module\n");
 715                 goto exit_free_host;
 716         }
 717
 718         ret = dln2_spi_get_cs_num(dln2, &host->num_chipselect);
 719         if (ret < 0) {
 720                 dev_err(&pdev->dev, "Failed to get number of CS pins\n");
 721                 goto exit_free_host;
 722         }
 723
 724         ret = dln2_spi_get_speed_range(dln2,
 725                                        &host->min_speed_hz,
 726                                        &host->max_speed_hz);
 727         if (ret < 0) {
 728                 dev_err(&pdev->dev, "Failed to read bus min/max freqs\n");
 729                 goto exit_free_host;
 730         }
 731
 732         ret = dln2_spi_get_supported_frame_sizes(dln2,
 733                                                  &host->bits_per_word_mask);
 734         if (ret < 0) {
 735                 dev_err(&pdev->dev, "Failed to read supported frame sizes\n");
 736                 goto exit_free_host;
 737         }
 738
 739         ret = dln2_spi_cs_enable_all(dln2, true);
 740         if (ret < 0) {
 741                 dev_err(&pdev->dev, "Failed to enable CS pins\n");
 742                 goto exit_free_host;
 743         }
 744
 745         host->bus_num = -1;
 746         host->mode_bits = SPI_CPOL | SPI_CPHA;
 747         host->prepare_message = dln2_spi_prepare_message;
 748         host->transfer_one = dln2_spi_transfer_one;
 749         host->auto_runtime_pm = true;
 750
 751         /* enable SPI module, we're good to go */
 752         ret = dln2_spi_enable(dln2, true);
 753         if (ret < 0) {
 754                 dev_err(&pdev->dev, "Failed to enable SPI module\n");
 755                 goto exit_free_host;
 756         }
 757
 758         pm_runtime_set_autosuspend_delay(&pdev->dev,
 759                                          DLN2_RPM_AUTOSUSPEND_TIMEOUT);
 760         pm_runtime_use_autosuspend(&pdev->dev);
 761         pm_runtime_set_active(&pdev->dev);
 762         pm_runtime_enable(&pdev->dev);
 763
 764         ret = devm_spi_register_controller(&pdev->dev, host);
 765         if (ret < 0) {
 766                 dev_err(&pdev->dev, "Failed to register host\n");
 767                 goto exit_register;
 768         }
 769
 770         return ret;
 771
 772 exit_register:
 773         pm_runtime_disable(&pdev->dev);
 774         pm_runtime_set_suspended(&pdev->dev);
 775
 776         if (dln2_spi_enable(dln2, false) < 0)
 777                 dev_err(&pdev->dev, "Failed to disable SPI module\n");
 778 exit_free_host:
 779         spi_controller_put(host);
 780
 781         return ret;
 782 }
 783
 784 static void dln2_spi_remove(struct platform_device *pdev)
 785 {
 786         struct spi_controller *host = platform_get_drvdata(pdev);
 787         struct dln2_spi *dln2 = spi_controller_get_devdata(host);
 788
 789         pm_runtime_disable(&pdev->dev);
 790
 791         if (dln2_spi_enable(dln2, false) < 0)
 792                 dev_err(&pdev->dev, "Failed to disable SPI module\n");
 793 }
 794
 795 #ifdef CONFIG_PM_SLEEP
 796 static int dln2_spi_suspend(struct device *dev)
 797 {
 798         int ret;
 799         struct spi_controller *host = dev_get_drvdata(dev);
 800         struct dln2_spi *dln2 = spi_controller_get_devdata(host);
 801
 802         ret = spi_controller_suspend(host);
 803         if (ret < 0)
 804                 return ret;
 805
 806         if (!pm_runtime_suspended(dev)) {
 807                 ret = dln2_spi_enable(dln2, false);
 808                 if (ret < 0)
 809                         return ret;
 810         }
 811
 812         /*
 813          * USB power may be cut off during sleep. Resetting the following
 814          * parameters will force the board to be set up before first transfer.
 815          */
 816         dln2->cs = 0xff;
 817         dln2->speed = 0;
 818         dln2->bpw = 0;
 819         dln2->mode = 0xff;
 820
 821         return 0;
 822 }
 823
 824 static int dln2_spi_resume(struct device *dev)
 825 {
 826         int ret;
 827         struct spi_controller *host = dev_get_drvdata(dev);
 828         struct dln2_spi *dln2 = spi_controller_get_devdata(host);
 829
 830         if (!pm_runtime_suspended(dev)) {
 831                 ret = dln2_spi_cs_enable_all(dln2, true);
 832                 if (ret < 0)
 833                         return ret;
 834
 835                 ret = dln2_spi_enable(dln2, true);
 836                 if (ret < 0)
 837                         return ret;
 838         }
 839
 840         return spi_controller_resume(host);
 841 }
 842 #endif /* CONFIG_PM_SLEEP */
 843
 844 #ifdef CONFIG_PM
 845 static int dln2_spi_runtime_suspend(struct device *dev)
 846 {
 847         struct spi_controller *host = dev_get_drvdata(dev);
 848         struct dln2_spi *dln2 = spi_controller_get_devdata(host);
 849
 850         return dln2_spi_enable(dln2, false);
 851 }
 852
 853 static int dln2_spi_runtime_resume(struct device *dev)
 854 {
 855         struct spi_controller *host = dev_get_drvdata(dev);
 856         struct dln2_spi *dln2 = spi_controller_get_devdata(host);
 857
 858         return  dln2_spi_enable(dln2, true);
 859 }
 860 #endif /* CONFIG_PM */
 861
 862 static const struct dev_pm_ops dln2_spi_pm = {
 863         SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume)
 864         SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend,
 865                            dln2_spi_runtime_resume, NULL)
 866 };
 867
 868 static struct platform_driver spi_dln2_driver = {
 869         .driver = {
 870                 .name   = "dln2-spi",
 871                 .pm     = &dln2_spi_pm,
 872         },
 873         .probe          = dln2_spi_probe,
 874         .remove         = dln2_spi_remove,
 875 };
 876 module_platform_driver(spi_dln2_driver);
 877
 878 MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI host interface");
 879 MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>");
 880 MODULE_LICENSE("GPL v2");
 881 MODULE_ALIAS("platform:dln2-spi");