drivers/spi/spi-dw.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __SPI_DW_H__
   3 #define __SPI_DW_H__
   4
   5 #include <linux/bits.h>
   6 #include <linux/completion.h>
   7 #include <linux/debugfs.h>
   8 #include <linux/irqreturn.h>
   9 #include <linux/io.h>
  10 #include <linux/scatterlist.h>
  11 #include <linux/spi/spi-mem.h>
  12 #include <linux/bitfield.h>
  13
  14 /* Synopsys DW SSI IP-core virtual IDs */
  15 #define DW_PSSI_ID                      0
  16 #define DW_HSSI_ID                      1
  17
  18 /* Synopsys DW SSI component versions (FourCC sequence) */
  19 #define DW_HSSI_102A                    0x3130322a
  20
  21 /* DW SSI IP-core ID and version check helpers */
  22 #define dw_spi_ip_is(_dws, _ip) \
  23         ((_dws)->ip == DW_ ## _ip ## _ID)
  24
  25 #define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \
  26         (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
  27
  28 #define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==)
  29
  30 #define dw_spi_ver_is_ge(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, >=)
  31
  32 /* DW SPI controller capabilities */
  33 #define DW_SPI_CAP_CS_OVERRIDE          BIT(0)
  34 #define DW_SPI_CAP_DFS32                BIT(1)
  35
  36 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
  37 #define DW_SPI_CTRLR0                   0x00
  38 #define DW_SPI_CTRLR1                   0x04
  39 #define DW_SPI_SSIENR                   0x08
  40 #define DW_SPI_MWCR                     0x0c
  41 #define DW_SPI_SER                      0x10
  42 #define DW_SPI_BAUDR                    0x14
  43 #define DW_SPI_TXFTLR                   0x18
  44 #define DW_SPI_RXFTLR                   0x1c
  45 #define DW_SPI_TXFLR                    0x20
  46 #define DW_SPI_RXFLR                    0x24
  47 #define DW_SPI_SR                       0x28
  48 #define DW_SPI_IMR                      0x2c
  49 #define DW_SPI_ISR                      0x30
  50 #define DW_SPI_RISR                     0x34
  51 #define DW_SPI_TXOICR                   0x38
  52 #define DW_SPI_RXOICR                   0x3c
  53 #define DW_SPI_RXUICR                   0x40
  54 #define DW_SPI_MSTICR                   0x44
  55 #define DW_SPI_ICR                      0x48
  56 #define DW_SPI_DMACR                    0x4c
  57 #define DW_SPI_DMATDLR                  0x50
  58 #define DW_SPI_DMARDLR                  0x54
  59 #define DW_SPI_IDR                      0x58
  60 #define DW_SPI_VERSION                  0x5c
  61 #define DW_SPI_DR                       0x60
  62 #define DW_SPI_RX_SAMPLE_DLY            0xf0
  63 #define DW_SPI_CS_OVERRIDE              0xf4
  64
  65 /* Bit fields in CTRLR0 (DWC APB SSI) */
  66 #define DW_PSSI_CTRLR0_DFS_MASK                 GENMASK(3, 0)
  67 #define DW_PSSI_CTRLR0_DFS32_MASK               GENMASK(20, 16)
  68
  69 #define DW_PSSI_CTRLR0_FRF_MASK                 GENMASK(5, 4)
  70 #define DW_SPI_CTRLR0_FRF_MOTO_SPI              0x0
  71 #define DW_SPI_CTRLR0_FRF_TI_SSP                0x1
  72 #define DW_SPI_CTRLR0_FRF_NS_MICROWIRE          0x2
  73 #define DW_SPI_CTRLR0_FRF_RESV                  0x3
  74
  75 #define DW_PSSI_CTRLR0_MODE_MASK                GENMASK(7, 6)
  76 #define DW_PSSI_CTRLR0_SCPHA                    BIT(6)
  77 #define DW_PSSI_CTRLR0_SCPOL                    BIT(7)
  78
  79 #define DW_PSSI_CTRLR0_TMOD_MASK                GENMASK(9, 8)
  80 #define DW_SPI_CTRLR0_TMOD_TR                   0x0     /* xmit & recv */
  81 #define DW_SPI_CTRLR0_TMOD_TO                   0x1     /* xmit only */
  82 #define DW_SPI_CTRLR0_TMOD_RO                   0x2     /* recv only */
  83 #define DW_SPI_CTRLR0_TMOD_EPROMREAD            0x3     /* eeprom read mode */
  84
  85 #define DW_PSSI_CTRLR0_SLV_OE                   BIT(10)
  86 #define DW_PSSI_CTRLR0_SRL                      BIT(11)
  87 #define DW_PSSI_CTRLR0_CFS                      BIT(12)
  88
  89 /* Bit fields in CTRLR0 (DWC SSI with AHB interface) */
  90 #define DW_HSSI_CTRLR0_DFS_MASK                 GENMASK(4, 0)
  91 #define DW_HSSI_CTRLR0_FRF_MASK                 GENMASK(7, 6)
  92 #define DW_HSSI_CTRLR0_SCPHA                    BIT(8)
  93 #define DW_HSSI_CTRLR0_SCPOL                    BIT(9)
  94 #define DW_HSSI_CTRLR0_TMOD_MASK                GENMASK(11, 10)
  95 #define DW_HSSI_CTRLR0_SRL                      BIT(13)
  96 #define DW_HSSI_CTRLR0_MST                      BIT(31)
  97
  98 /* Bit fields in CTRLR1 */
  99 #define DW_SPI_NDF_MASK                         GENMASK(15, 0)
 100
 101 /* Bit fields in SR, 7 bits */
 102 #define DW_SPI_SR_MASK                          GENMASK(6, 0)
 103 #define DW_SPI_SR_BUSY                          BIT(0)
 104 #define DW_SPI_SR_TF_NOT_FULL                   BIT(1)
 105 #define DW_SPI_SR_TF_EMPT                       BIT(2)
 106 #define DW_SPI_SR_RF_NOT_EMPT                   BIT(3)
 107 #define DW_SPI_SR_RF_FULL                       BIT(4)
 108 #define DW_SPI_SR_TX_ERR                        BIT(5)
 109 #define DW_SPI_SR_DCOL                          BIT(6)
 110
 111 /* Bit fields in ISR, IMR, RISR, 7 bits */
 112 #define DW_SPI_INT_MASK                         GENMASK(5, 0)
 113 #define DW_SPI_INT_TXEI                         BIT(0)
 114 #define DW_SPI_INT_TXOI                         BIT(1)
 115 #define DW_SPI_INT_RXUI                         BIT(2)
 116 #define DW_SPI_INT_RXOI                         BIT(3)
 117 #define DW_SPI_INT_RXFI                         BIT(4)
 118 #define DW_SPI_INT_MSTI                         BIT(5)
 119
 120 /* Bit fields in DMACR */
 121 #define DW_SPI_DMACR_RDMAE                      BIT(0)
 122 #define DW_SPI_DMACR_TDMAE                      BIT(1)
 123
 124 /* Mem/DMA operations helpers */
 125 #define DW_SPI_WAIT_RETRIES                     5
 126 #define DW_SPI_BUF_SIZE \
 127         (sizeof_field(struct spi_mem_op, cmd.opcode) + \
 128          sizeof_field(struct spi_mem_op, addr.val) + 256)
 129 #define DW_SPI_GET_BYTE(_val, _idx) \
 130         ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
 131
 132 /* Slave spi_transfer/spi_mem_op related */
 133 struct dw_spi_cfg {
 134         u8 tmode;
 135         u8 dfs;
 136         u32 ndf;
 137         u32 freq;
 138 };
 139
 140 struct dw_spi;
 141 struct dw_spi_dma_ops {
 142         int (*dma_init)(struct device *dev, struct dw_spi *dws);
 143         void (*dma_exit)(struct dw_spi *dws);
 144         int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
 145         bool (*can_dma)(struct spi_controller *host, struct spi_device *spi,
 146                         struct spi_transfer *xfer);
 147         int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
 148         void (*dma_stop)(struct dw_spi *dws);
 149 };
 150
 151 struct dw_spi {
 152         struct spi_controller   *host;
 153
 154         u32                     ip;             /* Synopsys DW SSI IP-core ID */
 155         u32                     ver;            /* Synopsys component version */
 156         u32                     caps;           /* DW SPI capabilities */
 157
 158         void __iomem            *regs;
 159         unsigned long           paddr;
 160         int                     irq;
 161         u32                     fifo_len;       /* depth of the FIFO buffer */
 162         unsigned int            dfs_offset;     /* CTRLR0 DFS field offset */
 163         u32                     max_mem_freq;   /* max mem-ops bus freq */
 164         u32                     max_freq;       /* max bus freq supported */
 165
 166         u32                     reg_io_width;   /* DR I/O width in bytes */
 167         u32                     num_cs;         /* chip select lines */
 168         u16                     bus_num;
 169         void (*set_cs)(struct spi_device *spi, bool enable);
 170
 171         /* Current message transfer state info */
 172         void                    *tx;
 173         unsigned int            tx_len;
 174         void                    *rx;
 175         unsigned int            rx_len;
 176         u8                      buf[DW_SPI_BUF_SIZE];
 177         int                     dma_mapped;
 178         u8                      n_bytes;        /* current is a 1/2 bytes op */
 179         irqreturn_t             (*transfer_handler)(struct dw_spi *dws);
 180         u32                     current_freq;   /* frequency in hz */
 181         u32                     cur_rx_sample_dly;
 182         u32                     def_rx_sample_dly_ns;
 183
 184         /* Custom memory operations */
 185         struct spi_controller_mem_ops mem_ops;
 186
 187         /* DMA info */
 188         struct dma_chan         *txchan;
 189         u32                     txburst;
 190         struct dma_chan         *rxchan;
 191         u32                     rxburst;
 192         u32                     dma_sg_burst;
 193         u32                     dma_addr_widths;
 194         unsigned long           dma_chan_busy;
 195         dma_addr_t              dma_addr; /* phy address of the Data register */
 196         const struct dw_spi_dma_ops *dma_ops;
 197         struct completion       dma_completion;
 198
 199 #ifdef CONFIG_DEBUG_FS
 200         struct dentry *debugfs;
 201         struct debugfs_regset32 regset;
 202 #endif
 203 };
 204
 205 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
 206 {
 207         return __raw_readl(dws->regs + offset);
 208 }
 209
 210 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
 211 {
 212         __raw_writel(val, dws->regs + offset);
 213 }
 214
 215 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
 216 {
 217         switch (dws->reg_io_width) {
 218         case 2:
 219                 return readw_relaxed(dws->regs + offset);
 220         case 4:
 221         default:
 222                 return readl_relaxed(dws->regs + offset);
 223         }
 224 }
 225
 226 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
 227 {
 228         switch (dws->reg_io_width) {
 229         case 2:
 230                 writew_relaxed(val, dws->regs + offset);
 231                 break;
 232         case 4:
 233         default:
 234                 writel_relaxed(val, dws->regs + offset);
 235                 break;
 236         }
 237 }
 238
 239 static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable)
 240 {
 241         dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
 242 }
 243
 244 static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div)
 245 {
 246         dw_writel(dws, DW_SPI_BAUDR, div);
 247 }
 248
 249 /* Disable IRQ bits */
 250 static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask)
 251 {
 252         u32 new_mask;
 253
 254         new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
 255         dw_writel(dws, DW_SPI_IMR, new_mask);
 256 }
 257
 258 /* Enable IRQ bits */
 259 static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask)
 260 {
 261         u32 new_mask;
 262
 263         new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
 264         dw_writel(dws, DW_SPI_IMR, new_mask);
 265 }
 266
 267 /*
 268  * This disables the SPI controller, interrupts, clears the interrupts status
 269  * and CS, then re-enables the controller back. Transmit and receive FIFO
 270  * buffers are cleared when the device is disabled.
 271  */
 272 static inline void dw_spi_reset_chip(struct dw_spi *dws)
 273 {
 274         dw_spi_enable_chip(dws, 0);
 275         dw_spi_mask_intr(dws, 0xff);
 276         dw_readl(dws, DW_SPI_ICR);
 277         dw_writel(dws, DW_SPI_SER, 0);
 278         dw_spi_enable_chip(dws, 1);
 279 }
 280
 281 static inline void dw_spi_shutdown_chip(struct dw_spi *dws)
 282 {
 283         dw_spi_enable_chip(dws, 0);
 284         dw_spi_set_clk(dws, 0);
 285 }
 286
 287 extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
 288 extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
 289                                  struct dw_spi_cfg *cfg);
 290 extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
 291 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
 292 extern void dw_spi_remove_host(struct dw_spi *dws);
 293 extern int dw_spi_suspend_host(struct dw_spi *dws);
 294 extern int dw_spi_resume_host(struct dw_spi *dws);
 295
 296 #ifdef CONFIG_SPI_DW_DMA
 297
 298 extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
 299 extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
 300
 301 #else
 302
 303 static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
 304 static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
 305
 306 #endif /* !CONFIG_SPI_DW_DMA */
 307
 308 #endif /* __SPI_DW_H__ */