drivers/thermal/qcom/lmh.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 /*
   4  * Copyright (C) 2021, Linaro Limited. All rights reserved.
   5  */
   6 #include <linux/module.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/irqdomain.h>
   9 #include <linux/err.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/slab.h>
  13 #include <linux/firmware/qcom/qcom_scm.h>
  14
  15 #define LMH_NODE_DCVS                   0x44435653
  16 #define LMH_CLUSTER0_NODE_ID            0x6370302D
  17 #define LMH_CLUSTER1_NODE_ID            0x6370312D
  18
  19 #define LMH_SUB_FN_THERMAL              0x54484D4C
  20 #define LMH_SUB_FN_CRNT                 0x43524E54
  21 #define LMH_SUB_FN_REL                  0x52454C00
  22 #define LMH_SUB_FN_BCL                  0x42434C00
  23
  24 #define LMH_ALGO_MODE_ENABLE            0x454E424C
  25 #define LMH_TH_HI_THRESHOLD             0x48494748
  26 #define LMH_TH_LOW_THRESHOLD            0x4C4F5700
  27 #define LMH_TH_ARM_THRESHOLD            0x41524D00
  28
  29 #define LMH_REG_DCVS_INTR_CLR           0x8
  30
  31 #define LMH_ENABLE_ALGOS                1
  32
  33 struct lmh_hw_data {
  34         void __iomem *base;
  35         struct irq_domain *domain;
  36         int irq;
  37 };
  38
  39 static irqreturn_t lmh_handle_irq(int hw_irq, void *data)
  40 {
  41         struct lmh_hw_data *lmh_data = data;
  42         int irq = irq_find_mapping(lmh_data->domain, 0);
  43
  44         /* Call the cpufreq driver to handle the interrupt */
  45         if (irq)
  46                 generic_handle_irq(irq);
  47
  48         return IRQ_HANDLED;
  49 }
  50
  51 static void lmh_enable_interrupt(struct irq_data *d)
  52 {
  53         struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
  54
  55         /* Clear the existing interrupt */
  56         writel(0xff, lmh_data->base + LMH_REG_DCVS_INTR_CLR);
  57         enable_irq(lmh_data->irq);
  58 }
  59
  60 static void lmh_disable_interrupt(struct irq_data *d)
  61 {
  62         struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
  63
  64         disable_irq_nosync(lmh_data->irq);
  65 }
  66
  67 static struct irq_chip lmh_irq_chip = {
  68         .name           = "lmh",
  69         .irq_enable     = lmh_enable_interrupt,
  70         .irq_disable    = lmh_disable_interrupt
  71 };
  72
  73 static int lmh_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  74 {
  75         struct lmh_hw_data *lmh_data = d->host_data;
  76         static struct lock_class_key lmh_lock_key;
  77         static struct lock_class_key lmh_request_key;
  78
  79         /*
  80          * This lock class tells lockdep that GPIO irqs are in a different
  81          * category than their parents, so it won't report false recursion.
  82          */
  83         irq_set_lockdep_class(irq, &lmh_lock_key, &lmh_request_key);
  84         irq_set_chip_and_handler(irq, &lmh_irq_chip, handle_simple_irq);
  85         irq_set_chip_data(irq, lmh_data);
  86
  87         return 0;
  88 }
  89
  90 static const struct irq_domain_ops lmh_irq_ops = {
  91         .map = lmh_irq_map,
  92         .xlate = irq_domain_xlate_onecell,
  93 };
  94
  95 static int lmh_probe(struct platform_device *pdev)
  96 {
  97         struct device *dev = &pdev->dev;
  98         struct device_node *np = dev->of_node;
  99         struct device_node *cpu_node;
 100         struct lmh_hw_data *lmh_data;
 101         int temp_low, temp_high, temp_arm, cpu_id, ret;
 102         unsigned int enable_alg;
 103         u32 node_id;
 104
 105         if (!qcom_scm_is_available())
 106                 return -EPROBE_DEFER;
 107
 108         lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL);
 109         if (!lmh_data)
 110                 return -ENOMEM;
 111
 112         lmh_data->base = devm_platform_ioremap_resource(pdev, 0);
 113         if (IS_ERR(lmh_data->base))
 114                 return PTR_ERR(lmh_data->base);
 115
 116         cpu_node = of_parse_phandle(np, "cpus", 0);
 117         if (!cpu_node)
 118                 return -EINVAL;
 119         cpu_id = of_cpu_node_to_id(cpu_node);
 120         of_node_put(cpu_node);
 121
 122         ret = of_property_read_u32(np, "qcom,lmh-temp-high-millicelsius", &temp_high);
 123         if (ret) {
 124                 dev_err(dev, "missing qcom,lmh-temp-high-millicelsius property\n");
 125                 return ret;
 126         }
 127
 128         ret = of_property_read_u32(np, "qcom,lmh-temp-low-millicelsius", &temp_low);
 129         if (ret) {
 130                 dev_err(dev, "missing qcom,lmh-temp-low-millicelsius property\n");
 131                 return ret;
 132         }
 133
 134         ret = of_property_read_u32(np, "qcom,lmh-temp-arm-millicelsius", &temp_arm);
 135         if (ret) {
 136                 dev_err(dev, "missing qcom,lmh-temp-arm-millicelsius property\n");
 137                 return ret;
 138         }
 139
 140         /*
 141          * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed
 142          * for other platforms, revisit this to check if the <cpu-id, node-id> should be part
 143          * of a dt match table.
 144          */
 145         if (cpu_id == 0) {
 146                 node_id = LMH_CLUSTER0_NODE_ID;
 147         } else if (cpu_id == 4) {
 148                 node_id = LMH_CLUSTER1_NODE_ID;
 149         } else {
 150                 dev_err(dev, "Wrong CPU id associated with LMh node\n");
 151                 return -EINVAL;
 152         }
 153
 154         if (!qcom_scm_lmh_dcvsh_available())
 155                 return -EINVAL;
 156
 157         enable_alg = (uintptr_t)of_device_get_match_data(dev);
 158
 159         if (enable_alg) {
 160                 ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
 161                                          LMH_NODE_DCVS, node_id, 0);
 162                 if (ret)
 163                         dev_err(dev, "Error %d enabling current subfunction\n", ret);
 164
 165                 ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
 166                                          LMH_NODE_DCVS, node_id, 0);
 167                 if (ret)
 168                         dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
 169
 170                 ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
 171                                          LMH_NODE_DCVS, node_id, 0);
 172                 if (ret)
 173                         dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
 174
 175                 ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
 176                                          LMH_NODE_DCVS, node_id, 0);
 177                 if (ret) {
 178                         dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
 179                         return ret;
 180                 }
 181
 182                 ret = qcom_scm_lmh_profile_change(0x1);
 183                 if (ret) {
 184                         dev_err(dev, "Error %d changing profile\n", ret);
 185                         return ret;
 186                 }
 187         }
 188
 189         /* Set default thermal trips */
 190         ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_ARM_THRESHOLD, temp_arm,
 191                                  LMH_NODE_DCVS, node_id, 0);
 192         if (ret) {
 193                 dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
 194                 return ret;
 195         }
 196
 197         ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_HI_THRESHOLD, temp_high,
 198                                  LMH_NODE_DCVS, node_id, 0);
 199         if (ret) {
 200                 dev_err(dev, "Error setting thermal HI threshold%d\n", ret);
 201                 return ret;
 202         }
 203
 204         ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_LOW_THRESHOLD, temp_low,
 205                                  LMH_NODE_DCVS, node_id, 0);
 206         if (ret) {
 207                 dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
 208                 return ret;
 209         }
 210
 211         lmh_data->irq = platform_get_irq(pdev, 0);
 212         lmh_data->domain = irq_domain_add_linear(np, 1, &lmh_irq_ops, lmh_data);
 213         if (!lmh_data->domain) {
 214                 dev_err(dev, "Error adding irq_domain\n");
 215                 return -EINVAL;
 216         }
 217
 218         /* Disable the irq and let cpufreq enable it when ready to handle the interrupt */
 219         irq_set_status_flags(lmh_data->irq, IRQ_NOAUTOEN);
 220         ret = devm_request_irq(dev, lmh_data->irq, lmh_handle_irq,
 221                                IRQF_ONESHOT | IRQF_NO_SUSPEND,
 222                                "lmh-irq", lmh_data);
 223         if (ret) {
 224                 dev_err(dev, "Error %d registering irq %x\n", ret, lmh_data->irq);
 225                 irq_domain_remove(lmh_data->domain);
 226                 return ret;
 227         }
 228
 229         return 0;
 230 }
 231
 232 static const struct of_device_id lmh_table[] = {
 233         { .compatible = "qcom,sc8180x-lmh", },
 234         { .compatible = "qcom,sdm845-lmh", .data = (void *)LMH_ENABLE_ALGOS},
 235         { .compatible = "qcom,sm8150-lmh", },
 236         {}
 237 };
 238 MODULE_DEVICE_TABLE(of, lmh_table);
 239
 240 static struct platform_driver lmh_driver = {
 241         .probe = lmh_probe,
 242         .driver = {
 243                 .name = "qcom-lmh",
 244                 .of_match_table = lmh_table,
 245                 .suppress_bind_attrs = true,
 246         },
 247 };
 248 module_platform_driver(lmh_driver);
 249
 250 MODULE_LICENSE("GPL v2");
 251 MODULE_DESCRIPTION("QCOM LMh driver");