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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / tty / serial / imx.c
blob17f70e4bee4358a64f17c6e4bf375798f3689ca2
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/circ_buf.h>
12 #include <linux/module.h>
13 #include <linux/ioport.h>
14 #include <linux/init.h>
15 #include <linux/console.h>
16 #include <linux/sysrq.h>
17 #include <linux/platform_device.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/ktime.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/rational.h>
27 #include <linux/slab.h>
28 #include <linux/of.h>
29 #include <linux/io.h>
30 #include <linux/iopoll.h>
31 #include <linux/dma-mapping.h>
32
33 #include <asm/irq.h>
34 #include <linux/dma/imx-dma.h>
35
36 #include "serial_mctrl_gpio.h"
37
38 /* Register definitions */
39 #define URXD0 0x0 /* Receiver Register */
40 #define URTX0 0x40 /* Transmitter Register */
41 #define UCR1 0x80 /* Control Register 1 */
42 #define UCR2 0x84 /* Control Register 2 */
43 #define UCR3 0x88 /* Control Register 3 */
44 #define UCR4 0x8c /* Control Register 4 */
45 #define UFCR 0x90 /* FIFO Control Register */
46 #define USR1 0x94 /* Status Register 1 */
47 #define USR2 0x98 /* Status Register 2 */
48 #define UESC 0x9c /* Escape Character Register */
49 #define UTIM 0xa0 /* Escape Timer Register */
50 #define UBIR 0xa4 /* BRM Incremental Register */
51 #define UBMR 0xa8 /* BRM Modulator Register */
52 #define UBRC 0xac /* Baud Rate Count Register */
53 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
54 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
55 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
56
57 /* UART Control Register Bit Fields.*/
58 #define URXD_DUMMY_READ (1<<16)
59 #define URXD_CHARRDY (1<<15)
60 #define URXD_ERR (1<<14)
61 #define URXD_OVRRUN (1<<13)
62 #define URXD_FRMERR (1<<12)
63 #define URXD_BRK (1<<11)
64 #define URXD_PRERR (1<<10)
65 #define URXD_RX_DATA (0xFF<<0)
66 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
67 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
68 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
69 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
70 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
71 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
72 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
73 #define UCR1_IREN (1<<7) /* Infrared interface enable */
74 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
75 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
76 #define UCR1_SNDBRK (1<<4) /* Send break */
77 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
78 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
79 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
80 #define UCR1_DOZE (1<<1) /* Doze */
81 #define UCR1_UARTEN (1<<0) /* UART enabled */
82 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
83 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
84 #define UCR2_CTSC (1<<13) /* CTS pin control */
85 #define UCR2_CTS (1<<12) /* Clear to send */
86 #define UCR2_ESCEN (1<<11) /* Escape enable */
87 #define UCR2_PREN (1<<8) /* Parity enable */
88 #define UCR2_PROE (1<<7) /* Parity odd/even */
89 #define UCR2_STPB (1<<6) /* Stop */
90 #define UCR2_WS (1<<5) /* Word size */
91 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
92 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
93 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
94 #define UCR2_RXEN (1<<1) /* Receiver enabled */
95 #define UCR2_SRST (1<<0) /* SW reset */
96 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
97 #define UCR3_PARERREN (1<<12) /* Parity enable */
98 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
99 #define UCR3_DSR (1<<10) /* Data set ready */
100 #define UCR3_DCD (1<<9) /* Data carrier detect */
101 #define UCR3_RI (1<<8) /* Ring indicator */
102 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
103 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
104 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
105 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
106 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
107 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
108 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
109 #define UCR3_BPEN (1<<0) /* Preset registers enable */
110 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
111 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
112 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
113 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
114 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
115 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
116 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
117 #define UCR4_IRSC (1<<5) /* IR special case */
118 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
119 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
120 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
121 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
122 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
123 #define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */
124 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
125 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
127 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
128 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
129 #define USR1_RTSS (1<<14) /* RTS pin status */
130 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
131 #define USR1_RTSD (1<<12) /* RTS delta */
132 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
133 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
134 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
135 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
136 #define USR1_DTRD (1<<7) /* DTR Delta */
137 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
138 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
139 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
140 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
141 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
142 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
143 #define USR2_IDLE (1<<12) /* Idle condition */
144 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
145 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
146 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
147 #define USR2_WAKE (1<<7) /* Wake */
148 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
149 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
150 #define USR2_TXDC (1<<3) /* Transmitter complete */
151 #define USR2_BRCD (1<<2) /* Break condition */
152 #define USR2_ORE (1<<1) /* Overrun error */
153 #define USR2_RDR (1<<0) /* Recv data ready */
154 #define UTS_FRCPERR (1<<13) /* Force parity error */
155 #define UTS_LOOP (1<<12) /* Loop tx and rx */
156 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
157 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
158 #define UTS_TXFULL (1<<4) /* TxFIFO full */
159 #define UTS_RXFULL (1<<3) /* RxFIFO full */
160 #define UTS_SOFTRST (1<<0) /* Software reset */
161
162 /* We've been assigned a range on the "Low-density serial ports" major */
163 #define SERIAL_IMX_MAJOR 207
164 #define MINOR_START 16
165 #define DEV_NAME "ttymxc"
166
167 /*
168 * This determines how often we check the modem status signals
169 * for any change. They generally aren't connected to an IRQ
170 * so we have to poll them. We also check immediately before
171 * filling the TX fifo incase CTS has been dropped.
172 */
173 #define MCTRL_TIMEOUT (250*HZ/1000)
174
175 #define DRIVER_NAME "IMX-uart"
176
177 #define UART_NR 8
178
179 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
180 enum imx_uart_type {
181 IMX1_UART,
182 IMX21_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* counter to stop 0xff flood */
214 int idle_counter;
215
216 /* DMA fields */
217 unsigned int dma_is_enabled:1;
218 unsigned int dma_is_rxing:1;
219 unsigned int dma_is_txing:1;
220 struct dma_chan *dma_chan_rx, *dma_chan_tx;
221 struct scatterlist rx_sgl, tx_sgl[2];
222 void *rx_buf;
223 struct circ_buf rx_ring;
224 unsigned int rx_buf_size;
225 unsigned int rx_period_length;
226 unsigned int rx_periods;
227 dma_cookie_t rx_cookie;
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 unsigned int saved_reg[10];
231 bool context_saved;
232
233 bool last_putchar_was_newline;
234
235 enum imx_tx_state tx_state;
236 struct hrtimer trigger_start_tx;
237 struct hrtimer trigger_stop_tx;
238 };
239
240 struct imx_port_ucrs {
241 unsigned int ucr1;
242 unsigned int ucr2;
243 unsigned int ucr3;
244 };
245
246 static const struct imx_uart_data imx_uart_imx1_devdata = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249 };
250
251 static const struct imx_uart_data imx_uart_imx21_devdata = {
252 .uts_reg = IMX21_UTS,
253 .devtype = IMX21_UART,
254 };
255
256 static const struct of_device_id imx_uart_dt_ids[] = {
257 /*
258 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are
259 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
260 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
261 * doesn't make any distinction between these two variants.
262 */
263 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
264 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
265 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
266 { /* sentinel */ }
267 };
268 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
269
270 static inline struct imx_port *to_imx_port(struct uart_port *port)
271 {
272 return container_of(port, struct imx_port, port);
273 }
274
275 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
276 {
277 writel(val, sport->port.membase + offset);
278 }
279
280 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
281 {
282 return readl(sport->port.membase + offset);
283 }
284
285 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
286 {
287 return sport->devdata->uts_reg;
288 }
289
290 static inline int imx_uart_is_imx1(struct imx_port *sport)
291 {
292 return sport->devdata->devtype == IMX1_UART;
293 }
294
295 /*
296 * Save and restore functions for UCR1, UCR2 and UCR3 registers
297 */
298 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
299 static void imx_uart_ucrs_save(struct imx_port *sport,
300 struct imx_port_ucrs *ucr)
301 {
302 /* save control registers */
303 ucr->ucr1 = imx_uart_readl(sport, UCR1);
304 ucr->ucr2 = imx_uart_readl(sport, UCR2);
305 ucr->ucr3 = imx_uart_readl(sport, UCR3);
306 }
307
308 static void imx_uart_ucrs_restore(struct imx_port *sport,
309 struct imx_port_ucrs *ucr)
310 {
311 /* restore control registers */
312 imx_uart_writel(sport, ucr->ucr1, UCR1);
313 imx_uart_writel(sport, ucr->ucr2, UCR2);
314 imx_uart_writel(sport, ucr->ucr3, UCR3);
315 }
316 #endif
317
318 /* called with port.lock taken and irqs caller dependent */
319 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
320 {
321 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
322
323 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
324 }
325
326 /* called with port.lock taken and irqs caller dependent */
327 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
328 {
329 *ucr2 &= ~UCR2_CTSC;
330 *ucr2 |= UCR2_CTS;
331
332 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
333 }
334
335 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
336 {
337 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
338 }
339
340 /* called with port.lock taken and irqs off */
341 static void imx_uart_soft_reset(struct imx_port *sport)
342 {
343 int i = 10;
344 u32 ucr2, ubir, ubmr, uts;
345
346 /*
347 * According to the Reference Manual description of the UART SRST bit:
348 *
349 * "Reset the transmit and receive state machines,
350 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
351 * and UTS[6-3]".
352 *
353 * We don't need to restore the old values from USR1, USR2, URXD and
354 * UTXD. UBRC is read only, so only save/restore the other three
355 * registers.
356 */
357 ubir = imx_uart_readl(sport, UBIR);
358 ubmr = imx_uart_readl(sport, UBMR);
359 uts = imx_uart_readl(sport, IMX21_UTS);
360
361 ucr2 = imx_uart_readl(sport, UCR2);
362 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
363
364 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
365 udelay(1);
366
367 /* Restore the registers */
368 imx_uart_writel(sport, ubir, UBIR);
369 imx_uart_writel(sport, ubmr, UBMR);
370 imx_uart_writel(sport, uts, IMX21_UTS);
371
372 sport->idle_counter = 0;
373 }
374
375 /* called with port.lock taken and irqs off */
376 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
377 {
378 unsigned int uts;
379
380 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
381 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
382 uts &= ~UTS_LOOP;
383 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
384 }
385
386 /* called with port.lock taken and irqs off */
387 static void imx_uart_start_rx(struct uart_port *port)
388 {
389 struct imx_port *sport = to_imx_port(port);
390 unsigned int ucr1, ucr2;
391
392 ucr1 = imx_uart_readl(sport, UCR1);
393 ucr2 = imx_uart_readl(sport, UCR2);
394
395 ucr2 |= UCR2_RXEN;
396
397 if (sport->dma_is_enabled) {
398 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
399 } else {
400 ucr1 |= UCR1_RRDYEN;
401 ucr2 |= UCR2_ATEN;
402 }
403
404 /* Write UCR2 first as it includes RXEN */
405 imx_uart_writel(sport, ucr2, UCR2);
406 imx_uart_writel(sport, ucr1, UCR1);
407 imx_uart_disable_loopback_rs485(sport);
408 }
409
410 /* called with port.lock taken and irqs off */
411 static void imx_uart_stop_tx(struct uart_port *port)
412 {
413 struct imx_port *sport = to_imx_port(port);
414 u32 ucr1, ucr4, usr2;
415
416 if (sport->tx_state == OFF)
417 return;
418
419 /*
420 * We are maybe in the SMP context, so if the DMA TX thread is running
421 * on other cpu, we have to wait for it to finish.
422 */
423 if (sport->dma_is_txing)
424 return;
425
426 ucr1 = imx_uart_readl(sport, UCR1);
427 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
428
429 ucr4 = imx_uart_readl(sport, UCR4);
430 usr2 = imx_uart_readl(sport, USR2);
431 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
432 /* The shifter is still busy, so retry once TC triggers */
433 return;
434 }
435
436 ucr4 &= ~UCR4_TCEN;
437 imx_uart_writel(sport, ucr4, UCR4);
438
439 /* in rs485 mode disable transmitter */
440 if (port->rs485.flags & SER_RS485_ENABLED) {
441 if (sport->tx_state == SEND) {
442 sport->tx_state = WAIT_AFTER_SEND;
443
444 if (port->rs485.delay_rts_after_send > 0) {
445 start_hrtimer_ms(&sport->trigger_stop_tx,
446 port->rs485.delay_rts_after_send);
447 return;
448 }
449
450 /* continue without any delay */
451 }
452
453 if (sport->tx_state == WAIT_AFTER_RTS ||
454 sport->tx_state == WAIT_AFTER_SEND) {
455 u32 ucr2;
456
457 hrtimer_try_to_cancel(&sport->trigger_start_tx);
458
459 ucr2 = imx_uart_readl(sport, UCR2);
460 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
461 imx_uart_rts_active(sport, &ucr2);
462 else
463 imx_uart_rts_inactive(sport, &ucr2);
464 imx_uart_writel(sport, ucr2, UCR2);
465
466 if (!port->rs485_rx_during_tx_gpio)
467 imx_uart_start_rx(port);
468
469 sport->tx_state = OFF;
470 }
471 } else {
472 sport->tx_state = OFF;
473 }
474 }
475
476 /* called with port.lock taken and irqs off */
477 static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
478 {
479 struct imx_port *sport = to_imx_port(port);
480 u32 ucr1, ucr2, ucr4, uts;
481
482 ucr1 = imx_uart_readl(sport, UCR1);
483 ucr2 = imx_uart_readl(sport, UCR2);
484 ucr4 = imx_uart_readl(sport, UCR4);
485
486 if (sport->dma_is_enabled) {
487 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
488 } else {
489 ucr1 &= ~UCR1_RRDYEN;
490 ucr2 &= ~UCR2_ATEN;
491 ucr4 &= ~UCR4_OREN;
492 }
493 imx_uart_writel(sport, ucr1, UCR1);
494 imx_uart_writel(sport, ucr4, UCR4);
495
496 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
497 if (port->rs485.flags & SER_RS485_ENABLED &&
498 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
499 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
500 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
501 uts |= UTS_LOOP;
502 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
503 ucr2 |= UCR2_RXEN;
504 } else {
505 ucr2 &= ~UCR2_RXEN;
506 }
507
508 imx_uart_writel(sport, ucr2, UCR2);
509 }
510
511 /* called with port.lock taken and irqs off */
512 static void imx_uart_stop_rx(struct uart_port *port)
513 {
514 /*
515 * Stop RX and enable loopback in order to make sure RS485 bus
516 * is not blocked. Se comment in imx_uart_probe().
517 */
518 imx_uart_stop_rx_with_loopback_ctrl(port, true);
519 }
520
521 /* called with port.lock taken and irqs off */
522 static void imx_uart_enable_ms(struct uart_port *port)
523 {
524 struct imx_port *sport = to_imx_port(port);
525
526 mod_timer(&sport->timer, jiffies);
527
528 mctrl_gpio_enable_ms(sport->gpios);
529 }
530
531 static void imx_uart_dma_tx(struct imx_port *sport);
532
533 /* called with port.lock taken and irqs off */
534 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
535 {
536 struct tty_port *tport = &sport->port.state->port;
537 unsigned char c;
538
539 if (sport->port.x_char) {
540 /* Send next char */
541 imx_uart_writel(sport, sport->port.x_char, URTX0);
542 sport->port.icount.tx++;
543 sport->port.x_char = 0;
544 return;
545 }
546
547 if (kfifo_is_empty(&tport->xmit_fifo) ||
548 uart_tx_stopped(&sport->port)) {
549 imx_uart_stop_tx(&sport->port);
550 return;
551 }
552
553 if (sport->dma_is_enabled) {
554 u32 ucr1;
555 /*
556 * We've just sent a X-char Ensure the TX DMA is enabled
557 * and the TX IRQ is disabled.
558 **/
559 ucr1 = imx_uart_readl(sport, UCR1);
560 ucr1 &= ~UCR1_TRDYEN;
561 if (sport->dma_is_txing) {
562 ucr1 |= UCR1_TXDMAEN;
563 imx_uart_writel(sport, ucr1, UCR1);
564 } else {
565 imx_uart_writel(sport, ucr1, UCR1);
566 imx_uart_dma_tx(sport);
567 }
568
569 return;
570 }
571
572 while (!(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) &&
573 uart_fifo_get(&sport->port, &c))
574 imx_uart_writel(sport, c, URTX0);
575
576 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
577 uart_write_wakeup(&sport->port);
578
579 if (kfifo_is_empty(&tport->xmit_fifo))
580 imx_uart_stop_tx(&sport->port);
581 }
582
583 static void imx_uart_dma_tx_callback(void *data)
584 {
585 struct imx_port *sport = data;
586 struct tty_port *tport = &sport->port.state->port;
587 struct scatterlist *sgl = &sport->tx_sgl[0];
588 unsigned long flags;
589 u32 ucr1;
590
591 uart_port_lock_irqsave(&sport->port, &flags);
592
593 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
594
595 ucr1 = imx_uart_readl(sport, UCR1);
596 ucr1 &= ~UCR1_TXDMAEN;
597 imx_uart_writel(sport, ucr1, UCR1);
598
599 uart_xmit_advance(&sport->port, sport->tx_bytes);
600
601 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
602
603 sport->dma_is_txing = 0;
604
605 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
606 uart_write_wakeup(&sport->port);
607
608 if (!kfifo_is_empty(&tport->xmit_fifo) &&
609 !uart_tx_stopped(&sport->port))
610 imx_uart_dma_tx(sport);
611 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
612 u32 ucr4 = imx_uart_readl(sport, UCR4);
613 ucr4 |= UCR4_TCEN;
614 imx_uart_writel(sport, ucr4, UCR4);
615 }
616
617 uart_port_unlock_irqrestore(&sport->port, flags);
618 }
619
620 /* called with port.lock taken and irqs off */
621 static void imx_uart_dma_tx(struct imx_port *sport)
622 {
623 struct tty_port *tport = &sport->port.state->port;
624 struct scatterlist *sgl = sport->tx_sgl;
625 struct dma_async_tx_descriptor *desc;
626 struct dma_chan *chan = sport->dma_chan_tx;
627 struct device *dev = sport->port.dev;
628 u32 ucr1, ucr4;
629 int ret;
630
631 if (sport->dma_is_txing)
632 return;
633
634 ucr4 = imx_uart_readl(sport, UCR4);
635 ucr4 &= ~UCR4_TCEN;
636 imx_uart_writel(sport, ucr4, UCR4);
637
638 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl));
639 sport->tx_bytes = kfifo_len(&tport->xmit_fifo);
640 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl,
641 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes);
642
643 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
644 if (ret == 0) {
645 dev_err(dev, "DMA mapping error for TX.\n");
646 return;
647 }
648 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
649 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
650 if (!desc) {
651 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
652 DMA_TO_DEVICE);
653 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
654 return;
655 }
656 desc->callback = imx_uart_dma_tx_callback;
657 desc->callback_param = sport;
658
659 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes);
660
661 ucr1 = imx_uart_readl(sport, UCR1);
662 ucr1 |= UCR1_TXDMAEN;
663 imx_uart_writel(sport, ucr1, UCR1);
664
665 /* fire it */
666 sport->dma_is_txing = 1;
667 dmaengine_submit(desc);
668 dma_async_issue_pending(chan);
669 return;
670 }
671
672 /* called with port.lock taken and irqs off */
673 static void imx_uart_start_tx(struct uart_port *port)
674 {
675 struct imx_port *sport = to_imx_port(port);
676 struct tty_port *tport = &sport->port.state->port;
677 u32 ucr1;
678
679 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo))
680 return;
681
682 /*
683 * We cannot simply do nothing here if sport->tx_state == SEND already
684 * because UCR1_TXMPTYEN might already have been cleared in
685 * imx_uart_stop_tx(), but tx_state is still SEND.
686 */
687
688 if (port->rs485.flags & SER_RS485_ENABLED) {
689 if (sport->tx_state == OFF) {
690 u32 ucr2 = imx_uart_readl(sport, UCR2);
691 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
692 imx_uart_rts_active(sport, &ucr2);
693 else
694 imx_uart_rts_inactive(sport, &ucr2);
695 imx_uart_writel(sport, ucr2, UCR2);
696
697 /*
698 * Since we are about to transmit we can not stop RX
699 * with loopback enabled because that will make our
700 * transmitted data being just looped to RX.
701 */
702 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
703 !port->rs485_rx_during_tx_gpio)
704 imx_uart_stop_rx_with_loopback_ctrl(port, false);
705
706 sport->tx_state = WAIT_AFTER_RTS;
707
708 if (port->rs485.delay_rts_before_send > 0) {
709 start_hrtimer_ms(&sport->trigger_start_tx,
710 port->rs485.delay_rts_before_send);
711 return;
712 }
713
714 /* continue without any delay */
715 }
716
717 if (sport->tx_state == WAIT_AFTER_SEND
718 || sport->tx_state == WAIT_AFTER_RTS) {
719
720 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
721
722 /*
723 * Enable transmitter and shifter empty irq only if DMA
724 * is off. In the DMA case this is done in the
725 * tx-callback.
726 */
727 if (!sport->dma_is_enabled) {
728 u32 ucr4 = imx_uart_readl(sport, UCR4);
729 ucr4 |= UCR4_TCEN;
730 imx_uart_writel(sport, ucr4, UCR4);
731 }
732
733 sport->tx_state = SEND;
734 }
735 } else {
736 sport->tx_state = SEND;
737 }
738
739 if (!sport->dma_is_enabled) {
740 ucr1 = imx_uart_readl(sport, UCR1);
741 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
742 }
743
744 if (sport->dma_is_enabled) {
745 if (sport->port.x_char) {
746 /* We have X-char to send, so enable TX IRQ and
747 * disable TX DMA to let TX interrupt to send X-char */
748 ucr1 = imx_uart_readl(sport, UCR1);
749 ucr1 &= ~UCR1_TXDMAEN;
750 ucr1 |= UCR1_TRDYEN;
751 imx_uart_writel(sport, ucr1, UCR1);
752 return;
753 }
754
755 if (!kfifo_is_empty(&tport->xmit_fifo) &&
756 !uart_tx_stopped(port))
757 imx_uart_dma_tx(sport);
758 return;
759 }
760 }
761
762 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
763 {
764 struct imx_port *sport = dev_id;
765 u32 usr1;
766
767 imx_uart_writel(sport, USR1_RTSD, USR1);
768 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
769 /*
770 * Update sport->old_status here, so any follow-up calls to
771 * imx_uart_mctrl_check() will be able to recognize that RTS
772 * state changed since last imx_uart_mctrl_check() call.
773 *
774 * In case RTS has been detected as asserted here and later on
775 * deasserted by the time imx_uart_mctrl_check() was called,
776 * imx_uart_mctrl_check() can detect the RTS state change and
777 * trigger uart_handle_cts_change() to unblock the port for
778 * further TX transfers.
779 */
780 if (usr1 & USR1_RTSS)
781 sport->old_status |= TIOCM_CTS;
782 else
783 sport->old_status &= ~TIOCM_CTS;
784 uart_handle_cts_change(&sport->port, usr1);
785 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
786
787 return IRQ_HANDLED;
788 }
789
790 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
791 {
792 struct imx_port *sport = dev_id;
793 irqreturn_t ret;
794
795 uart_port_lock(&sport->port);
796
797 ret = __imx_uart_rtsint(irq, dev_id);
798
799 uart_port_unlock(&sport->port);
800
801 return ret;
802 }
803
804 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
805 {
806 struct imx_port *sport = dev_id;
807
808 uart_port_lock(&sport->port);
809 imx_uart_transmit_buffer(sport);
810 uart_port_unlock(&sport->port);
811 return IRQ_HANDLED;
812 }
813
814 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
815 * This is to be called from Rx ISRs only when some bytes were actually
816 * received.
817 *
818 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
819 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
820 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
821 * that is terminated by any activity on RxD line, or could be stopped by
822 * issuing soft reset to the UART (just stop/start of RX does not help). Note
823 * that what we do here is sending isolated start bit about 2.4 times shorter
824 * than it is to be on UART configured baud rate.
825 *
826 * Called with port.lock taken and irqs off.
827 */
828 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
829 {
830 /* To detect hardware 0xff flood we monitor RxD line between RX
831 * interrupts to isolate "receiving" of char(s) with no activity
832 * on RxD line, that'd never happen on actual data transfers.
833 *
834 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
835 * race here if we clear USR2_WAKE when receiving of a char is in
836 * progress, so we might get RX interrupt later with USR2_WAKE bit
837 * cleared. Note though that as we don't try to clear USR2_WAKE when we
838 * detected no activity, this race may hide actual activity only once.
839 *
840 * Yet another case where receive interrupt may occur without RxD
841 * activity is expiration of aging timer, so we consider this as well.
842 *
843 * We use 'idle_counter' to ensure that we got at least so many RX
844 * interrupts without any detected activity on RxD line. 2 cases
845 * described plus 1 to be on the safe side gives us a margin of 3,
846 * below. In practice I was not able to produce a false positive to
847 * induce soft reset at regular data transfers even using 1 as the
848 * margin, so 3 is actually very strong.
849 *
850 * We count interrupts, not chars in 'idle-counter' for simplicity.
851 */
852
853 if (usr2 & USR2_WAKE) {
854 imx_uart_writel(sport, USR2_WAKE, USR2);
855 sport->idle_counter = 0;
856 } else if (++sport->idle_counter > 3) {
857 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
858 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
859 }
860 }
861
862 /* called with port.lock taken and irqs off */
863 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
864 {
865 struct imx_port *sport = dev_id;
866 struct tty_port *port = &sport->port.state->port;
867 u32 usr2, rx;
868
869 /* If we received something, check for 0xff flood */
870 usr2 = imx_uart_readl(sport, USR2);
871 if (usr2 & USR2_RDR)
872 imx_uart_check_flood(sport, usr2);
873
874 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
875 unsigned int flg = TTY_NORMAL;
876 sport->port.icount.rx++;
877
878 if (unlikely(rx & URXD_ERR)) {
879 if (rx & URXD_BRK) {
880 sport->port.icount.brk++;
881 if (uart_handle_break(&sport->port))
882 continue;
883 }
884 else if (rx & URXD_PRERR)
885 sport->port.icount.parity++;
886 else if (rx & URXD_FRMERR)
887 sport->port.icount.frame++;
888 if (rx & URXD_OVRRUN)
889 sport->port.icount.overrun++;
890
891 if (rx & sport->port.ignore_status_mask)
892 continue;
893
894 rx &= (sport->port.read_status_mask | 0xFF);
895
896 if (rx & URXD_BRK)
897 flg = TTY_BREAK;
898 else if (rx & URXD_PRERR)
899 flg = TTY_PARITY;
900 else if (rx & URXD_FRMERR)
901 flg = TTY_FRAME;
902 if (rx & URXD_OVRRUN)
903 flg = TTY_OVERRUN;
904
905 sport->port.sysrq = 0;
906 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
907 continue;
908 }
909
910 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
911 continue;
912
913 if (tty_insert_flip_char(port, rx, flg) == 0)
914 sport->port.icount.buf_overrun++;
915 }
916
917 tty_flip_buffer_push(port);
918
919 return IRQ_HANDLED;
920 }
921
922 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
923 {
924 struct imx_port *sport = dev_id;
925 irqreturn_t ret;
926
927 uart_port_lock(&sport->port);
928
929 ret = __imx_uart_rxint(irq, dev_id);
930
931 uart_port_unlock(&sport->port);
932
933 return ret;
934 }
935
936 static void imx_uart_clear_rx_errors(struct imx_port *sport);
937
938 /*
939 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
940 */
941 /* called with port.lock taken and irqs off */
942 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
943 {
944 unsigned int tmp = TIOCM_DSR;
945 unsigned usr1 = imx_uart_readl(sport, USR1);
946 unsigned usr2 = imx_uart_readl(sport, USR2);
947
948 if (usr1 & USR1_RTSS)
949 tmp |= TIOCM_CTS;
950
951 /* in DCE mode DCDIN is always 0 */
952 if (!(usr2 & USR2_DCDIN))
953 tmp |= TIOCM_CAR;
954
955 if (sport->dte_mode)
956 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
957 tmp |= TIOCM_RI;
958
959 return tmp;
960 }
961
962 /*
963 * Handle any change of modem status signal since we were last called.
964 *
965 * Called with port.lock taken and irqs off.
966 */
967 static void imx_uart_mctrl_check(struct imx_port *sport)
968 {
969 unsigned int status, changed;
970
971 status = imx_uart_get_hwmctrl(sport);
972 changed = status ^ sport->old_status;
973
974 if (changed == 0)
975 return;
976
977 sport->old_status = status;
978
979 if (changed & TIOCM_RI && status & TIOCM_RI)
980 sport->port.icount.rng++;
981 if (changed & TIOCM_DSR)
982 sport->port.icount.dsr++;
983 if (changed & TIOCM_CAR)
984 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
985 if (changed & TIOCM_CTS)
986 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
987
988 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
989 }
990
991 static irqreturn_t imx_uart_int(int irq, void *dev_id)
992 {
993 struct imx_port *sport = dev_id;
994 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
995 irqreturn_t ret = IRQ_NONE;
996
997 uart_port_lock(&sport->port);
998
999 usr1 = imx_uart_readl(sport, USR1);
1000 usr2 = imx_uart_readl(sport, USR2);
1001 ucr1 = imx_uart_readl(sport, UCR1);
1002 ucr2 = imx_uart_readl(sport, UCR2);
1003 ucr3 = imx_uart_readl(sport, UCR3);
1004 ucr4 = imx_uart_readl(sport, UCR4);
1005
1006 /*
1007 * Even if a condition is true that can trigger an irq only handle it if
1008 * the respective irq source is enabled. This prevents some undesired
1009 * actions, for example if a character that sits in the RX FIFO and that
1010 * should be fetched via DMA is tried to be fetched using PIO. Or the
1011 * receiver is currently off and so reading from URXD0 results in an
1012 * exception. So just mask the (raw) status bits for disabled irqs.
1013 */
1014 if ((ucr1 & UCR1_RRDYEN) == 0)
1015 usr1 &= ~USR1_RRDY;
1016 if ((ucr2 & UCR2_ATEN) == 0)
1017 usr1 &= ~USR1_AGTIM;
1018 if ((ucr1 & UCR1_TRDYEN) == 0)
1019 usr1 &= ~USR1_TRDY;
1020 if ((ucr4 & UCR4_TCEN) == 0)
1021 usr2 &= ~USR2_TXDC;
1022 if ((ucr3 & UCR3_DTRDEN) == 0)
1023 usr1 &= ~USR1_DTRD;
1024 if ((ucr1 & UCR1_RTSDEN) == 0)
1025 usr1 &= ~USR1_RTSD;
1026 if ((ucr3 & UCR3_AWAKEN) == 0)
1027 usr1 &= ~USR1_AWAKE;
1028 if ((ucr4 & UCR4_OREN) == 0)
1029 usr2 &= ~USR2_ORE;
1030
1031 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1032 imx_uart_writel(sport, USR1_AGTIM, USR1);
1033
1034 __imx_uart_rxint(irq, dev_id);
1035 ret = IRQ_HANDLED;
1036 }
1037
1038 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1039 imx_uart_transmit_buffer(sport);
1040 ret = IRQ_HANDLED;
1041 }
1042
1043 if (usr1 & USR1_DTRD) {
1044 imx_uart_writel(sport, USR1_DTRD, USR1);
1045
1046 imx_uart_mctrl_check(sport);
1047
1048 ret = IRQ_HANDLED;
1049 }
1050
1051 if (usr1 & USR1_RTSD) {
1052 __imx_uart_rtsint(irq, dev_id);
1053 ret = IRQ_HANDLED;
1054 }
1055
1056 if (usr1 & USR1_AWAKE) {
1057 imx_uart_writel(sport, USR1_AWAKE, USR1);
1058 ret = IRQ_HANDLED;
1059 }
1060
1061 if (usr2 & USR2_ORE) {
1062 sport->port.icount.overrun++;
1063 imx_uart_writel(sport, USR2_ORE, USR2);
1064 ret = IRQ_HANDLED;
1065 }
1066
1067 uart_port_unlock(&sport->port);
1068
1069 return ret;
1070 }
1071
1072 /*
1073 * Return TIOCSER_TEMT when transmitter is not busy.
1074 */
1075 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1076 {
1077 struct imx_port *sport = to_imx_port(port);
1078 unsigned int ret;
1079
1080 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1081
1082 /* If the TX DMA is working, return 0. */
1083 if (sport->dma_is_txing)
1084 ret = 0;
1085
1086 return ret;
1087 }
1088
1089 /* called with port.lock taken and irqs off */
1090 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1091 {
1092 struct imx_port *sport = to_imx_port(port);
1093 unsigned int ret = imx_uart_get_hwmctrl(sport);
1094
1095 mctrl_gpio_get(sport->gpios, &ret);
1096
1097 return ret;
1098 }
1099
1100 /* called with port.lock taken and irqs off */
1101 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1102 {
1103 struct imx_port *sport = to_imx_port(port);
1104 u32 ucr3, uts;
1105
1106 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1107 u32 ucr2;
1108
1109 /*
1110 * Turn off autoRTS if RTS is lowered and restore autoRTS
1111 * setting if RTS is raised.
1112 */
1113 ucr2 = imx_uart_readl(sport, UCR2);
1114 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1115 if (mctrl & TIOCM_RTS) {
1116 ucr2 |= UCR2_CTS;
1117 /*
1118 * UCR2_IRTS is unset if and only if the port is
1119 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1120 * to get the state to restore to.
1121 */
1122 if (!(ucr2 & UCR2_IRTS))
1123 ucr2 |= UCR2_CTSC;
1124 }
1125 imx_uart_writel(sport, ucr2, UCR2);
1126 }
1127
1128 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1129 if (!(mctrl & TIOCM_DTR))
1130 ucr3 |= UCR3_DSR;
1131 imx_uart_writel(sport, ucr3, UCR3);
1132
1133 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1134 if (mctrl & TIOCM_LOOP)
1135 uts |= UTS_LOOP;
1136 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1137
1138 mctrl_gpio_set(sport->gpios, mctrl);
1139 }
1140
1141 /*
1142 * Interrupts always disabled.
1143 */
1144 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1145 {
1146 struct imx_port *sport = to_imx_port(port);
1147 unsigned long flags;
1148 u32 ucr1;
1149
1150 uart_port_lock_irqsave(&sport->port, &flags);
1151
1152 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1153
1154 if (break_state != 0)
1155 ucr1 |= UCR1_SNDBRK;
1156
1157 imx_uart_writel(sport, ucr1, UCR1);
1158
1159 uart_port_unlock_irqrestore(&sport->port, flags);
1160 }
1161
1162 /*
1163 * This is our per-port timeout handler, for checking the
1164 * modem status signals.
1165 */
1166 static void imx_uart_timeout(struct timer_list *t)
1167 {
1168 struct imx_port *sport = from_timer(sport, t, timer);
1169 unsigned long flags;
1170
1171 if (sport->port.state) {
1172 uart_port_lock_irqsave(&sport->port, &flags);
1173 imx_uart_mctrl_check(sport);
1174 uart_port_unlock_irqrestore(&sport->port, flags);
1175
1176 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1177 }
1178 }
1179
1180 /*
1181 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1182 * [1] the RX DMA buffer is full.
1183 * [2] the aging timer expires
1184 *
1185 * Condition [2] is triggered when a character has been sitting in the FIFO
1186 * for at least 8 byte durations.
1187 */
1188 static void imx_uart_dma_rx_callback(void *data)
1189 {
1190 struct imx_port *sport = data;
1191 struct dma_chan *chan = sport->dma_chan_rx;
1192 struct scatterlist *sgl = &sport->rx_sgl;
1193 struct tty_port *port = &sport->port.state->port;
1194 struct dma_tx_state state;
1195 struct circ_buf *rx_ring = &sport->rx_ring;
1196 enum dma_status status;
1197 unsigned int w_bytes = 0;
1198 unsigned int r_bytes;
1199 unsigned int bd_size;
1200
1201 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1202
1203 if (status == DMA_ERROR) {
1204 uart_port_lock(&sport->port);
1205 imx_uart_clear_rx_errors(sport);
1206 uart_port_unlock(&sport->port);
1207 return;
1208 }
1209
1210 /*
1211 * The state-residue variable represents the empty space
1212 * relative to the entire buffer. Taking this in consideration
1213 * the head is always calculated base on the buffer total
1214 * length - DMA transaction residue. The UART script from the
1215 * SDMA firmware will jump to the next buffer descriptor,
1216 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1217 * Taking this in consideration the tail is always at the
1218 * beginning of the buffer descriptor that contains the head.
1219 */
1220
1221 /* Calculate the head */
1222 rx_ring->head = sg_dma_len(sgl) - state.residue;
1223
1224 /* Calculate the tail. */
1225 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1226 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1227
1228 if (rx_ring->head <= sg_dma_len(sgl) &&
1229 rx_ring->head > rx_ring->tail) {
1230
1231 /* Move data from tail to head */
1232 r_bytes = rx_ring->head - rx_ring->tail;
1233
1234 /* If we received something, check for 0xff flood */
1235 uart_port_lock(&sport->port);
1236 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1237 uart_port_unlock(&sport->port);
1238
1239 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1240
1241 /* CPU claims ownership of RX DMA buffer */
1242 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1243 DMA_FROM_DEVICE);
1244
1245 w_bytes = tty_insert_flip_string(port,
1246 sport->rx_buf + rx_ring->tail, r_bytes);
1247
1248 /* UART retrieves ownership of RX DMA buffer */
1249 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1250 DMA_FROM_DEVICE);
1251
1252 if (w_bytes != r_bytes)
1253 sport->port.icount.buf_overrun++;
1254
1255 sport->port.icount.rx += w_bytes;
1256 }
1257 } else {
1258 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1259 WARN_ON(rx_ring->head <= rx_ring->tail);
1260 }
1261
1262 if (w_bytes) {
1263 tty_flip_buffer_push(port);
1264 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1265 }
1266 }
1267
1268 static int imx_uart_start_rx_dma(struct imx_port *sport)
1269 {
1270 struct scatterlist *sgl = &sport->rx_sgl;
1271 struct dma_chan *chan = sport->dma_chan_rx;
1272 struct device *dev = sport->port.dev;
1273 struct dma_async_tx_descriptor *desc;
1274 int ret;
1275
1276 sport->rx_ring.head = 0;
1277 sport->rx_ring.tail = 0;
1278
1279 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1280 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1281 if (ret == 0) {
1282 dev_err(dev, "DMA mapping error for RX.\n");
1283 return -EINVAL;
1284 }
1285
1286 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1287 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1288 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1289
1290 if (!desc) {
1291 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1292 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1293 return -EINVAL;
1294 }
1295 desc->callback = imx_uart_dma_rx_callback;
1296 desc->callback_param = sport;
1297
1298 dev_dbg(dev, "RX: prepare for the DMA.\n");
1299 sport->dma_is_rxing = 1;
1300 sport->rx_cookie = dmaengine_submit(desc);
1301 dma_async_issue_pending(chan);
1302 return 0;
1303 }
1304
1305 /* called with port.lock taken and irqs off */
1306 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1307 {
1308 struct tty_port *port = &sport->port.state->port;
1309 u32 usr1, usr2;
1310
1311 usr1 = imx_uart_readl(sport, USR1);
1312 usr2 = imx_uart_readl(sport, USR2);
1313
1314 if (usr2 & USR2_BRCD) {
1315 sport->port.icount.brk++;
1316 imx_uart_writel(sport, USR2_BRCD, USR2);
1317 uart_handle_break(&sport->port);
1318 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1319 sport->port.icount.buf_overrun++;
1320 tty_flip_buffer_push(port);
1321 } else {
1322 if (usr1 & USR1_FRAMERR) {
1323 sport->port.icount.frame++;
1324 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1325 } else if (usr1 & USR1_PARITYERR) {
1326 sport->port.icount.parity++;
1327 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1328 }
1329 }
1330
1331 if (usr2 & USR2_ORE) {
1332 sport->port.icount.overrun++;
1333 imx_uart_writel(sport, USR2_ORE, USR2);
1334 }
1335
1336 sport->idle_counter = 0;
1337
1338 }
1339
1340 #define TXTL_DEFAULT 8
1341 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1342 #define TXTL_DMA 8 /* DMA burst setting */
1343 #define RXTL_DMA 9 /* DMA burst setting */
1344
1345 static void imx_uart_setup_ufcr(struct imx_port *sport,
1346 unsigned char txwl, unsigned char rxwl)
1347 {
1348 unsigned int val;
1349
1350 /* set receiver / transmitter trigger level */
1351 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1352 val |= txwl << UFCR_TXTL_SHF | rxwl;
1353 imx_uart_writel(sport, val, UFCR);
1354 }
1355
1356 static void imx_uart_dma_exit(struct imx_port *sport)
1357 {
1358 if (sport->dma_chan_rx) {
1359 dmaengine_terminate_sync(sport->dma_chan_rx);
1360 dma_release_channel(sport->dma_chan_rx);
1361 sport->dma_chan_rx = NULL;
1362 sport->rx_cookie = -EINVAL;
1363 kfree(sport->rx_buf);
1364 sport->rx_buf = NULL;
1365 }
1366
1367 if (sport->dma_chan_tx) {
1368 dmaengine_terminate_sync(sport->dma_chan_tx);
1369 dma_release_channel(sport->dma_chan_tx);
1370 sport->dma_chan_tx = NULL;
1371 }
1372 }
1373
1374 static int imx_uart_dma_init(struct imx_port *sport)
1375 {
1376 struct dma_slave_config slave_config = {};
1377 struct device *dev = sport->port.dev;
1378 struct dma_chan *chan;
1379 int ret;
1380
1381 /* Prepare for RX : */
1382 chan = dma_request_chan(dev, "rx");
1383 if (IS_ERR(chan)) {
1384 dev_dbg(dev, "cannot get the DMA channel.\n");
1385 sport->dma_chan_rx = NULL;
1386 ret = PTR_ERR(chan);
1387 goto err;
1388 }
1389 sport->dma_chan_rx = chan;
1390
1391 slave_config.direction = DMA_DEV_TO_MEM;
1392 slave_config.src_addr = sport->port.mapbase + URXD0;
1393 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1394 /* one byte less than the watermark level to enable the aging timer */
1395 slave_config.src_maxburst = RXTL_DMA - 1;
1396 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1397 if (ret) {
1398 dev_err(dev, "error in RX dma configuration.\n");
1399 goto err;
1400 }
1401
1402 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1403 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1404 if (!sport->rx_buf) {
1405 ret = -ENOMEM;
1406 goto err;
1407 }
1408 sport->rx_ring.buf = sport->rx_buf;
1409
1410 /* Prepare for TX : */
1411 chan = dma_request_chan(dev, "tx");
1412 if (IS_ERR(chan)) {
1413 dev_err(dev, "cannot get the TX DMA channel!\n");
1414 sport->dma_chan_tx = NULL;
1415 ret = PTR_ERR(chan);
1416 goto err;
1417 }
1418 sport->dma_chan_tx = chan;
1419
1420 slave_config.direction = DMA_MEM_TO_DEV;
1421 slave_config.dst_addr = sport->port.mapbase + URTX0;
1422 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1423 slave_config.dst_maxburst = TXTL_DMA;
1424 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1425 if (ret) {
1426 dev_err(dev, "error in TX dma configuration.");
1427 goto err;
1428 }
1429
1430 return 0;
1431 err:
1432 imx_uart_dma_exit(sport);
1433 return ret;
1434 }
1435
1436 /* called with port.lock taken and irqs off */
1437 static void imx_uart_enable_dma(struct imx_port *sport)
1438 {
1439 u32 ucr1;
1440
1441 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1442
1443 /* set UCR1 */
1444 ucr1 = imx_uart_readl(sport, UCR1);
1445 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1446 imx_uart_writel(sport, ucr1, UCR1);
1447
1448 sport->dma_is_enabled = 1;
1449 }
1450
1451 static void imx_uart_disable_dma(struct imx_port *sport)
1452 {
1453 u32 ucr1;
1454
1455 /* clear UCR1 */
1456 ucr1 = imx_uart_readl(sport, UCR1);
1457 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1458 imx_uart_writel(sport, ucr1, UCR1);
1459
1460 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1461
1462 sport->dma_is_enabled = 0;
1463 }
1464
1465 /* half the RX buffer size */
1466 #define CTSTL 16
1467
1468 static int imx_uart_startup(struct uart_port *port)
1469 {
1470 struct imx_port *sport = to_imx_port(port);
1471 int retval;
1472 unsigned long flags;
1473 int dma_is_inited = 0;
1474 u32 ucr1, ucr2, ucr3, ucr4;
1475
1476 retval = clk_prepare_enable(sport->clk_per);
1477 if (retval)
1478 return retval;
1479 retval = clk_prepare_enable(sport->clk_ipg);
1480 if (retval) {
1481 clk_disable_unprepare(sport->clk_per);
1482 return retval;
1483 }
1484
1485 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1486
1487 /* disable the DREN bit (Data Ready interrupt enable) before
1488 * requesting IRQs
1489 */
1490 ucr4 = imx_uart_readl(sport, UCR4);
1491
1492 /* set the trigger level for CTS */
1493 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1494 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1495
1496 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1497
1498 /* Can we enable the DMA support? */
1499 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
1500 lockdep_set_subclass(&port->lock, 1);
1501 dma_is_inited = 1;
1502 }
1503
1504 uart_port_lock_irqsave(&sport->port, &flags);
1505
1506 /* Reset fifo's and state machines */
1507 imx_uart_soft_reset(sport);
1508
1509 /*
1510 * Finally, clear and enable interrupts
1511 */
1512 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1513 imx_uart_writel(sport, USR2_ORE, USR2);
1514
1515 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1516 ucr1 |= UCR1_UARTEN;
1517 if (sport->have_rtscts)
1518 ucr1 |= UCR1_RTSDEN;
1519
1520 imx_uart_writel(sport, ucr1, UCR1);
1521
1522 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1523 if (!dma_is_inited)
1524 ucr4 |= UCR4_OREN;
1525 if (sport->inverted_rx)
1526 ucr4 |= UCR4_INVR;
1527 imx_uart_writel(sport, ucr4, UCR4);
1528
1529 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1530 /*
1531 * configure tx polarity before enabling tx
1532 */
1533 if (sport->inverted_tx)
1534 ucr3 |= UCR3_INVT;
1535
1536 if (!imx_uart_is_imx1(sport)) {
1537 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1538
1539 if (sport->dte_mode)
1540 /* disable broken interrupts */
1541 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1542 }
1543 imx_uart_writel(sport, ucr3, UCR3);
1544
1545 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1546 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1547 if (!sport->have_rtscts)
1548 ucr2 |= UCR2_IRTS;
1549 /*
1550 * make sure the edge sensitive RTS-irq is disabled,
1551 * we're using RTSD instead.
1552 */
1553 if (!imx_uart_is_imx1(sport))
1554 ucr2 &= ~UCR2_RTSEN;
1555 imx_uart_writel(sport, ucr2, UCR2);
1556
1557 /*
1558 * Enable modem status interrupts
1559 */
1560 imx_uart_enable_ms(&sport->port);
1561
1562 if (dma_is_inited) {
1563 imx_uart_enable_dma(sport);
1564 imx_uart_start_rx_dma(sport);
1565 } else {
1566 ucr1 = imx_uart_readl(sport, UCR1);
1567 ucr1 |= UCR1_RRDYEN;
1568 imx_uart_writel(sport, ucr1, UCR1);
1569
1570 ucr2 = imx_uart_readl(sport, UCR2);
1571 ucr2 |= UCR2_ATEN;
1572 imx_uart_writel(sport, ucr2, UCR2);
1573 }
1574
1575 imx_uart_disable_loopback_rs485(sport);
1576
1577 uart_port_unlock_irqrestore(&sport->port, flags);
1578
1579 return 0;
1580 }
1581
1582 static void imx_uart_shutdown(struct uart_port *port)
1583 {
1584 struct imx_port *sport = to_imx_port(port);
1585 unsigned long flags;
1586 u32 ucr1, ucr2, ucr4, uts;
1587 int loops;
1588
1589 if (sport->dma_is_enabled) {
1590 dmaengine_terminate_sync(sport->dma_chan_tx);
1591 if (sport->dma_is_txing) {
1592 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1593 sport->dma_tx_nents, DMA_TO_DEVICE);
1594 sport->dma_is_txing = 0;
1595 }
1596 dmaengine_terminate_sync(sport->dma_chan_rx);
1597 if (sport->dma_is_rxing) {
1598 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1599 1, DMA_FROM_DEVICE);
1600 sport->dma_is_rxing = 0;
1601 }
1602
1603 uart_port_lock_irqsave(&sport->port, &flags);
1604 imx_uart_stop_tx(port);
1605 imx_uart_stop_rx(port);
1606 imx_uart_disable_dma(sport);
1607 uart_port_unlock_irqrestore(&sport->port, flags);
1608 imx_uart_dma_exit(sport);
1609 }
1610
1611 mctrl_gpio_disable_ms(sport->gpios);
1612
1613 uart_port_lock_irqsave(&sport->port, &flags);
1614 ucr2 = imx_uart_readl(sport, UCR2);
1615 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1616 imx_uart_writel(sport, ucr2, UCR2);
1617 uart_port_unlock_irqrestore(&sport->port, flags);
1618
1619 /*
1620 * Stop our timer.
1621 */
1622 del_timer_sync(&sport->timer);
1623
1624 /*
1625 * Disable all interrupts, port and break condition.
1626 */
1627
1628 uart_port_lock_irqsave(&sport->port, &flags);
1629
1630 ucr1 = imx_uart_readl(sport, UCR1);
1631 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1632 UCR1_ATDMAEN | UCR1_SNDBRK);
1633 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1634 if (port->rs485.flags & SER_RS485_ENABLED &&
1635 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1636 sport->have_rtscts && !sport->have_rtsgpio) {
1637 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1638 uts |= UTS_LOOP;
1639 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1640 ucr1 |= UCR1_UARTEN;
1641 } else {
1642 ucr1 &= ~UCR1_UARTEN;
1643 }
1644 imx_uart_writel(sport, ucr1, UCR1);
1645
1646 ucr4 = imx_uart_readl(sport, UCR4);
1647 ucr4 &= ~UCR4_TCEN;
1648 imx_uart_writel(sport, ucr4, UCR4);
1649
1650 /*
1651 * We have to ensure the tx state machine ends up in OFF. This
1652 * is especially important for rs485 where we must not leave
1653 * the RTS signal high, blocking the bus indefinitely.
1654 *
1655 * All interrupts are now disabled, so imx_uart_stop_tx() will
1656 * no longer be called from imx_uart_transmit_buffer(). It may
1657 * still be called via the hrtimers, and if those are in play,
1658 * we have to honour the delays.
1659 */
1660 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND)
1661 imx_uart_stop_tx(port);
1662
1663 /*
1664 * In many cases (rs232 mode, or if tx_state was
1665 * WAIT_AFTER_RTS, or if tx_state was SEND and there is no
1666 * delay_rts_after_send), this will have moved directly to
1667 * OFF. In rs485 mode, tx_state might already have been
1668 * WAIT_AFTER_SEND and the hrtimer thus already started, or
1669 * the above imx_uart_stop_tx() call could have started it. In
1670 * those cases, we have to wait for the hrtimer to fire and
1671 * complete the transition to OFF.
1672 */
1673 loops = port->rs485.flags & SER_RS485_ENABLED ?
1674 port->rs485.delay_rts_after_send : 0;
1675 while (sport->tx_state != OFF && loops--) {
1676 uart_port_unlock_irqrestore(&sport->port, flags);
1677 msleep(1);
1678 uart_port_lock_irqsave(&sport->port, &flags);
1679 }
1680
1681 if (sport->tx_state != OFF) {
1682 dev_warn(sport->port.dev, "unexpected tx_state %d\n",
1683 sport->tx_state);
1684 /*
1685 * This machine may be busted, but ensure the RTS
1686 * signal is inactive in order not to block other
1687 * devices.
1688 */
1689 if (port->rs485.flags & SER_RS485_ENABLED) {
1690 ucr2 = imx_uart_readl(sport, UCR2);
1691 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1692 imx_uart_rts_active(sport, &ucr2);
1693 else
1694 imx_uart_rts_inactive(sport, &ucr2);
1695 imx_uart_writel(sport, ucr2, UCR2);
1696 }
1697 sport->tx_state = OFF;
1698 }
1699
1700 uart_port_unlock_irqrestore(&sport->port, flags);
1701
1702 clk_disable_unprepare(sport->clk_per);
1703 clk_disable_unprepare(sport->clk_ipg);
1704 }
1705
1706 /* called with port.lock taken and irqs off */
1707 static void imx_uart_flush_buffer(struct uart_port *port)
1708 {
1709 struct imx_port *sport = to_imx_port(port);
1710 struct scatterlist *sgl = &sport->tx_sgl[0];
1711
1712 if (!sport->dma_chan_tx)
1713 return;
1714
1715 sport->tx_bytes = 0;
1716 dmaengine_terminate_all(sport->dma_chan_tx);
1717 if (sport->dma_is_txing) {
1718 u32 ucr1;
1719
1720 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1721 DMA_TO_DEVICE);
1722 ucr1 = imx_uart_readl(sport, UCR1);
1723 ucr1 &= ~UCR1_TXDMAEN;
1724 imx_uart_writel(sport, ucr1, UCR1);
1725 sport->dma_is_txing = 0;
1726 }
1727
1728 imx_uart_soft_reset(sport);
1729
1730 }
1731
1732 static void
1733 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1734 const struct ktermios *old)
1735 {
1736 struct imx_port *sport = to_imx_port(port);
1737 unsigned long flags;
1738 u32 ucr2, old_ucr2, ufcr;
1739 unsigned int baud, quot;
1740 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1741 unsigned long div;
1742 unsigned long num, denom, old_ubir, old_ubmr;
1743 uint64_t tdiv64;
1744
1745 /*
1746 * We only support CS7 and CS8.
1747 */
1748 while ((termios->c_cflag & CSIZE) != CS7 &&
1749 (termios->c_cflag & CSIZE) != CS8) {
1750 termios->c_cflag &= ~CSIZE;
1751 termios->c_cflag |= old_csize;
1752 old_csize = CS8;
1753 }
1754
1755 del_timer_sync(&sport->timer);
1756
1757 /*
1758 * Ask the core to calculate the divisor for us.
1759 */
1760 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1761 quot = uart_get_divisor(port, baud);
1762
1763 uart_port_lock_irqsave(&sport->port, &flags);
1764
1765 /*
1766 * Read current UCR2 and save it for future use, then clear all the bits
1767 * except those we will or may need to preserve.
1768 */
1769 old_ucr2 = imx_uart_readl(sport, UCR2);
1770 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1771
1772 ucr2 |= UCR2_SRST | UCR2_IRTS;
1773 if ((termios->c_cflag & CSIZE) == CS8)
1774 ucr2 |= UCR2_WS;
1775
1776 if (!sport->have_rtscts)
1777 termios->c_cflag &= ~CRTSCTS;
1778
1779 if (port->rs485.flags & SER_RS485_ENABLED) {
1780 /*
1781 * RTS is mandatory for rs485 operation, so keep
1782 * it under manual control and keep transmitter
1783 * disabled.
1784 */
1785 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1786 imx_uart_rts_active(sport, &ucr2);
1787 else
1788 imx_uart_rts_inactive(sport, &ucr2);
1789
1790 } else if (termios->c_cflag & CRTSCTS) {
1791 /*
1792 * Only let receiver control RTS output if we were not requested
1793 * to have RTS inactive (which then should take precedence).
1794 */
1795 if (ucr2 & UCR2_CTS)
1796 ucr2 |= UCR2_CTSC;
1797 }
1798
1799 if (termios->c_cflag & CRTSCTS)
1800 ucr2 &= ~UCR2_IRTS;
1801 if (termios->c_cflag & CSTOPB)
1802 ucr2 |= UCR2_STPB;
1803 if (termios->c_cflag & PARENB) {
1804 ucr2 |= UCR2_PREN;
1805 if (termios->c_cflag & PARODD)
1806 ucr2 |= UCR2_PROE;
1807 }
1808
1809 sport->port.read_status_mask = 0;
1810 if (termios->c_iflag & INPCK)
1811 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1812 if (termios->c_iflag & (BRKINT | PARMRK))
1813 sport->port.read_status_mask |= URXD_BRK;
1814
1815 /*
1816 * Characters to ignore
1817 */
1818 sport->port.ignore_status_mask = 0;
1819 if (termios->c_iflag & IGNPAR)
1820 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1821 if (termios->c_iflag & IGNBRK) {
1822 sport->port.ignore_status_mask |= URXD_BRK;
1823 /*
1824 * If we're ignoring parity and break indicators,
1825 * ignore overruns too (for real raw support).
1826 */
1827 if (termios->c_iflag & IGNPAR)
1828 sport->port.ignore_status_mask |= URXD_OVRRUN;
1829 }
1830
1831 if ((termios->c_cflag & CREAD) == 0)
1832 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1833
1834 /*
1835 * Update the per-port timeout.
1836 */
1837 uart_update_timeout(port, termios->c_cflag, baud);
1838
1839 /* custom-baudrate handling */
1840 div = sport->port.uartclk / (baud * 16);
1841 if (baud == 38400 && quot != div)
1842 baud = sport->port.uartclk / (quot * 16);
1843
1844 div = sport->port.uartclk / (baud * 16);
1845 if (div > 7)
1846 div = 7;
1847 if (!div)
1848 div = 1;
1849
1850 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1851 1 << 16, 1 << 16, &num, &denom);
1852
1853 tdiv64 = sport->port.uartclk;
1854 tdiv64 *= num;
1855 do_div(tdiv64, denom * 16 * div);
1856 tty_termios_encode_baud_rate(termios,
1857 (speed_t)tdiv64, (speed_t)tdiv64);
1858
1859 num -= 1;
1860 denom -= 1;
1861
1862 ufcr = imx_uart_readl(sport, UFCR);
1863 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1864 imx_uart_writel(sport, ufcr, UFCR);
1865
1866 /*
1867 * Two registers below should always be written both and in this
1868 * particular order. One consequence is that we need to check if any of
1869 * them changes and then update both. We do need the check for change
1870 * as even writing the same values seem to "restart"
1871 * transmission/receiving logic in the hardware, that leads to data
1872 * breakage even when rate doesn't in fact change. E.g., user switches
1873 * RTS/CTS handshake and suddenly gets broken bytes.
1874 */
1875 old_ubir = imx_uart_readl(sport, UBIR);
1876 old_ubmr = imx_uart_readl(sport, UBMR);
1877 if (old_ubir != num || old_ubmr != denom) {
1878 imx_uart_writel(sport, num, UBIR);
1879 imx_uart_writel(sport, denom, UBMR);
1880 }
1881
1882 if (!imx_uart_is_imx1(sport))
1883 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1884 IMX21_ONEMS);
1885
1886 imx_uart_writel(sport, ucr2, UCR2);
1887
1888 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1889 imx_uart_enable_ms(&sport->port);
1890
1891 uart_port_unlock_irqrestore(&sport->port, flags);
1892 }
1893
1894 static const char *imx_uart_type(struct uart_port *port)
1895 {
1896 return port->type == PORT_IMX ? "IMX" : NULL;
1897 }
1898
1899 /*
1900 * Configure/autoconfigure the port.
1901 */
1902 static void imx_uart_config_port(struct uart_port *port, int flags)
1903 {
1904 if (flags & UART_CONFIG_TYPE)
1905 port->type = PORT_IMX;
1906 }
1907
1908 /*
1909 * Verify the new serial_struct (for TIOCSSERIAL).
1910 * The only change we allow are to the flags and type, and
1911 * even then only between PORT_IMX and PORT_UNKNOWN
1912 */
1913 static int
1914 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1915 {
1916 int ret = 0;
1917
1918 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1919 ret = -EINVAL;
1920 if (port->irq != ser->irq)
1921 ret = -EINVAL;
1922 if (ser->io_type != UPIO_MEM)
1923 ret = -EINVAL;
1924 if (port->uartclk / 16 != ser->baud_base)
1925 ret = -EINVAL;
1926 if (port->mapbase != (unsigned long)ser->iomem_base)
1927 ret = -EINVAL;
1928 if (port->iobase != ser->port)
1929 ret = -EINVAL;
1930 if (ser->hub6 != 0)
1931 ret = -EINVAL;
1932 return ret;
1933 }
1934
1935 #if defined(CONFIG_CONSOLE_POLL)
1936
1937 static int imx_uart_poll_init(struct uart_port *port)
1938 {
1939 struct imx_port *sport = to_imx_port(port);
1940 unsigned long flags;
1941 u32 ucr1, ucr2;
1942 int retval;
1943
1944 retval = clk_prepare_enable(sport->clk_ipg);
1945 if (retval)
1946 return retval;
1947 retval = clk_prepare_enable(sport->clk_per);
1948 if (retval)
1949 clk_disable_unprepare(sport->clk_ipg);
1950
1951 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1952
1953 uart_port_lock_irqsave(&sport->port, &flags);
1954
1955 /*
1956 * Be careful about the order of enabling bits here. First enable the
1957 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1958 * This prevents that a character that already sits in the RX fifo is
1959 * triggering an irq but the try to fetch it from there results in an
1960 * exception because UARTEN or RXEN is still off.
1961 */
1962 ucr1 = imx_uart_readl(sport, UCR1);
1963 ucr2 = imx_uart_readl(sport, UCR2);
1964
1965 if (imx_uart_is_imx1(sport))
1966 ucr1 |= IMX1_UCR1_UARTCLKEN;
1967
1968 ucr1 |= UCR1_UARTEN;
1969 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1970
1971 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1972 ucr2 &= ~UCR2_ATEN;
1973
1974 imx_uart_writel(sport, ucr1, UCR1);
1975 imx_uart_writel(sport, ucr2, UCR2);
1976
1977 /* now enable irqs */
1978 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1979 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1980
1981 uart_port_unlock_irqrestore(&sport->port, flags);
1982
1983 return 0;
1984 }
1985
1986 static int imx_uart_poll_get_char(struct uart_port *port)
1987 {
1988 struct imx_port *sport = to_imx_port(port);
1989 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1990 return NO_POLL_CHAR;
1991
1992 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1993 }
1994
1995 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1996 {
1997 struct imx_port *sport = to_imx_port(port);
1998 unsigned int status;
1999
2000 /* drain */
2001 do {
2002 status = imx_uart_readl(sport, USR1);
2003 } while (~status & USR1_TRDY);
2004
2005 /* write */
2006 imx_uart_writel(sport, c, URTX0);
2007
2008 /* flush */
2009 do {
2010 status = imx_uart_readl(sport, USR2);
2011 } while (~status & USR2_TXDC);
2012 }
2013 #endif
2014
2015 /* called with port.lock taken and irqs off or from .probe without locking */
2016 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
2017 struct serial_rs485 *rs485conf)
2018 {
2019 struct imx_port *sport = to_imx_port(port);
2020 u32 ucr2, ufcr;
2021
2022 if (rs485conf->flags & SER_RS485_ENABLED) {
2023 /* Enable receiver if low-active RTS signal is requested */
2024 if (sport->have_rtscts && !sport->have_rtsgpio &&
2025 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
2026 rs485conf->flags |= SER_RS485_RX_DURING_TX;
2027
2028 /* disable transmitter */
2029 ucr2 = imx_uart_readl(sport, UCR2);
2030 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
2031 imx_uart_rts_active(sport, &ucr2);
2032 else
2033 imx_uart_rts_inactive(sport, &ucr2);
2034 imx_uart_writel(sport, ucr2, UCR2);
2035 }
2036
2037 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
2038 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
2039 rs485conf->flags & SER_RS485_RX_DURING_TX) {
2040 /* If the receiver trigger is 0, set it to a default value */
2041 ufcr = imx_uart_readl(sport, UFCR);
2042 if ((ufcr & UFCR_RXTL_MASK) == 0)
2043 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2044 imx_uart_start_rx(port);
2045 }
2046
2047 return 0;
2048 }
2049
2050 static const struct uart_ops imx_uart_pops = {
2051 .tx_empty = imx_uart_tx_empty,
2052 .set_mctrl = imx_uart_set_mctrl,
2053 .get_mctrl = imx_uart_get_mctrl,
2054 .stop_tx = imx_uart_stop_tx,
2055 .start_tx = imx_uart_start_tx,
2056 .stop_rx = imx_uart_stop_rx,
2057 .enable_ms = imx_uart_enable_ms,
2058 .break_ctl = imx_uart_break_ctl,
2059 .startup = imx_uart_startup,
2060 .shutdown = imx_uart_shutdown,
2061 .flush_buffer = imx_uart_flush_buffer,
2062 .set_termios = imx_uart_set_termios,
2063 .type = imx_uart_type,
2064 .config_port = imx_uart_config_port,
2065 .verify_port = imx_uart_verify_port,
2066 #if defined(CONFIG_CONSOLE_POLL)
2067 .poll_init = imx_uart_poll_init,
2068 .poll_get_char = imx_uart_poll_get_char,
2069 .poll_put_char = imx_uart_poll_put_char,
2070 #endif
2071 };
2072
2073 static struct imx_port *imx_uart_ports[UART_NR];
2074
2075 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
2076 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
2077 {
2078 struct imx_port *sport = to_imx_port(port);
2079
2080 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
2081 barrier();
2082
2083 imx_uart_writel(sport, ch, URTX0);
2084
2085 sport->last_putchar_was_newline = (ch == '\n');
2086 }
2087
2088 static void imx_uart_console_device_lock(struct console *co, unsigned long *flags)
2089 {
2090 struct uart_port *up = &imx_uart_ports[co->index]->port;
2091
2092 return __uart_port_lock_irqsave(up, flags);
2093 }
2094
2095 static void imx_uart_console_device_unlock(struct console *co, unsigned long flags)
2096 {
2097 struct uart_port *up = &imx_uart_ports[co->index]->port;
2098
2099 return __uart_port_unlock_irqrestore(up, flags);
2100 }
2101
2102 static void imx_uart_console_write_atomic(struct console *co,
2103 struct nbcon_write_context *wctxt)
2104 {
2105 struct imx_port *sport = imx_uart_ports[co->index];
2106 struct uart_port *port = &sport->port;
2107 struct imx_port_ucrs old_ucr;
2108 unsigned int ucr1, usr2;
2109
2110 if (!nbcon_enter_unsafe(wctxt))
2111 return;
2112
2113 /*
2114 * First, save UCR1/2/3 and then disable interrupts
2115 */
2116 imx_uart_ucrs_save(sport, &old_ucr);
2117 ucr1 = old_ucr.ucr1;
2118
2119 if (imx_uart_is_imx1(sport))
2120 ucr1 |= IMX1_UCR1_UARTCLKEN;
2121 ucr1 |= UCR1_UARTEN;
2122 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2123
2124 imx_uart_writel(sport, ucr1, UCR1);
2125 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2126
2127 if (!sport->last_putchar_was_newline)
2128 uart_console_write(port, "\n", 1, imx_uart_console_putchar);
2129 uart_console_write(port, wctxt->outbuf, wctxt->len,
2130 imx_uart_console_putchar);
2131
2132 /*
2133 * Finally, wait for transmitter to become empty
2134 * and restore UCR1/2/3
2135 */
2136 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2137 0, USEC_PER_SEC, false, sport, USR2);
2138 imx_uart_ucrs_restore(sport, &old_ucr);
2139
2140 nbcon_exit_unsafe(wctxt);
2141 }
2142
2143 static void imx_uart_console_write_thread(struct console *co,
2144 struct nbcon_write_context *wctxt)
2145 {
2146 struct imx_port *sport = imx_uart_ports[co->index];
2147 struct uart_port *port = &sport->port;
2148 struct imx_port_ucrs old_ucr;
2149 unsigned int ucr1, usr2;
2150
2151 if (!nbcon_enter_unsafe(wctxt))
2152 return;
2153
2154 /*
2155 * First, save UCR1/2/3 and then disable interrupts
2156 */
2157 imx_uart_ucrs_save(sport, &old_ucr);
2158 ucr1 = old_ucr.ucr1;
2159
2160 if (imx_uart_is_imx1(sport))
2161 ucr1 |= IMX1_UCR1_UARTCLKEN;
2162 ucr1 |= UCR1_UARTEN;
2163 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2164
2165 imx_uart_writel(sport, ucr1, UCR1);
2166 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2167
2168 if (nbcon_exit_unsafe(wctxt)) {
2169 int len = READ_ONCE(wctxt->len);
2170 int i;
2171
2172 /*
2173 * Write out the message. Toggle unsafe for each byte in order
2174 * to give another (higher priority) context the opportunity
2175 * for a friendly takeover. If such a takeover occurs, this
2176 * context must reacquire ownership in order to perform final
2177 * actions (such as re-enabling the interrupts).
2178 *
2179 * IMPORTANT: wctxt->outbuf and wctxt->len are no longer valid
2180 * after a reacquire so writing the message must be
2181 * aborted.
2182 */
2183 for (i = 0; i < len; i++) {
2184 if (!nbcon_enter_unsafe(wctxt))
2185 break;
2186
2187 uart_console_write(port, wctxt->outbuf + i, 1,
2188 imx_uart_console_putchar);
2189
2190 if (!nbcon_exit_unsafe(wctxt))
2191 break;
2192 }
2193 }
2194
2195 while (!nbcon_enter_unsafe(wctxt))
2196 nbcon_reacquire_nobuf(wctxt);
2197
2198 /*
2199 * Finally, wait for transmitter to become empty
2200 * and restore UCR1/2/3
2201 */
2202 read_poll_timeout(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2203 0, USEC_PER_SEC, false, sport, USR2);
2204 imx_uart_ucrs_restore(sport, &old_ucr);
2205
2206 nbcon_exit_unsafe(wctxt);
2207 }
2208
2209 /*
2210 * If the port was already initialised (eg, by a boot loader),
2211 * try to determine the current setup.
2212 */
2213 static void
2214 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2215 int *parity, int *bits)
2216 {
2217
2218 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2219 /* ok, the port was enabled */
2220 unsigned int ucr2, ubir, ubmr, uartclk;
2221 unsigned int baud_raw;
2222 unsigned int ucfr_rfdiv;
2223
2224 ucr2 = imx_uart_readl(sport, UCR2);
2225
2226 *parity = 'n';
2227 if (ucr2 & UCR2_PREN) {
2228 if (ucr2 & UCR2_PROE)
2229 *parity = 'o';
2230 else
2231 *parity = 'e';
2232 }
2233
2234 if (ucr2 & UCR2_WS)
2235 *bits = 8;
2236 else
2237 *bits = 7;
2238
2239 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2240 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2241
2242 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2243 if (ucfr_rfdiv == 6)
2244 ucfr_rfdiv = 7;
2245 else
2246 ucfr_rfdiv = 6 - ucfr_rfdiv;
2247
2248 uartclk = clk_get_rate(sport->clk_per);
2249 uartclk /= ucfr_rfdiv;
2250
2251 { /*
2252 * The next code provides exact computation of
2253 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2254 * without need of float support or long long division,
2255 * which would be required to prevent 32bit arithmetic overflow
2256 */
2257 unsigned int mul = ubir + 1;
2258 unsigned int div = 16 * (ubmr + 1);
2259 unsigned int rem = uartclk % div;
2260
2261 baud_raw = (uartclk / div) * mul;
2262 baud_raw += (rem * mul + div / 2) / div;
2263 *baud = (baud_raw + 50) / 100 * 100;
2264 }
2265
2266 if (*baud != baud_raw)
2267 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2268 baud_raw, *baud);
2269 }
2270 }
2271
2272 static int
2273 imx_uart_console_setup(struct console *co, char *options)
2274 {
2275 struct imx_port *sport;
2276 int baud = 9600;
2277 int bits = 8;
2278 int parity = 'n';
2279 int flow = 'n';
2280 int retval;
2281
2282 /*
2283 * Check whether an invalid uart number has been specified, and
2284 * if so, search for the first available port that does have
2285 * console support.
2286 */
2287 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2288 co->index = 0;
2289 sport = imx_uart_ports[co->index];
2290 if (sport == NULL)
2291 return -ENODEV;
2292
2293 /* For setting the registers, we only need to enable the ipg clock. */
2294 retval = clk_prepare_enable(sport->clk_ipg);
2295 if (retval)
2296 goto error_console;
2297
2298 sport->last_putchar_was_newline = true;
2299
2300 if (options)
2301 uart_parse_options(options, &baud, &parity, &bits, &flow);
2302 else
2303 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2304
2305 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2306
2307 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2308
2309 if (retval) {
2310 clk_disable_unprepare(sport->clk_ipg);
2311 goto error_console;
2312 }
2313
2314 retval = clk_prepare_enable(sport->clk_per);
2315 if (retval)
2316 clk_disable_unprepare(sport->clk_ipg);
2317
2318 error_console:
2319 return retval;
2320 }
2321
2322 static int
2323 imx_uart_console_exit(struct console *co)
2324 {
2325 struct imx_port *sport = imx_uart_ports[co->index];
2326
2327 clk_disable_unprepare(sport->clk_per);
2328 clk_disable_unprepare(sport->clk_ipg);
2329
2330 return 0;
2331 }
2332
2333 static struct uart_driver imx_uart_uart_driver;
2334 static struct console imx_uart_console = {
2335 .name = DEV_NAME,
2336 .write_atomic = imx_uart_console_write_atomic,
2337 .write_thread = imx_uart_console_write_thread,
2338 .device_lock = imx_uart_console_device_lock,
2339 .device_unlock = imx_uart_console_device_unlock,
2340 .flags = CON_PRINTBUFFER | CON_NBCON,
2341 .device = uart_console_device,
2342 .setup = imx_uart_console_setup,
2343 .exit = imx_uart_console_exit,
2344 .index = -1,
2345 .data = &imx_uart_uart_driver,
2346 };
2347
2348 #define IMX_CONSOLE &imx_uart_console
2349
2350 #else
2351 #define IMX_CONSOLE NULL
2352 #endif
2353
2354 static struct uart_driver imx_uart_uart_driver = {
2355 .owner = THIS_MODULE,
2356 .driver_name = DRIVER_NAME,
2357 .dev_name = DEV_NAME,
2358 .major = SERIAL_IMX_MAJOR,
2359 .minor = MINOR_START,
2360 .nr = ARRAY_SIZE(imx_uart_ports),
2361 .cons = IMX_CONSOLE,
2362 };
2363
2364 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2365 {
2366 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2367 unsigned long flags;
2368
2369 uart_port_lock_irqsave(&sport->port, &flags);
2370 if (sport->tx_state == WAIT_AFTER_RTS)
2371 imx_uart_start_tx(&sport->port);
2372 uart_port_unlock_irqrestore(&sport->port, flags);
2373
2374 return HRTIMER_NORESTART;
2375 }
2376
2377 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2378 {
2379 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2380 unsigned long flags;
2381
2382 uart_port_lock_irqsave(&sport->port, &flags);
2383 if (sport->tx_state == WAIT_AFTER_SEND)
2384 imx_uart_stop_tx(&sport->port);
2385 uart_port_unlock_irqrestore(&sport->port, flags);
2386
2387 return HRTIMER_NORESTART;
2388 }
2389
2390 static const struct serial_rs485 imx_rs485_supported = {
2391 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2392 SER_RS485_RX_DURING_TX,
2393 .delay_rts_before_send = 1,
2394 .delay_rts_after_send = 1,
2395 };
2396
2397 /* Default RX DMA buffer configuration */
2398 #define RX_DMA_PERIODS 16
2399 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2400
2401 static int imx_uart_probe(struct platform_device *pdev)
2402 {
2403 struct device_node *np = pdev->dev.of_node;
2404 struct imx_port *sport;
2405 void __iomem *base;
2406 u32 dma_buf_conf[2];
2407 int ret = 0;
2408 u32 ucr1, ucr2, uts;
2409 struct resource *res;
2410 int txirq, rxirq, rtsirq;
2411
2412 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2413 if (!sport)
2414 return -ENOMEM;
2415
2416 sport->devdata = of_device_get_match_data(&pdev->dev);
2417
2418 ret = of_alias_get_id(np, "serial");
2419 if (ret < 0) {
2420 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2421 return ret;
2422 }
2423 sport->port.line = ret;
2424
2425 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2426 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2427
2428 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2429
2430 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2431
2432 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2433
2434 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2435
2436 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2437 sport->rx_period_length = dma_buf_conf[0];
2438 sport->rx_periods = dma_buf_conf[1];
2439 } else {
2440 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2441 sport->rx_periods = RX_DMA_PERIODS;
2442 }
2443
2444 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2445 dev_err(&pdev->dev, "serial%d out of range\n",
2446 sport->port.line);
2447 return -EINVAL;
2448 }
2449
2450 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2451 if (IS_ERR(base))
2452 return PTR_ERR(base);
2453
2454 rxirq = platform_get_irq(pdev, 0);
2455 if (rxirq < 0)
2456 return rxirq;
2457 txirq = platform_get_irq_optional(pdev, 1);
2458 rtsirq = platform_get_irq_optional(pdev, 2);
2459
2460 sport->port.dev = &pdev->dev;
2461 sport->port.mapbase = res->start;
2462 sport->port.membase = base;
2463 sport->port.type = PORT_IMX;
2464 sport->port.iotype = UPIO_MEM;
2465 sport->port.irq = rxirq;
2466 sport->port.fifosize = 32;
2467 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2468 sport->port.ops = &imx_uart_pops;
2469 sport->port.rs485_config = imx_uart_rs485_config;
2470 /* RTS is required to control the RS485 transmitter */
2471 if (sport->have_rtscts || sport->have_rtsgpio)
2472 sport->port.rs485_supported = imx_rs485_supported;
2473 sport->port.flags = UPF_BOOT_AUTOCONF;
2474 timer_setup(&sport->timer, imx_uart_timeout, 0);
2475
2476 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2477 if (IS_ERR(sport->gpios))
2478 return PTR_ERR(sport->gpios);
2479
2480 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2481 if (IS_ERR(sport->clk_ipg)) {
2482 ret = PTR_ERR(sport->clk_ipg);
2483 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2484 return ret;
2485 }
2486
2487 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2488 if (IS_ERR(sport->clk_per)) {
2489 ret = PTR_ERR(sport->clk_per);
2490 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2491 return ret;
2492 }
2493
2494 sport->port.uartclk = clk_get_rate(sport->clk_per);
2495
2496 /* For register access, we only need to enable the ipg clock. */
2497 ret = clk_prepare_enable(sport->clk_ipg);
2498 if (ret) {
2499 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2500 return ret;
2501 }
2502
2503 ret = uart_get_rs485_mode(&sport->port);
2504 if (ret)
2505 goto err_clk;
2506
2507 /*
2508 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2509 * signal cannot be set low during transmission in case the
2510 * receiver is off (limitation of the i.MX UART IP).
2511 */
2512 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2513 sport->have_rtscts && !sport->have_rtsgpio &&
2514 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2515 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2516 dev_err(&pdev->dev,
2517 "low-active RTS not possible when receiver is off, enabling receiver\n");
2518
2519 /* Disable interrupts before requesting them */
2520 ucr1 = imx_uart_readl(sport, UCR1);
2521 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2522 imx_uart_writel(sport, ucr1, UCR1);
2523
2524 /* Disable Ageing Timer interrupt */
2525 ucr2 = imx_uart_readl(sport, UCR2);
2526 ucr2 &= ~UCR2_ATEN;
2527 imx_uart_writel(sport, ucr2, UCR2);
2528
2529 /*
2530 * In case RS485 is enabled without GPIO RTS control, the UART IP
2531 * is used to control CTS signal. Keep both the UART and Receiver
2532 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2533 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2534 * data from being fed into the RX FIFO, enable loopback mode in
2535 * UTS register, which disconnects the RX path from external RXD
2536 * pin and connects it to the Transceiver, which is disabled, so
2537 * no data can be fed to the RX FIFO that way.
2538 */
2539 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2540 sport->have_rtscts && !sport->have_rtsgpio) {
2541 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2542 uts |= UTS_LOOP;
2543 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2544
2545 ucr1 = imx_uart_readl(sport, UCR1);
2546 ucr1 |= UCR1_UARTEN;
2547 imx_uart_writel(sport, ucr1, UCR1);
2548
2549 ucr2 = imx_uart_readl(sport, UCR2);
2550 ucr2 |= UCR2_RXEN;
2551 imx_uart_writel(sport, ucr2, UCR2);
2552 }
2553
2554 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2555 /*
2556 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2557 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2558 * and DCD (when they are outputs) or enables the respective
2559 * irqs. So set this bit early, i.e. before requesting irqs.
2560 */
2561 u32 ufcr = imx_uart_readl(sport, UFCR);
2562 if (!(ufcr & UFCR_DCEDTE))
2563 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2564
2565 /*
2566 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2567 * enabled later because they cannot be cleared
2568 * (confirmed on i.MX25) which makes them unusable.
2569 */
2570 imx_uart_writel(sport,
2571 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2572 UCR3);
2573
2574 } else {
2575 u32 ucr3 = UCR3_DSR;
2576 u32 ufcr = imx_uart_readl(sport, UFCR);
2577 if (ufcr & UFCR_DCEDTE)
2578 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2579
2580 if (!imx_uart_is_imx1(sport))
2581 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2582 imx_uart_writel(sport, ucr3, UCR3);
2583 }
2584
2585 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2586 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2587 sport->trigger_start_tx.function = imx_trigger_start_tx;
2588 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2589
2590 /*
2591 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2592 * chips only have one interrupt.
2593 */
2594 if (txirq > 0) {
2595 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2596 dev_name(&pdev->dev), sport);
2597 if (ret) {
2598 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2599 ret);
2600 goto err_clk;
2601 }
2602
2603 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2604 dev_name(&pdev->dev), sport);
2605 if (ret) {
2606 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2607 ret);
2608 goto err_clk;
2609 }
2610
2611 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2612 dev_name(&pdev->dev), sport);
2613 if (ret) {
2614 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2615 ret);
2616 goto err_clk;
2617 }
2618 } else {
2619 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2620 dev_name(&pdev->dev), sport);
2621 if (ret) {
2622 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2623 goto err_clk;
2624 }
2625 }
2626
2627 imx_uart_ports[sport->port.line] = sport;
2628
2629 platform_set_drvdata(pdev, sport);
2630
2631 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2632
2633 err_clk:
2634 clk_disable_unprepare(sport->clk_ipg);
2635
2636 return ret;
2637 }
2638
2639 static void imx_uart_remove(struct platform_device *pdev)
2640 {
2641 struct imx_port *sport = platform_get_drvdata(pdev);
2642
2643 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2644 }
2645
2646 static void imx_uart_restore_context(struct imx_port *sport)
2647 {
2648 unsigned long flags;
2649
2650 uart_port_lock_irqsave(&sport->port, &flags);
2651 if (!sport->context_saved) {
2652 uart_port_unlock_irqrestore(&sport->port, flags);
2653 return;
2654 }
2655
2656 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2657 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2658 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2659 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2660 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2661 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2662 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2663 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2664 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2665 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2666 sport->context_saved = false;
2667 uart_port_unlock_irqrestore(&sport->port, flags);
2668 }
2669
2670 static void imx_uart_save_context(struct imx_port *sport)
2671 {
2672 unsigned long flags;
2673
2674 /* Save necessary regs */
2675 uart_port_lock_irqsave(&sport->port, &flags);
2676 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2677 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2678 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2679 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2680 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2681 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2682 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2683 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2684 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2685 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2686 sport->context_saved = true;
2687 uart_port_unlock_irqrestore(&sport->port, flags);
2688 }
2689
2690 /* called with irq off */
2691 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2692 {
2693 u32 ucr3;
2694
2695 uart_port_lock(&sport->port);
2696
2697 ucr3 = imx_uart_readl(sport, UCR3);
2698 if (on) {
2699 imx_uart_writel(sport, USR1_AWAKE, USR1);
2700 ucr3 |= UCR3_AWAKEN;
2701 } else {
2702 ucr3 &= ~UCR3_AWAKEN;
2703 }
2704 imx_uart_writel(sport, ucr3, UCR3);
2705
2706 if (sport->have_rtscts) {
2707 u32 ucr1 = imx_uart_readl(sport, UCR1);
2708 if (on) {
2709 imx_uart_writel(sport, USR1_RTSD, USR1);
2710 ucr1 |= UCR1_RTSDEN;
2711 } else {
2712 ucr1 &= ~UCR1_RTSDEN;
2713 }
2714 imx_uart_writel(sport, ucr1, UCR1);
2715 }
2716
2717 uart_port_unlock(&sport->port);
2718 }
2719
2720 static int imx_uart_suspend_noirq(struct device *dev)
2721 {
2722 struct imx_port *sport = dev_get_drvdata(dev);
2723
2724 imx_uart_save_context(sport);
2725
2726 clk_disable(sport->clk_ipg);
2727
2728 pinctrl_pm_select_sleep_state(dev);
2729
2730 return 0;
2731 }
2732
2733 static int imx_uart_resume_noirq(struct device *dev)
2734 {
2735 struct imx_port *sport = dev_get_drvdata(dev);
2736 int ret;
2737
2738 pinctrl_pm_select_default_state(dev);
2739
2740 ret = clk_enable(sport->clk_ipg);
2741 if (ret)
2742 return ret;
2743
2744 imx_uart_restore_context(sport);
2745
2746 return 0;
2747 }
2748
2749 static int imx_uart_suspend(struct device *dev)
2750 {
2751 struct imx_port *sport = dev_get_drvdata(dev);
2752 int ret;
2753
2754 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2755 disable_irq(sport->port.irq);
2756
2757 ret = clk_prepare_enable(sport->clk_ipg);
2758 if (ret)
2759 return ret;
2760
2761 /* enable wakeup from i.MX UART */
2762 imx_uart_enable_wakeup(sport, true);
2763
2764 return 0;
2765 }
2766
2767 static int imx_uart_resume(struct device *dev)
2768 {
2769 struct imx_port *sport = dev_get_drvdata(dev);
2770
2771 /* disable wakeup from i.MX UART */
2772 imx_uart_enable_wakeup(sport, false);
2773
2774 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2775 enable_irq(sport->port.irq);
2776
2777 clk_disable_unprepare(sport->clk_ipg);
2778
2779 return 0;
2780 }
2781
2782 static int imx_uart_freeze(struct device *dev)
2783 {
2784 struct imx_port *sport = dev_get_drvdata(dev);
2785
2786 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2787
2788 return clk_prepare_enable(sport->clk_ipg);
2789 }
2790
2791 static int imx_uart_thaw(struct device *dev)
2792 {
2793 struct imx_port *sport = dev_get_drvdata(dev);
2794
2795 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2796
2797 clk_disable_unprepare(sport->clk_ipg);
2798
2799 return 0;
2800 }
2801
2802 static const struct dev_pm_ops imx_uart_pm_ops = {
2803 .suspend_noirq = imx_uart_suspend_noirq,
2804 .resume_noirq = imx_uart_resume_noirq,
2805 .freeze_noirq = imx_uart_suspend_noirq,
2806 .thaw_noirq = imx_uart_resume_noirq,
2807 .restore_noirq = imx_uart_resume_noirq,
2808 .suspend = imx_uart_suspend,
2809 .resume = imx_uart_resume,
2810 .freeze = imx_uart_freeze,
2811 .thaw = imx_uart_thaw,
2812 .restore = imx_uart_thaw,
2813 };
2814
2815 static struct platform_driver imx_uart_platform_driver = {
2816 .probe = imx_uart_probe,
2817 .remove = imx_uart_remove,
2818
2819 .driver = {
2820 .name = "imx-uart",
2821 .of_match_table = imx_uart_dt_ids,
2822 .pm = &imx_uart_pm_ops,
2823 },
2824 };
2825
2826 static int __init imx_uart_init(void)
2827 {
2828 int ret = uart_register_driver(&imx_uart_uart_driver);
2829
2830 if (ret)
2831 return ret;
2832
2833 ret = platform_driver_register(&imx_uart_platform_driver);
2834 if (ret != 0)
2835 uart_unregister_driver(&imx_uart_uart_driver);
2836
2837 return ret;
2838 }
2839
2840 static void __exit imx_uart_exit(void)
2841 {
2842 platform_driver_unregister(&imx_uart_platform_driver);
2843 uart_unregister_driver(&imx_uart_uart_driver);
2844 }
2845
2846 module_init(imx_uart_init);
2847 module_exit(imx_uart_exit);
2848
2849 MODULE_AUTHOR("Sascha Hauer");
2850 MODULE_DESCRIPTION("IMX generic serial port driver");
2851 MODULE_LICENSE("GPL");
2852 MODULE_ALIAS("platform:imx-uart");
Kernel DRM miscellaneous fixes and cross-tree changes