1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Comtrol RocketPort EXPRESS/INFINITY cards
5 * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
7 * Inspired by, and loosely based on:
10 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
12 * rocketport_infinity_express-linux-1.20.tar.gz
13 * Copyright (C) 2004-2011 Comtrol, Inc.
16 #include <linux/bitops.h>
17 #include <linux/compiler.h>
18 #include <linux/completion.h>
19 #include <linux/console.h>
20 #include <linux/delay.h>
21 #include <linux/firmware.h>
22 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/log2.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/serial.h>
31 #include <linux/serial_core.h>
32 #include <linux/slab.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/types.h>
38 #define DRV_NAME "rp2"
40 #define RP2_FW_NAME "rp2.fw"
41 #define RP2_UCODE_BYTES 0x3f
43 #define PORTS_PER_ASIC 16
44 #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
46 #define UART_CLOCK 44236800
47 #define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
51 #define RP2_FPGA_CTL0 0x110
52 #define RP2_FPGA_CTL1 0x11c
53 #define RP2_IRQ_MASK 0x1ec
54 #define RP2_IRQ_MASK_EN_m BIT(0)
55 #define RP2_IRQ_STATUS 0x1f0
58 #define RP2_ASIC_SPACING 0x1000
59 #define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
61 #define RP2_PORT_BASE 0x000
62 #define RP2_PORT_SPACING 0x040
64 #define RP2_UCODE_BASE 0x400
65 #define RP2_UCODE_SPACING 0x80
67 #define RP2_CLK_PRESCALER 0xc00
68 #define RP2_CH_IRQ_STAT 0xc04
69 #define RP2_CH_IRQ_MASK 0xc08
70 #define RP2_ASIC_IRQ 0xd00
71 #define RP2_ASIC_IRQ_EN_m BIT(20)
72 #define RP2_GLOBAL_CMD 0xd0c
73 #define RP2_ASIC_CFG 0xd04
76 #define RP2_DATA_DWORD 0x000
78 #define RP2_DATA_BYTE 0x008
79 #define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
80 #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
81 #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
82 #define RP2_DATA_BYTE_BREAK_m BIT(11)
84 /* This lets uart_insert_char() drop bytes received on a !CREAD port */
85 #define RP2_DUMMY_READ BIT(16)
87 #define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
88 RP2_DATA_BYTE_ERR_OVERRUN_m | \
89 RP2_DATA_BYTE_ERR_FRAMING_m | \
90 RP2_DATA_BYTE_BREAK_m)
92 #define RP2_RX_FIFO_COUNT 0x00c
93 #define RP2_TX_FIFO_COUNT 0x00e
95 #define RP2_CHAN_STAT 0x010
96 #define RP2_CHAN_STAT_RXDATA_m BIT(0)
97 #define RP2_CHAN_STAT_DCD_m BIT(3)
98 #define RP2_CHAN_STAT_DSR_m BIT(4)
99 #define RP2_CHAN_STAT_CTS_m BIT(5)
100 #define RP2_CHAN_STAT_RI_m BIT(6)
101 #define RP2_CHAN_STAT_OVERRUN_m BIT(13)
102 #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
103 #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
104 #define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
105 #define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
106 #define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
108 #define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
109 RP2_CHAN_STAT_CTS_CHANGED_m | \
110 RP2_CHAN_STAT_CD_CHANGED_m | \
111 RP2_CHAN_STAT_RI_CHANGED_m)
113 #define RP2_TXRX_CTL 0x014
114 #define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
115 #define RP2_TXRX_CTL_RXIRQ_m BIT(2)
116 #define RP2_TXRX_CTL_RX_TRIG_s 3
117 #define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
118 #define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
119 #define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
120 #define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
121 #define RP2_TXRX_CTL_RX_EN_m BIT(5)
122 #define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
123 #define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
124 #define RP2_TXRX_CTL_TX_TRIG_s 16
125 #define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
126 #define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
127 #define RP2_TXRX_CTL_TXIRQ_m BIT(19)
128 #define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
129 #define RP2_TXRX_CTL_TX_EN_m BIT(24)
130 #define RP2_TXRX_CTL_RTS_m BIT(25)
131 #define RP2_TXRX_CTL_DTR_m BIT(26)
132 #define RP2_TXRX_CTL_LOOP_m BIT(27)
133 #define RP2_TXRX_CTL_BREAK_m BIT(28)
134 #define RP2_TXRX_CTL_CMSPAR_m BIT(29)
135 #define RP2_TXRX_CTL_nPARODD_m BIT(30)
136 #define RP2_TXRX_CTL_PARENB_m BIT(31)
138 #define RP2_UART_CTL 0x018
139 #define RP2_UART_CTL_MODE_s 0
140 #define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
141 #define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
142 #define RP2_UART_CTL_FLUSH_RX_m BIT(3)
143 #define RP2_UART_CTL_FLUSH_TX_m BIT(4)
144 #define RP2_UART_CTL_RESET_CH_m BIT(5)
145 #define RP2_UART_CTL_XMIT_EN_m BIT(6)
146 #define RP2_UART_CTL_DATABITS_s 8
147 #define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
148 #define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
149 #define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
150 #define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
151 #define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
152 #define RP2_UART_CTL_STOPBITS_m BIT(10)
154 #define RP2_BAUD 0x01c
156 /* ucode registers */
157 #define RP2_TX_SWFLOW 0x02
158 #define RP2_TX_SWFLOW_ena 0x81
159 #define RP2_TX_SWFLOW_dis 0x9d
161 #define RP2_RX_SWFLOW 0x0c
162 #define RP2_RX_SWFLOW_ena 0x81
163 #define RP2_RX_SWFLOW_dis 0x8d
165 #define RP2_RX_FIFO 0x37
166 #define RP2_RX_FIFO_ena 0x08
167 #define RP2_RX_FIFO_dis 0x81
169 static struct uart_driver rp2_uart_driver
= {
170 .owner
= THIS_MODULE
,
171 .driver_name
= DRV_NAME
,
173 .nr
= CONFIG_SERIAL_RP2_NR_UARTS
,
178 struct rp2_uart_port
{
179 struct uart_port port
;
181 struct rp2_card
*card
;
182 void __iomem
*asic_base
;
188 struct pci_dev
*pdev
;
189 struct rp2_uart_port
*ports
;
191 int initialized_ports
;
196 spinlock_t card_lock
;
199 #define RP_ID(prod) PCI_VDEVICE(RP, (prod))
200 #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
202 static inline void rp2_decode_cap(const struct pci_device_id
*id
,
203 int *ports
, int *smpte
)
205 *ports
= id
->driver_data
>> 8;
206 *smpte
= id
->driver_data
& 0xff;
209 static DEFINE_SPINLOCK(rp2_minor_lock
);
210 static int rp2_minor_next
;
212 static int rp2_alloc_ports(int n_ports
)
216 spin_lock(&rp2_minor_lock
);
217 if (rp2_minor_next
+ n_ports
<= CONFIG_SERIAL_RP2_NR_UARTS
) {
218 /* sorry, no support for hot unplugging individual cards */
219 ret
= rp2_minor_next
;
220 rp2_minor_next
+= n_ports
;
222 spin_unlock(&rp2_minor_lock
);
227 static inline struct rp2_uart_port
*port_to_up(struct uart_port
*port
)
229 return container_of(port
, struct rp2_uart_port
, port
);
232 static void rp2_rmw(struct rp2_uart_port
*up
, int reg
,
233 u32 clr_bits
, u32 set_bits
)
235 u32 tmp
= readl(up
->base
+ reg
);
238 writel(tmp
, up
->base
+ reg
);
241 static void rp2_rmw_clr(struct rp2_uart_port
*up
, int reg
, u32 val
)
243 rp2_rmw(up
, reg
, val
, 0);
246 static void rp2_rmw_set(struct rp2_uart_port
*up
, int reg
, u32 val
)
248 rp2_rmw(up
, reg
, 0, val
);
251 static void rp2_mask_ch_irq(struct rp2_uart_port
*up
, int ch_num
,
254 unsigned long flags
, irq_mask
;
256 spin_lock_irqsave(&up
->card
->card_lock
, flags
);
258 irq_mask
= readl(up
->asic_base
+ RP2_CH_IRQ_MASK
);
260 irq_mask
&= ~BIT(ch_num
);
262 irq_mask
|= BIT(ch_num
);
263 writel(irq_mask
, up
->asic_base
+ RP2_CH_IRQ_MASK
);
265 spin_unlock_irqrestore(&up
->card
->card_lock
, flags
);
268 static unsigned int rp2_uart_tx_empty(struct uart_port
*port
)
270 struct rp2_uart_port
*up
= port_to_up(port
);
271 unsigned long tx_fifo_bytes
, flags
;
274 * This should probably check the transmitter, not the FIFO.
275 * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is
278 uart_port_lock_irqsave(&up
->port
, &flags
);
279 tx_fifo_bytes
= readw(up
->base
+ RP2_TX_FIFO_COUNT
);
280 uart_port_unlock_irqrestore(&up
->port
, flags
);
282 return tx_fifo_bytes
? 0 : TIOCSER_TEMT
;
285 static unsigned int rp2_uart_get_mctrl(struct uart_port
*port
)
287 struct rp2_uart_port
*up
= port_to_up(port
);
290 status
= readl(up
->base
+ RP2_CHAN_STAT
);
291 return ((status
& RP2_CHAN_STAT_DCD_m
) ? TIOCM_CAR
: 0) |
292 ((status
& RP2_CHAN_STAT_DSR_m
) ? TIOCM_DSR
: 0) |
293 ((status
& RP2_CHAN_STAT_CTS_m
) ? TIOCM_CTS
: 0) |
294 ((status
& RP2_CHAN_STAT_RI_m
) ? TIOCM_RI
: 0);
297 static void rp2_uart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
299 rp2_rmw(port_to_up(port
), RP2_TXRX_CTL
,
300 RP2_TXRX_CTL_DTR_m
| RP2_TXRX_CTL_RTS_m
| RP2_TXRX_CTL_LOOP_m
,
301 ((mctrl
& TIOCM_DTR
) ? RP2_TXRX_CTL_DTR_m
: 0) |
302 ((mctrl
& TIOCM_RTS
) ? RP2_TXRX_CTL_RTS_m
: 0) |
303 ((mctrl
& TIOCM_LOOP
) ? RP2_TXRX_CTL_LOOP_m
: 0));
306 static void rp2_uart_start_tx(struct uart_port
*port
)
308 rp2_rmw_set(port_to_up(port
), RP2_TXRX_CTL
, RP2_TXRX_CTL_TXIRQ_m
);
311 static void rp2_uart_stop_tx(struct uart_port
*port
)
313 rp2_rmw_clr(port_to_up(port
), RP2_TXRX_CTL
, RP2_TXRX_CTL_TXIRQ_m
);
316 static void rp2_uart_stop_rx(struct uart_port
*port
)
318 rp2_rmw_clr(port_to_up(port
), RP2_TXRX_CTL
, RP2_TXRX_CTL_RXIRQ_m
);
321 static void rp2_uart_break_ctl(struct uart_port
*port
, int break_state
)
325 uart_port_lock_irqsave(port
, &flags
);
326 rp2_rmw(port_to_up(port
), RP2_TXRX_CTL
, RP2_TXRX_CTL_BREAK_m
,
327 break_state
? RP2_TXRX_CTL_BREAK_m
: 0);
328 uart_port_unlock_irqrestore(port
, flags
);
331 static void rp2_uart_enable_ms(struct uart_port
*port
)
333 rp2_rmw_set(port_to_up(port
), RP2_TXRX_CTL
, RP2_TXRX_CTL_MSRIRQ_m
);
336 static void __rp2_uart_set_termios(struct rp2_uart_port
*up
,
339 unsigned int baud_div
)
341 /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */
342 writew(baud_div
- 1, up
->base
+ RP2_BAUD
);
344 /* data bits and stop bits */
345 rp2_rmw(up
, RP2_UART_CTL
,
346 RP2_UART_CTL_STOPBITS_m
| RP2_UART_CTL_DATABITS_m
,
347 ((cfl
& CSTOPB
) ? RP2_UART_CTL_STOPBITS_m
: 0) |
348 (((cfl
& CSIZE
) == CS8
) ? RP2_UART_CTL_DATABITS_8
: 0) |
349 (((cfl
& CSIZE
) == CS7
) ? RP2_UART_CTL_DATABITS_7
: 0) |
350 (((cfl
& CSIZE
) == CS6
) ? RP2_UART_CTL_DATABITS_6
: 0) |
351 (((cfl
& CSIZE
) == CS5
) ? RP2_UART_CTL_DATABITS_5
: 0));
353 /* parity and hardware flow control */
354 rp2_rmw(up
, RP2_TXRX_CTL
,
355 RP2_TXRX_CTL_PARENB_m
| RP2_TXRX_CTL_nPARODD_m
|
356 RP2_TXRX_CTL_CMSPAR_m
| RP2_TXRX_CTL_DTRFLOW_m
|
357 RP2_TXRX_CTL_DSRFLOW_m
| RP2_TXRX_CTL_RTSFLOW_m
|
358 RP2_TXRX_CTL_CTSFLOW_m
,
359 ((cfl
& PARENB
) ? RP2_TXRX_CTL_PARENB_m
: 0) |
360 ((cfl
& PARODD
) ? 0 : RP2_TXRX_CTL_nPARODD_m
) |
361 ((cfl
& CMSPAR
) ? RP2_TXRX_CTL_CMSPAR_m
: 0) |
362 ((cfl
& CRTSCTS
) ? (RP2_TXRX_CTL_RTSFLOW_m
|
363 RP2_TXRX_CTL_CTSFLOW_m
) : 0));
365 /* XON/XOFF software flow control */
366 writeb((ifl
& IXON
) ? RP2_TX_SWFLOW_ena
: RP2_TX_SWFLOW_dis
,
367 up
->ucode
+ RP2_TX_SWFLOW
);
368 writeb((ifl
& IXOFF
) ? RP2_RX_SWFLOW_ena
: RP2_RX_SWFLOW_dis
,
369 up
->ucode
+ RP2_RX_SWFLOW
);
372 static void rp2_uart_set_termios(struct uart_port
*port
, struct ktermios
*new,
373 const struct ktermios
*old
)
375 struct rp2_uart_port
*up
= port_to_up(port
);
377 unsigned int baud
, baud_div
;
379 baud
= uart_get_baud_rate(port
, new, old
, 0, port
->uartclk
/ 16);
380 baud_div
= uart_get_divisor(port
, baud
);
382 if (tty_termios_baud_rate(new))
383 tty_termios_encode_baud_rate(new, baud
, baud
);
385 uart_port_lock_irqsave(port
, &flags
);
387 /* ignore all characters if CREAD is not set */
388 port
->ignore_status_mask
= (new->c_cflag
& CREAD
) ? 0 : RP2_DUMMY_READ
;
390 __rp2_uart_set_termios(up
, new->c_cflag
, new->c_iflag
, baud_div
);
391 uart_update_timeout(port
, new->c_cflag
, baud
);
393 uart_port_unlock_irqrestore(port
, flags
);
396 static void rp2_rx_chars(struct rp2_uart_port
*up
)
398 u16 bytes
= readw(up
->base
+ RP2_RX_FIFO_COUNT
);
399 struct tty_port
*port
= &up
->port
.state
->port
;
401 for (; bytes
!= 0; bytes
--) {
402 u32 byte
= readw(up
->base
+ RP2_DATA_BYTE
) | RP2_DUMMY_READ
;
405 if (likely(!(byte
& RP2_DATA_BYTE_EXCEPTION_MASK
))) {
406 if (!uart_handle_sysrq_char(&up
->port
, ch
))
407 uart_insert_char(&up
->port
, byte
, 0, ch
,
410 u8 flag
= TTY_NORMAL
;
412 if (byte
& RP2_DATA_BYTE_BREAK_m
)
414 else if (byte
& RP2_DATA_BYTE_ERR_FRAMING_m
)
416 else if (byte
& RP2_DATA_BYTE_ERR_PARITY_m
)
418 uart_insert_char(&up
->port
, byte
,
419 RP2_DATA_BYTE_ERR_OVERRUN_m
, ch
, flag
);
421 up
->port
.icount
.rx
++;
424 tty_flip_buffer_push(port
);
427 static void rp2_tx_chars(struct rp2_uart_port
*up
)
431 uart_port_tx_limited(&up
->port
, ch
,
432 FIFO_SIZE
- readw(up
->base
+ RP2_TX_FIFO_COUNT
),
434 writeb(ch
, up
->base
+ RP2_DATA_BYTE
),
438 static void rp2_ch_interrupt(struct rp2_uart_port
*up
)
442 uart_port_lock(&up
->port
);
445 * The IRQ status bits are clear-on-write. Other status bits in
446 * this register aren't, so it's harmless to write to them.
448 status
= readl(up
->base
+ RP2_CHAN_STAT
);
449 writel(status
, up
->base
+ RP2_CHAN_STAT
);
451 if (status
& RP2_CHAN_STAT_RXDATA_m
)
453 if (status
& RP2_CHAN_STAT_TXEMPTY_m
)
455 if (status
& RP2_CHAN_STAT_MS_CHANGED_MASK
)
456 wake_up_interruptible(&up
->port
.state
->port
.delta_msr_wait
);
458 uart_port_unlock(&up
->port
);
461 static int rp2_asic_interrupt(struct rp2_card
*card
, unsigned int asic_id
)
463 void __iomem
*base
= card
->bar1
+ RP2_ASIC_OFFSET(asic_id
);
465 unsigned long status
= readl(base
+ RP2_CH_IRQ_STAT
) &
466 ~readl(base
+ RP2_CH_IRQ_MASK
);
468 for_each_set_bit(ch
, &status
, PORTS_PER_ASIC
) {
469 rp2_ch_interrupt(&card
->ports
[ch
]);
475 static irqreturn_t
rp2_uart_interrupt(int irq
, void *dev_id
)
477 struct rp2_card
*card
= dev_id
;
480 handled
= rp2_asic_interrupt(card
, 0);
481 if (card
->n_ports
>= PORTS_PER_ASIC
)
482 handled
+= rp2_asic_interrupt(card
, 1);
484 return handled
? IRQ_HANDLED
: IRQ_NONE
;
487 static inline void rp2_flush_fifos(struct rp2_uart_port
*up
)
489 rp2_rmw_set(up
, RP2_UART_CTL
,
490 RP2_UART_CTL_FLUSH_RX_m
| RP2_UART_CTL_FLUSH_TX_m
);
491 readl(up
->base
+ RP2_UART_CTL
);
493 rp2_rmw_clr(up
, RP2_UART_CTL
,
494 RP2_UART_CTL_FLUSH_RX_m
| RP2_UART_CTL_FLUSH_TX_m
);
497 static int rp2_uart_startup(struct uart_port
*port
)
499 struct rp2_uart_port
*up
= port_to_up(port
);
502 rp2_rmw(up
, RP2_TXRX_CTL
, RP2_TXRX_CTL_MSRIRQ_m
, RP2_TXRX_CTL_RXIRQ_m
);
503 rp2_rmw(up
, RP2_TXRX_CTL
, RP2_TXRX_CTL_RX_TRIG_m
,
504 RP2_TXRX_CTL_RX_TRIG_1
);
505 rp2_rmw(up
, RP2_CHAN_STAT
, 0, 0);
506 rp2_mask_ch_irq(up
, up
->idx
, 1);
511 static void rp2_uart_shutdown(struct uart_port
*port
)
513 struct rp2_uart_port
*up
= port_to_up(port
);
516 rp2_uart_break_ctl(port
, 0);
518 uart_port_lock_irqsave(port
, &flags
);
519 rp2_mask_ch_irq(up
, up
->idx
, 0);
520 rp2_rmw(up
, RP2_CHAN_STAT
, 0, 0);
521 uart_port_unlock_irqrestore(port
, flags
);
524 static const char *rp2_uart_type(struct uart_port
*port
)
526 return (port
->type
== PORT_RP2
) ? "RocketPort 2 UART" : NULL
;
529 static void rp2_uart_release_port(struct uart_port
*port
)
531 /* Nothing to release ... */
534 static int rp2_uart_request_port(struct uart_port
*port
)
536 /* UARTs always present */
540 static void rp2_uart_config_port(struct uart_port
*port
, int flags
)
542 if (flags
& UART_CONFIG_TYPE
)
543 port
->type
= PORT_RP2
;
546 static int rp2_uart_verify_port(struct uart_port
*port
,
547 struct serial_struct
*ser
)
549 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_RP2
)
555 static const struct uart_ops rp2_uart_ops
= {
556 .tx_empty
= rp2_uart_tx_empty
,
557 .set_mctrl
= rp2_uart_set_mctrl
,
558 .get_mctrl
= rp2_uart_get_mctrl
,
559 .stop_tx
= rp2_uart_stop_tx
,
560 .start_tx
= rp2_uart_start_tx
,
561 .stop_rx
= rp2_uart_stop_rx
,
562 .enable_ms
= rp2_uart_enable_ms
,
563 .break_ctl
= rp2_uart_break_ctl
,
564 .startup
= rp2_uart_startup
,
565 .shutdown
= rp2_uart_shutdown
,
566 .set_termios
= rp2_uart_set_termios
,
567 .type
= rp2_uart_type
,
568 .release_port
= rp2_uart_release_port
,
569 .request_port
= rp2_uart_request_port
,
570 .config_port
= rp2_uart_config_port
,
571 .verify_port
= rp2_uart_verify_port
,
574 static void rp2_reset_asic(struct rp2_card
*card
, unsigned int asic_id
)
576 void __iomem
*base
= card
->bar1
+ RP2_ASIC_OFFSET(asic_id
);
579 writew(1, base
+ RP2_GLOBAL_CMD
);
581 readw(base
+ RP2_GLOBAL_CMD
);
582 writel(0, base
+ RP2_CLK_PRESCALER
);
584 /* TDM clock configuration */
585 clk_cfg
= readw(base
+ RP2_ASIC_CFG
);
586 clk_cfg
= (clk_cfg
& ~BIT(8)) | BIT(9);
587 writew(clk_cfg
, base
+ RP2_ASIC_CFG
);
590 writel(ALL_PORTS_MASK
, base
+ RP2_CH_IRQ_MASK
);
591 writel(RP2_ASIC_IRQ_EN_m
, base
+ RP2_ASIC_IRQ
);
594 static void rp2_init_card(struct rp2_card
*card
)
596 writel(4, card
->bar0
+ RP2_FPGA_CTL0
);
597 writel(0, card
->bar0
+ RP2_FPGA_CTL1
);
599 rp2_reset_asic(card
, 0);
600 if (card
->n_ports
>= PORTS_PER_ASIC
)
601 rp2_reset_asic(card
, 1);
603 writel(RP2_IRQ_MASK_EN_m
, card
->bar0
+ RP2_IRQ_MASK
);
606 static void rp2_init_port(struct rp2_uart_port
*up
, const struct firmware
*fw
)
610 writel(RP2_UART_CTL_RESET_CH_m
, up
->base
+ RP2_UART_CTL
);
611 readl(up
->base
+ RP2_UART_CTL
);
614 writel(0, up
->base
+ RP2_TXRX_CTL
);
615 writel(0, up
->base
+ RP2_UART_CTL
);
616 readl(up
->base
+ RP2_UART_CTL
);
621 for (i
= 0; i
< min_t(int, fw
->size
, RP2_UCODE_BYTES
); i
++)
622 writeb(fw
->data
[i
], up
->ucode
+ i
);
624 __rp2_uart_set_termios(up
, CS8
| CREAD
| CLOCAL
, 0, DEFAULT_BAUD_DIV
);
625 rp2_uart_set_mctrl(&up
->port
, 0);
627 writeb(RP2_RX_FIFO_ena
, up
->ucode
+ RP2_RX_FIFO
);
628 rp2_rmw(up
, RP2_UART_CTL
, RP2_UART_CTL_MODE_m
,
629 RP2_UART_CTL_XMIT_EN_m
| RP2_UART_CTL_MODE_rs232
);
630 rp2_rmw_set(up
, RP2_TXRX_CTL
,
631 RP2_TXRX_CTL_TX_EN_m
| RP2_TXRX_CTL_RX_EN_m
);
634 static void rp2_remove_ports(struct rp2_card
*card
)
638 for (i
= 0; i
< card
->initialized_ports
; i
++)
639 uart_remove_one_port(&rp2_uart_driver
, &card
->ports
[i
].port
);
640 card
->initialized_ports
= 0;
643 static int rp2_load_firmware(struct rp2_card
*card
, const struct firmware
*fw
)
645 resource_size_t phys_base
;
648 phys_base
= pci_resource_start(card
->pdev
, 1);
650 for (i
= 0; i
< card
->n_ports
; i
++) {
651 struct rp2_uart_port
*rp
= &card
->ports
[i
];
653 int j
= (unsigned)i
% PORTS_PER_ASIC
;
655 rp
->asic_base
= card
->bar1
;
656 rp
->base
= card
->bar1
+ RP2_PORT_BASE
+ j
*RP2_PORT_SPACING
;
657 rp
->ucode
= card
->bar1
+ RP2_UCODE_BASE
+ j
*RP2_UCODE_SPACING
;
662 p
->line
= card
->minor_start
+ i
;
663 p
->dev
= &card
->pdev
->dev
;
665 p
->iotype
= UPIO_MEM32
;
666 p
->uartclk
= UART_CLOCK
;
668 p
->fifosize
= FIFO_SIZE
;
669 p
->ops
= &rp2_uart_ops
;
670 p
->irq
= card
->pdev
->irq
;
671 p
->membase
= rp
->base
;
672 p
->mapbase
= phys_base
+ RP2_PORT_BASE
+ j
*RP2_PORT_SPACING
;
674 if (i
>= PORTS_PER_ASIC
) {
675 rp
->asic_base
+= RP2_ASIC_SPACING
;
676 rp
->base
+= RP2_ASIC_SPACING
;
677 rp
->ucode
+= RP2_ASIC_SPACING
;
678 p
->mapbase
+= RP2_ASIC_SPACING
;
681 rp2_init_port(rp
, fw
);
682 rc
= uart_add_one_port(&rp2_uart_driver
, p
);
684 dev_err(&card
->pdev
->dev
,
685 "error registering port %d: %d\n", i
, rc
);
686 rp2_remove_ports(card
);
689 card
->initialized_ports
++;
695 static int rp2_probe(struct pci_dev
*pdev
,
696 const struct pci_device_id
*id
)
698 const struct firmware
*fw
;
699 struct rp2_card
*card
;
700 struct rp2_uart_port
*ports
;
703 card
= devm_kzalloc(&pdev
->dev
, sizeof(*card
), GFP_KERNEL
);
706 pci_set_drvdata(pdev
, card
);
707 spin_lock_init(&card
->card_lock
);
709 rc
= pcim_enable_device(pdev
);
713 rc
= pcim_request_all_regions(pdev
, DRV_NAME
);
717 card
->bar0
= pcim_iomap(pdev
, 0, 0);
720 card
->bar1
= pcim_iomap(pdev
, 1, 0);
725 rp2_decode_cap(id
, &card
->n_ports
, &card
->smpte
);
726 dev_info(&pdev
->dev
, "found new card with %d ports\n", card
->n_ports
);
728 card
->minor_start
= rp2_alloc_ports(card
->n_ports
);
729 if (card
->minor_start
< 0) {
731 "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
737 ports
= devm_kcalloc(&pdev
->dev
, card
->n_ports
, sizeof(*ports
),
743 rc
= request_firmware(&fw
, RP2_FW_NAME
, &pdev
->dev
);
745 dev_err(&pdev
->dev
, "cannot find '%s' firmware image\n",
750 rc
= rp2_load_firmware(card
, fw
);
752 release_firmware(fw
);
756 rc
= devm_request_irq(&pdev
->dev
, pdev
->irq
, rp2_uart_interrupt
,
757 IRQF_SHARED
, DRV_NAME
, card
);
764 static void rp2_remove(struct pci_dev
*pdev
)
766 struct rp2_card
*card
= pci_get_drvdata(pdev
);
768 rp2_remove_ports(card
);
771 static const struct pci_device_id rp2_pci_tbl
[] = {
773 /* RocketPort INFINITY cards */
775 { RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */
776 { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */
777 { RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */
778 { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */
779 { RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */
780 { RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */
781 { RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */
782 { RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */
783 { RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */
784 { RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */
785 { RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */
786 { RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */
787 { RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */
788 { RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */
789 { RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */
790 { RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */
791 { RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */
793 /* RocketPort EXPRESS cards */
795 { RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */
796 { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */
797 { RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */
798 { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */
799 { RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */
800 { RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */
801 { RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */
802 { RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */
803 { RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */
804 { RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */
807 MODULE_DEVICE_TABLE(pci
, rp2_pci_tbl
);
809 static struct pci_driver rp2_pci_driver
= {
811 .id_table
= rp2_pci_tbl
,
813 .remove
= rp2_remove
,
816 static int __init
rp2_uart_init(void)
820 rc
= uart_register_driver(&rp2_uart_driver
);
824 rc
= pci_register_driver(&rp2_pci_driver
);
826 uart_unregister_driver(&rp2_uart_driver
);
833 static void __exit
rp2_uart_exit(void)
835 pci_unregister_driver(&rp2_pci_driver
);
836 uart_unregister_driver(&rp2_uart_driver
);
839 module_init(rp2_uart_init
);
840 module_exit(rp2_uart_exit
);
842 MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
843 MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>");
844 MODULE_LICENSE("GPL v2");
845 MODULE_FIRMWARE(RP2_FW_NAME
);