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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / video / fbdev / arkfb.c
blob082501feceb96a118df3b0f9e25f04d3708ebc7a
1 /*
2 * linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV
3 * with ICS 5342 dac (it is easy to add support for different dacs).
4 *
5 * Copyright (c) 2007 Ondrej Zajicek <santiago@crfreenet.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * Code is based on s3fb
12 */
13
14 #include <linux/aperture.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/fb.h>
24 #include <linux/svga.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
28 #include <video/vga.h>
29
30 struct arkfb_info {
31 int mclk_freq;
32 int wc_cookie;
33
34 struct dac_info *dac;
35 struct vgastate state;
36 struct mutex open_lock;
37 unsigned int ref_count;
38 u32 pseudo_palette[16];
39 };
40
41
42 /* ------------------------------------------------------------------------- */
43
44
45 static const struct svga_fb_format arkfb_formats[] = {
46 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
47 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 8},
48 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
49 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
50 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
51 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
52 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
53 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
54 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
55 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
56 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
58 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
59 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 8, 8},
60 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
62 SVGA_FORMAT_END
63 };
64
65
66 /* CRT timing register sets */
67
68 static const struct vga_regset ark_h_total_regs[] = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END};
69 static const struct vga_regset ark_h_display_regs[] = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END};
70 static const struct vga_regset ark_h_blank_start_regs[] = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END};
71 static const struct vga_regset ark_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7 }, VGA_REGSET_END};
72 static const struct vga_regset ark_h_sync_start_regs[] = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END};
73 static const struct vga_regset ark_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
74
75 static const struct vga_regset ark_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END};
76 static const struct vga_regset ark_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END};
77 static const struct vga_regset ark_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END};
78 // const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 6}, VGA_REGSET_END};
79 static const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
80 static const struct vga_regset ark_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END};
81 static const struct vga_regset ark_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
82
83 static const struct vga_regset ark_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END};
84 static const struct vga_regset ark_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END};
85 static const struct vga_regset ark_offset_regs[] = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END};
86
87 static const struct svga_timing_regs ark_timing_regs = {
88 ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs,
89 ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs,
90 ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs,
91 ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs,
92 };
93
94
95 /* ------------------------------------------------------------------------- */
96
97
98 /* Module parameters */
99
100 static char *mode_option = "640x480-8@60";
101
102 MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <santiago@crfreenet.org>");
103 MODULE_LICENSE("GPL");
104 MODULE_DESCRIPTION("fbdev driver for ARK 2000PV");
105
106 module_param(mode_option, charp, 0444);
107 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
108 module_param_named(mode, mode_option, charp, 0444);
109 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
110
111 static int threshold = 4;
112
113 module_param(threshold, int, 0644);
114 MODULE_PARM_DESC(threshold, "FIFO threshold");
115
116
117 /* ------------------------------------------------------------------------- */
118
119
120 static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
121 {
122 const u8 *font = map->data;
123 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
124 int i, c;
125
126 if ((map->width != 8) || (map->height != 16) ||
127 (map->depth != 1) || (map->length != 256)) {
128 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
129 map->width, map->height, map->depth, map->length);
130 return;
131 }
132
133 fb += 2;
134 for (c = 0; c < map->length; c++) {
135 for (i = 0; i < map->height; i++) {
136 fb_writeb(font[i], &fb[i * 4]);
137 fb_writeb(font[i], &fb[i * 4 + (128 * 8)]);
138 }
139 fb += 128;
140
141 if ((c % 8) == 7)
142 fb += 128*8;
143
144 font += map->height;
145 }
146 }
147
148 static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
149 {
150 struct arkfb_info *par = info->par;
151
152 svga_tilecursor(par->state.vgabase, info, cursor);
153 }
154
155 static struct fb_tile_ops arkfb_tile_ops = {
156 .fb_settile = arkfb_settile,
157 .fb_tilecopy = svga_tilecopy,
158 .fb_tilefill = svga_tilefill,
159 .fb_tileblit = svga_tileblit,
160 .fb_tilecursor = arkfb_tilecursor,
161 .fb_get_tilemax = svga_get_tilemax,
162 };
163
164
165 /* ------------------------------------------------------------------------- */
166
167
168 /* image data is MSB-first, fb structure is MSB-first too */
169 static inline u32 expand_color(u32 c)
170 {
171 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
172 }
173
174 /* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
175 static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
176 {
177 u32 fg = expand_color(image->fg_color);
178 u32 bg = expand_color(image->bg_color);
179 const u8 *src1, *src;
180 u8 __iomem *dst1;
181 u32 __iomem *dst;
182 u32 val;
183 int x, y;
184
185 src1 = image->data;
186 dst1 = info->screen_base + (image->dy * info->fix.line_length)
187 + ((image->dx / 8) * 4);
188
189 for (y = 0; y < image->height; y++) {
190 src = src1;
191 dst = (u32 __iomem *) dst1;
192 for (x = 0; x < image->width; x += 8) {
193 val = *(src++) * 0x01010101;
194 val = (val & fg) | (~val & bg);
195 fb_writel(val, dst++);
196 }
197 src1 += image->width / 8;
198 dst1 += info->fix.line_length;
199 }
200
201 }
202
203 /* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
204 static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
205 {
206 u32 fg = expand_color(rect->color);
207 u8 __iomem *dst1;
208 u32 __iomem *dst;
209 int x, y;
210
211 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
212 + ((rect->dx / 8) * 4);
213
214 for (y = 0; y < rect->height; y++) {
215 dst = (u32 __iomem *) dst1;
216 for (x = 0; x < rect->width; x += 8) {
217 fb_writel(fg, dst++);
218 }
219 dst1 += info->fix.line_length;
220 }
221
222 }
223
224
225 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
226 static inline u32 expand_pixel(u32 c)
227 {
228 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
229 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
230 }
231
232 /* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
233 static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
234 {
235 u32 fg = image->fg_color * 0x11111111;
236 u32 bg = image->bg_color * 0x11111111;
237 const u8 *src1, *src;
238 u8 __iomem *dst1;
239 u32 __iomem *dst;
240 u32 val;
241 int x, y;
242
243 src1 = image->data;
244 dst1 = info->screen_base + (image->dy * info->fix.line_length)
245 + ((image->dx / 8) * 4);
246
247 for (y = 0; y < image->height; y++) {
248 src = src1;
249 dst = (u32 __iomem *) dst1;
250 for (x = 0; x < image->width; x += 8) {
251 val = expand_pixel(*(src++));
252 val = (val & fg) | (~val & bg);
253 fb_writel(val, dst++);
254 }
255 src1 += image->width / 8;
256 dst1 += info->fix.line_length;
257 }
258
259 }
260
261 static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image)
262 {
263 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
264 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
265 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
266 arkfb_iplan_imageblit(info, image);
267 else
268 arkfb_cfb4_imageblit(info, image);
269 } else
270 cfb_imageblit(info, image);
271 }
272
273 static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
274 {
275 if ((info->var.bits_per_pixel == 4)
276 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
277 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
278 arkfb_iplan_fillrect(info, rect);
279 else
280 cfb_fillrect(info, rect);
281 }
282
283
284 /* ------------------------------------------------------------------------- */
285
286
287 enum
288 {
289 DAC_PSEUDO8_8,
290 DAC_RGB1555_8,
291 DAC_RGB0565_8,
292 DAC_RGB0888_8,
293 DAC_RGB8888_8,
294 DAC_PSEUDO8_16,
295 DAC_RGB1555_16,
296 DAC_RGB0565_16,
297 DAC_RGB0888_16,
298 DAC_RGB8888_16,
299 DAC_MAX
300 };
301
302 struct dac_ops {
303 int (*dac_get_mode)(struct dac_info *info);
304 int (*dac_set_mode)(struct dac_info *info, int mode);
305 int (*dac_get_freq)(struct dac_info *info, int channel);
306 int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq);
307 void (*dac_release)(struct dac_info *info);
308 };
309
310 typedef void (*dac_read_regs_t)(void *data, u8 *code, int count);
311 typedef void (*dac_write_regs_t)(void *data, u8 *code, int count);
312
313 struct dac_info
314 {
315 struct dac_ops *dacops;
316 dac_read_regs_t dac_read_regs;
317 dac_write_regs_t dac_write_regs;
318 void *data;
319 };
320
321 static inline void dac_read_regs(struct dac_info *info, u8 *code, int count)
322 {
323 info->dac_read_regs(info->data, code, count);
324 }
325
326 static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val)
327 {
328 u8 code[2] = {reg, val};
329 info->dac_write_regs(info->data, code, 1);
330 }
331
332 static inline void dac_write_regs(struct dac_info *info, u8 *code, int count)
333 {
334 info->dac_write_regs(info->data, code, count);
335 }
336
337 static inline int dac_set_mode(struct dac_info *info, int mode)
338 {
339 return info->dacops->dac_set_mode(info, mode);
340 }
341
342 static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq)
343 {
344 return info->dacops->dac_set_freq(info, channel, freq);
345 }
346
347 static inline void dac_release(struct dac_info *info)
348 {
349 info->dacops->dac_release(info);
350 }
351
352
353 /* ------------------------------------------------------------------------- */
354
355
356 /* ICS5342 DAC */
357
358 struct ics5342_info
359 {
360 struct dac_info dac;
361 u8 mode;
362 };
363
364 #define DAC_PAR(info) ((struct ics5342_info *) info)
365
366 /* LSB is set to distinguish unused slots */
367 static const u8 ics5342_mode_table[DAC_MAX] = {
368 [DAC_PSEUDO8_8] = 0x01, [DAC_RGB1555_8] = 0x21, [DAC_RGB0565_8] = 0x61,
369 [DAC_RGB0888_8] = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31,
370 [DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71
371 };
372
373 static int ics5342_set_mode(struct dac_info *info, int mode)
374 {
375 u8 code;
376
377 if (mode >= DAC_MAX)
378 return -EINVAL;
379
380 code = ics5342_mode_table[mode];
381
382 if (! code)
383 return -EINVAL;
384
385 dac_write_reg(info, 6, code & 0xF0);
386 DAC_PAR(info)->mode = mode;
387
388 return 0;
389 }
390
391 static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3,
392 60000, 250000, 14318};
393
394 /* pd4 - allow only posdivider 4 (r=2) */
395 static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2,
396 60000, 335000, 14318};
397
398 /* 270 MHz should be upper bound for VCO clock according to specs,
399 but that is too restrictive in pd4 case */
400
401 static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq)
402 {
403 u16 m, n, r;
404
405 /* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */
406 int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16)
407 ? &ics5342_pll_pd4 : &ics5342_pll,
408 freq, &m, &n, &r, 0);
409
410 if (rv < 0) {
411 return -EINVAL;
412 } else {
413 u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)};
414 dac_write_regs(info, code, 3);
415 return 0;
416 }
417 }
418
419 static void ics5342_release(struct dac_info *info)
420 {
421 ics5342_set_mode(info, DAC_PSEUDO8_8);
422 kfree(info);
423 }
424
425 static struct dac_ops ics5342_ops = {
426 .dac_set_mode = ics5342_set_mode,
427 .dac_set_freq = ics5342_set_freq,
428 .dac_release = ics5342_release
429 };
430
431
432 static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data)
433 {
434 struct dac_info *info = kzalloc(sizeof(struct ics5342_info), GFP_KERNEL);
435
436 if (! info)
437 return NULL;
438
439 info->dacops = &ics5342_ops;
440 info->dac_read_regs = drr;
441 info->dac_write_regs = dwr;
442 info->data = data;
443 DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */
444 return info;
445 }
446
447
448 /* ------------------------------------------------------------------------- */
449
450
451 static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
452
453 static void ark_dac_read_regs(void *data, u8 *code, int count)
454 {
455 struct fb_info *info = data;
456 struct arkfb_info *par;
457 u8 regval;
458
459 par = info->par;
460 regval = vga_rseq(par->state.vgabase, 0x1C);
461 while (count != 0)
462 {
463 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
464 code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]);
465 count--;
466 code += 2;
467 }
468
469 vga_wseq(par->state.vgabase, 0x1C, regval);
470 }
471
472 static void ark_dac_write_regs(void *data, u8 *code, int count)
473 {
474 struct fb_info *info = data;
475 struct arkfb_info *par;
476 u8 regval;
477
478 par = info->par;
479 regval = vga_rseq(par->state.vgabase, 0x1C);
480 while (count != 0)
481 {
482 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
483 vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]);
484 count--;
485 code += 2;
486 }
487
488 vga_wseq(par->state.vgabase, 0x1C, regval);
489 }
490
491
492 static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
493 {
494 struct arkfb_info *par = info->par;
495 u8 regval;
496
497 int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock);
498 if (rv < 0) {
499 fb_err(info, "cannot set requested pixclock, keeping old value\n");
500 return;
501 }
502
503 /* Set VGA misc register */
504 regval = vga_r(par->state.vgabase, VGA_MIS_R);
505 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
506 }
507
508
509 /* Open framebuffer */
510
511 static int arkfb_open(struct fb_info *info, int user)
512 {
513 struct arkfb_info *par = info->par;
514
515 mutex_lock(&(par->open_lock));
516 if (par->ref_count == 0) {
517 void __iomem *vgabase = par->state.vgabase;
518
519 memset(&(par->state), 0, sizeof(struct vgastate));
520 par->state.vgabase = vgabase;
521 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
522 par->state.num_crtc = 0x60;
523 par->state.num_seq = 0x30;
524 save_vga(&(par->state));
525 }
526
527 par->ref_count++;
528 mutex_unlock(&(par->open_lock));
529
530 return 0;
531 }
532
533 /* Close framebuffer */
534
535 static int arkfb_release(struct fb_info *info, int user)
536 {
537 struct arkfb_info *par = info->par;
538
539 mutex_lock(&(par->open_lock));
540 if (par->ref_count == 0) {
541 mutex_unlock(&(par->open_lock));
542 return -EINVAL;
543 }
544
545 if (par->ref_count == 1) {
546 restore_vga(&(par->state));
547 dac_set_mode(par->dac, DAC_PSEUDO8_8);
548 }
549
550 par->ref_count--;
551 mutex_unlock(&(par->open_lock));
552
553 return 0;
554 }
555
556 /* Validate passed in var */
557
558 static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
559 {
560 int rv, mem, step;
561
562 if (!var->pixclock)
563 return -EINVAL;
564
565 /* Find appropriate format */
566 rv = svga_match_format (arkfb_formats, var, NULL);
567 if (rv < 0)
568 {
569 fb_err(info, "unsupported mode requested\n");
570 return rv;
571 }
572
573 /* Do not allow to have real resoulution larger than virtual */
574 if (var->xres > var->xres_virtual)
575 var->xres_virtual = var->xres;
576
577 if (var->yres > var->yres_virtual)
578 var->yres_virtual = var->yres;
579
580 /* Round up xres_virtual to have proper alignment of lines */
581 step = arkfb_formats[rv].xresstep - 1;
582 var->xres_virtual = (var->xres_virtual+step) & ~step;
583
584
585 /* Check whether have enough memory */
586 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
587 if (mem > info->screen_size)
588 {
589 fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n",
590 mem >> 10, (unsigned int) (info->screen_size >> 10));
591 return -EINVAL;
592 }
593
594 rv = svga_check_timings (&ark_timing_regs, var, info->node);
595 if (rv < 0)
596 {
597 fb_err(info, "invalid timings requested\n");
598 return rv;
599 }
600
601 /* Interlaced mode is broken */
602 if (var->vmode & FB_VMODE_INTERLACED)
603 return -EINVAL;
604
605 return 0;
606 }
607
608 /* Set video mode from par */
609
610 static int arkfb_set_par(struct fb_info *info)
611 {
612 struct arkfb_info *par = info->par;
613 u32 value, mode, hmul, hdiv, offset_value, screen_size;
614 u32 bpp = info->var.bits_per_pixel;
615 u8 regval;
616
617 if (bpp != 0) {
618 info->fix.ypanstep = 1;
619 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
620
621 info->flags &= ~FBINFO_MISC_TILEBLITTING;
622 info->tileops = NULL;
623
624 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
625 if (bpp == 4) {
626 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH);
627 set_bit(8 - 1, info->pixmap.blit_x);
628 } else {
629 bitmap_fill(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH);
630 }
631 bitmap_fill(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT);
632
633 offset_value = (info->var.xres_virtual * bpp) / 64;
634 screen_size = info->var.yres_virtual * info->fix.line_length;
635 } else {
636 info->fix.ypanstep = 16;
637 info->fix.line_length = 0;
638
639 info->flags |= FBINFO_MISC_TILEBLITTING;
640 info->tileops = &arkfb_tile_ops;
641
642 /* supports 8x16 tiles only */
643 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH);
644 set_bit(8 - 1, info->pixmap.blit_x);
645 bitmap_zero(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT);
646 set_bit(16 - 1, info->pixmap.blit_y);
647
648 offset_value = info->var.xres_virtual / 16;
649 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
650 }
651
652 info->var.xoffset = 0;
653 info->var.yoffset = 0;
654 info->var.activate = FB_ACTIVATE_NOW;
655
656 /* Unlock registers */
657 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
658
659 /* Blank screen and turn off sync */
660 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
661 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
662
663 /* Set default values */
664 svga_set_default_gfx_regs(par->state.vgabase);
665 svga_set_default_atc_regs(par->state.vgabase);
666 svga_set_default_seq_regs(par->state.vgabase);
667 svga_set_default_crt_regs(par->state.vgabase);
668 svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF);
669 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
670
671 /* ARK specific initialization */
672 svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
673 svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
674
675 vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16);
676 vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24);
677 vga_wseq(par->state.vgabase, 0x15, 0);
678 vga_wseq(par->state.vgabase, 0x16, 0);
679
680 /* Set the FIFO threshold register */
681 /* It is fascinating way to store 5-bit value in 8-bit register */
682 regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
683 vga_wseq(par->state.vgabase, 0x18, regval);
684
685 /* Set the offset register */
686 fb_dbg(info, "offset register : %d\n", offset_value);
687 svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value);
688
689 /* fix for hi-res textmode */
690 svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08);
691
692 if (info->var.vmode & FB_VMODE_DOUBLE)
693 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
694 else
695 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
696
697 if (info->var.vmode & FB_VMODE_INTERLACED)
698 svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04);
699 else
700 svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04);
701
702 hmul = 1;
703 hdiv = 1;
704 mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix));
705
706 /* Set mode-specific register values */
707 switch (mode) {
708 case 0:
709 fb_dbg(info, "text mode\n");
710 svga_set_textmode_vga_regs(par->state.vgabase);
711
712 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
713 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
714 dac_set_mode(par->dac, DAC_PSEUDO8_8);
715
716 break;
717 case 1:
718 fb_dbg(info, "4 bit pseudocolor\n");
719 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
720
721 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
722 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
723 dac_set_mode(par->dac, DAC_PSEUDO8_8);
724 break;
725 case 2:
726 fb_dbg(info, "4 bit pseudocolor, planar\n");
727
728 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
729 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
730 dac_set_mode(par->dac, DAC_PSEUDO8_8);
731 break;
732 case 3:
733 fb_dbg(info, "8 bit pseudocolor\n");
734
735 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */
736
737 if (info->var.pixclock > 20000) {
738 fb_dbg(info, "not using multiplex\n");
739 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
740 dac_set_mode(par->dac, DAC_PSEUDO8_8);
741 } else {
742 fb_dbg(info, "using multiplex\n");
743 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
744 dac_set_mode(par->dac, DAC_PSEUDO8_16);
745 hdiv = 2;
746 }
747 break;
748 case 4:
749 fb_dbg(info, "5/5/5 truecolor\n");
750
751 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
752 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
753 dac_set_mode(par->dac, DAC_RGB1555_16);
754 break;
755 case 5:
756 fb_dbg(info, "5/6/5 truecolor\n");
757
758 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
759 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
760 dac_set_mode(par->dac, DAC_RGB0565_16);
761 break;
762 case 6:
763 fb_dbg(info, "8/8/8 truecolor\n");
764
765 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */
766 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
767 dac_set_mode(par->dac, DAC_RGB0888_16);
768 hmul = 3;
769 hdiv = 2;
770 break;
771 case 7:
772 fb_dbg(info, "8/8/8/8 truecolor\n");
773
774 vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */
775 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
776 dac_set_mode(par->dac, DAC_RGB8888_16);
777 hmul = 2;
778 break;
779 default:
780 fb_err(info, "unsupported mode - bug\n");
781 return -EINVAL;
782 }
783
784 value = (hdiv * info->var.pixclock) / hmul;
785 if (!value) {
786 fb_dbg(info, "invalid pixclock\n");
787 value = 1;
788 }
789 ark_set_pixclock(info, value);
790 svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
791 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
792 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
793 hmul, info->node);
794
795 /* Set interlaced mode start/end register */
796 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
797 value = ((value * hmul / hdiv) / 8) - 5;
798 vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2);
799
800 if (screen_size > info->screen_size)
801 screen_size = info->screen_size;
802 memset_io(info->screen_base, 0x00, screen_size);
803 /* Device and screen back on */
804 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
805 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
806
807 return 0;
808 }
809
810 /* Set a colour register */
811
812 static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
813 u_int transp, struct fb_info *fb)
814 {
815 switch (fb->var.bits_per_pixel) {
816 case 0:
817 case 4:
818 if (regno >= 16)
819 return -EINVAL;
820
821 if ((fb->var.bits_per_pixel == 4) &&
822 (fb->var.nonstd == 0)) {
823 outb(0xF0, VGA_PEL_MSK);
824 outb(regno*16, VGA_PEL_IW);
825 } else {
826 outb(0x0F, VGA_PEL_MSK);
827 outb(regno, VGA_PEL_IW);
828 }
829 outb(red >> 10, VGA_PEL_D);
830 outb(green >> 10, VGA_PEL_D);
831 outb(blue >> 10, VGA_PEL_D);
832 break;
833 case 8:
834 if (regno >= 256)
835 return -EINVAL;
836
837 outb(0xFF, VGA_PEL_MSK);
838 outb(regno, VGA_PEL_IW);
839 outb(red >> 10, VGA_PEL_D);
840 outb(green >> 10, VGA_PEL_D);
841 outb(blue >> 10, VGA_PEL_D);
842 break;
843 case 16:
844 if (regno >= 16)
845 return 0;
846
847 if (fb->var.green.length == 5)
848 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
849 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
850 else if (fb->var.green.length == 6)
851 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
852 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
853 else
854 return -EINVAL;
855 break;
856 case 24:
857 case 32:
858 if (regno >= 16)
859 return 0;
860
861 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
862 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
863 break;
864 default:
865 return -EINVAL;
866 }
867
868 return 0;
869 }
870
871 /* Set the display blanking state */
872
873 static int arkfb_blank(int blank_mode, struct fb_info *info)
874 {
875 struct arkfb_info *par = info->par;
876
877 switch (blank_mode) {
878 case FB_BLANK_UNBLANK:
879 fb_dbg(info, "unblank\n");
880 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
881 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
882 break;
883 case FB_BLANK_NORMAL:
884 fb_dbg(info, "blank\n");
885 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
886 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
887 break;
888 case FB_BLANK_POWERDOWN:
889 case FB_BLANK_HSYNC_SUSPEND:
890 case FB_BLANK_VSYNC_SUSPEND:
891 fb_dbg(info, "sync down\n");
892 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
893 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
894 break;
895 }
896 return 0;
897 }
898
899
900 /* Pan the display */
901
902 static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
903 {
904 struct arkfb_info *par = info->par;
905 unsigned int offset;
906
907 /* Calculate the offset */
908 if (info->var.bits_per_pixel == 0) {
909 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
910 + (var->xoffset / 2);
911 offset = offset >> 2;
912 } else {
913 offset = (var->yoffset * info->fix.line_length) +
914 (var->xoffset * info->var.bits_per_pixel / 8);
915 offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 3);
916 }
917
918 /* Set the offset */
919 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset);
920
921 return 0;
922 }
923
924
925 /* ------------------------------------------------------------------------- */
926
927
928 /* Frame buffer operations */
929
930 static const struct fb_ops arkfb_ops = {
931 .owner = THIS_MODULE,
932 .fb_open = arkfb_open,
933 .fb_release = arkfb_release,
934 __FB_DEFAULT_IOMEM_OPS_RDWR,
935 .fb_check_var = arkfb_check_var,
936 .fb_set_par = arkfb_set_par,
937 .fb_setcolreg = arkfb_setcolreg,
938 .fb_blank = arkfb_blank,
939 .fb_pan_display = arkfb_pan_display,
940 .fb_fillrect = arkfb_fillrect,
941 .fb_copyarea = cfb_copyarea,
942 .fb_imageblit = arkfb_imageblit,
943 __FB_DEFAULT_IOMEM_OPS_MMAP,
944 .fb_get_caps = svga_get_caps,
945 };
946
947
948 /* ------------------------------------------------------------------------- */
949
950
951 /* PCI probe */
952 static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
953 {
954 struct pci_bus_region bus_reg;
955 struct resource vga_res;
956 struct fb_info *info;
957 struct arkfb_info *par;
958 int rc;
959 u8 regval;
960
961 rc = aperture_remove_conflicting_pci_devices(dev, "arkfb");
962 if (rc < 0)
963 return rc;
964
965 /* Ignore secondary VGA device because there is no VGA arbitration */
966 if (! svga_primary_device(dev)) {
967 dev_info(&(dev->dev), "ignoring secondary device\n");
968 return -ENODEV;
969 }
970
971 /* Allocate and fill driver data structure */
972 info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev));
973 if (!info)
974 return -ENOMEM;
975
976 par = info->par;
977 mutex_init(&par->open_lock);
978
979 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
980 info->fbops = &arkfb_ops;
981
982 /* Prepare PCI device */
983 rc = pci_enable_device(dev);
984 if (rc < 0) {
985 dev_err(info->device, "cannot enable PCI device\n");
986 goto err_enable_device;
987 }
988
989 rc = pci_request_regions(dev, "arkfb");
990 if (rc < 0) {
991 dev_err(info->device, "cannot reserve framebuffer region\n");
992 goto err_request_regions;
993 }
994
995 par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info);
996 if (! par->dac) {
997 rc = -ENOMEM;
998 dev_err(info->device, "RAMDAC initialization failed\n");
999 goto err_dac;
1000 }
1001
1002 info->fix.smem_start = pci_resource_start(dev, 0);
1003 info->fix.smem_len = pci_resource_len(dev, 0);
1004
1005 /* Map physical IO memory address into kernel space */
1006 info->screen_base = pci_iomap_wc(dev, 0, 0);
1007 if (! info->screen_base) {
1008 rc = -ENOMEM;
1009 dev_err(info->device, "iomap for framebuffer failed\n");
1010 goto err_iomap;
1011 }
1012
1013 bus_reg.start = 0;
1014 bus_reg.end = 64 * 1024;
1015
1016 vga_res.flags = IORESOURCE_IO;
1017
1018 pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
1019
1020 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1021
1022 /* FIXME get memsize */
1023 regval = vga_rseq(par->state.vgabase, 0x10);
1024 info->screen_size = (1 << (regval >> 6)) << 20;
1025 info->fix.smem_len = info->screen_size;
1026
1027 strcpy(info->fix.id, "ARK 2000PV");
1028 info->fix.mmio_start = 0;
1029 info->fix.mmio_len = 0;
1030 info->fix.type = FB_TYPE_PACKED_PIXELS;
1031 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1032 info->fix.ypanstep = 0;
1033 info->fix.accel = FB_ACCEL_NONE;
1034 info->pseudo_palette = (void*) (par->pseudo_palette);
1035
1036 /* Prepare startup mode */
1037 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
1038 if (! ((rc == 1) || (rc == 2))) {
1039 rc = -EINVAL;
1040 dev_err(info->device, "mode %s not found\n", mode_option);
1041 goto err_find_mode;
1042 }
1043
1044 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1045 if (rc < 0) {
1046 dev_err(info->device, "cannot allocate colormap\n");
1047 goto err_alloc_cmap;
1048 }
1049
1050 rc = register_framebuffer(info);
1051 if (rc < 0) {
1052 dev_err(info->device, "cannot register framebuffer\n");
1053 goto err_reg_fb;
1054 }
1055
1056 fb_info(info, "%s on %s, %d MB RAM\n",
1057 info->fix.id, pci_name(dev), info->fix.smem_len >> 20);
1058
1059 /* Record a reference to the driver data */
1060 pci_set_drvdata(dev, info);
1061 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1062 info->fix.smem_len);
1063 return 0;
1064
1065 /* Error handling */
1066 err_reg_fb:
1067 fb_dealloc_cmap(&info->cmap);
1068 err_alloc_cmap:
1069 err_find_mode:
1070 pci_iounmap(dev, info->screen_base);
1071 err_iomap:
1072 dac_release(par->dac);
1073 err_dac:
1074 pci_release_regions(dev);
1075 err_request_regions:
1076 /* pci_disable_device(dev); */
1077 err_enable_device:
1078 framebuffer_release(info);
1079 return rc;
1080 }
1081
1082 /* PCI remove */
1083
1084 static void ark_pci_remove(struct pci_dev *dev)
1085 {
1086 struct fb_info *info = pci_get_drvdata(dev);
1087
1088 if (info) {
1089 struct arkfb_info *par = info->par;
1090 arch_phys_wc_del(par->wc_cookie);
1091 dac_release(par->dac);
1092 unregister_framebuffer(info);
1093 fb_dealloc_cmap(&info->cmap);
1094
1095 pci_iounmap(dev, info->screen_base);
1096 pci_release_regions(dev);
1097 /* pci_disable_device(dev); */
1098
1099 framebuffer_release(info);
1100 }
1101 }
1102
1103
1104 /* PCI suspend */
1105
1106 static int __maybe_unused ark_pci_suspend(struct device *dev)
1107 {
1108 struct fb_info *info = dev_get_drvdata(dev);
1109 struct arkfb_info *par = info->par;
1110
1111 dev_info(info->device, "suspend\n");
1112
1113 console_lock();
1114 mutex_lock(&(par->open_lock));
1115
1116 if (par->ref_count == 0) {
1117 mutex_unlock(&(par->open_lock));
1118 console_unlock();
1119 return 0;
1120 }
1121
1122 fb_set_suspend(info, 1);
1123
1124 mutex_unlock(&(par->open_lock));
1125 console_unlock();
1126
1127 return 0;
1128 }
1129
1130
1131 /* PCI resume */
1132
1133 static int __maybe_unused ark_pci_resume(struct device *dev)
1134 {
1135 struct fb_info *info = dev_get_drvdata(dev);
1136 struct arkfb_info *par = info->par;
1137
1138 dev_info(info->device, "resume\n");
1139
1140 console_lock();
1141 mutex_lock(&(par->open_lock));
1142
1143 if (par->ref_count == 0)
1144 goto fail;
1145
1146 arkfb_set_par(info);
1147 fb_set_suspend(info, 0);
1148
1149 fail:
1150 mutex_unlock(&(par->open_lock));
1151 console_unlock();
1152 return 0;
1153 }
1154
1155 static const struct dev_pm_ops ark_pci_pm_ops = {
1156 #ifdef CONFIG_PM_SLEEP
1157 .suspend = ark_pci_suspend,
1158 .resume = ark_pci_resume,
1159 .freeze = NULL,
1160 .thaw = ark_pci_resume,
1161 .poweroff = ark_pci_suspend,
1162 .restore = ark_pci_resume,
1163 #endif
1164 };
1165
1166 /* List of boards that we are trying to support */
1167
1168 static const struct pci_device_id ark_devices[] = {
1169 {PCI_DEVICE(0xEDD8, 0xA099)},
1170 {0, 0, 0, 0, 0, 0, 0}
1171 };
1172
1173
1174 MODULE_DEVICE_TABLE(pci, ark_devices);
1175
1176 static struct pci_driver arkfb_pci_driver = {
1177 .name = "arkfb",
1178 .id_table = ark_devices,
1179 .probe = ark_pci_probe,
1180 .remove = ark_pci_remove,
1181 .driver.pm = &ark_pci_pm_ops,
1182 };
1183
1184 /* Cleanup */
1185
1186 static void __exit arkfb_cleanup(void)
1187 {
1188 pr_debug("arkfb: cleaning up\n");
1189 pci_unregister_driver(&arkfb_pci_driver);
1190 }
1191
1192 /* Driver Initialisation */
1193
1194 static int __init arkfb_init(void)
1195 {
1196
1197 #ifndef MODULE
1198 char *option = NULL;
1199 #endif
1200
1201 if (fb_modesetting_disabled("arkfb"))
1202 return -ENODEV;
1203
1204 #ifndef MODULE
1205 if (fb_get_options("arkfb", &option))
1206 return -ENODEV;
1207
1208 if (option && *option)
1209 mode_option = option;
1210 #endif
1211
1212 pr_debug("arkfb: initializing\n");
1213 return pci_register_driver(&arkfb_pci_driver);
1214 }
1215
1216 module_init(arkfb_init);
1217 module_exit(arkfb_cleanup);
Kernel DRM miscellaneous fixes and cross-tree changes