| blob | d115c741c255e79c2f6074696c5414a299daa43c |
1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2 /*
3 * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
4 * Author: Chuan Liu <chuan.liu@amlogic.com>
5 */
7 #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
8 #define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
10 #define CLKID_RTC_XTAL_CLKIN 0
11 #define CLKID_RTC_32K_DIV 1
12 #define CLKID_RTC_32K_MUX 2
13 #define CLKID_RTC_32K 3
14 #define CLKID_RTC_CLK 4
15 #define CLKID_SYS_RESET_CTRL 5
16 #define CLKID_SYS_PWR_CTRL 6
17 #define CLKID_SYS_PAD_CTRL 7
18 #define CLKID_SYS_CTRL 8
19 #define CLKID_SYS_TS_PLL 9
20 #define CLKID_SYS_DEV_ARB 10
21 #define CLKID_SYS_MMC_PCLK 11
22 #define CLKID_SYS_CPU_CTRL 12
23 #define CLKID_SYS_JTAG_CTRL 13
24 #define CLKID_SYS_IR_CTRL 14
25 #define CLKID_SYS_IRQ_CTRL 15
26 #define CLKID_SYS_MSR_CLK 16
27 #define CLKID_SYS_ROM 17
28 #define CLKID_SYS_UART_F 18
29 #define CLKID_SYS_CPU_ARB 19
30 #define CLKID_SYS_RSA 20
31 #define CLKID_SYS_SAR_ADC 21
32 #define CLKID_SYS_STARTUP 22
33 #define CLKID_SYS_SECURE 23
34 #define CLKID_SYS_SPIFC 24
35 #define CLKID_SYS_NNA 25
36 #define CLKID_SYS_ETH_MAC 26
37 #define CLKID_SYS_GIC 27
38 #define CLKID_SYS_RAMA 28
39 #define CLKID_SYS_BIG_NIC 29
40 #define CLKID_SYS_RAMB 30
41 #define CLKID_SYS_AUDIO_PCLK 31
42 #define CLKID_SYS_PWM_KL 32
43 #define CLKID_SYS_PWM_IJ 33
44 #define CLKID_SYS_USB 34
45 #define CLKID_SYS_SD_EMMC_A 35
46 #define CLKID_SYS_SD_EMMC_C 36
47 #define CLKID_SYS_PWM_AB 37
48 #define CLKID_SYS_PWM_CD 38
49 #define CLKID_SYS_PWM_EF 39
50 #define CLKID_SYS_PWM_GH 40
51 #define CLKID_SYS_SPICC_1 41
52 #define CLKID_SYS_SPICC_0 42
53 #define CLKID_SYS_UART_A 43
54 #define CLKID_SYS_UART_B 44
55 #define CLKID_SYS_UART_C 45
56 #define CLKID_SYS_UART_D 46
57 #define CLKID_SYS_UART_E 47
58 #define CLKID_SYS_I2C_M_A 48
59 #define CLKID_SYS_I2C_M_B 49
60 #define CLKID_SYS_I2C_M_C 50
61 #define CLKID_SYS_I2C_M_D 51
62 #define CLKID_SYS_I2S_S_A 52
63 #define CLKID_SYS_RTC 53
64 #define CLKID_SYS_GE2D 54
65 #define CLKID_SYS_ISP 55
66 #define CLKID_SYS_GPV_ISP_NIC 56
67 #define CLKID_SYS_GPV_CVE_NIC 57
68 #define CLKID_SYS_MIPI_DSI_HOST 58
69 #define CLKID_SYS_MIPI_DSI_PHY 59
70 #define CLKID_SYS_ETH_PHY 60
71 #define CLKID_SYS_ACODEC 61
72 #define CLKID_SYS_DWAP 62
73 #define CLKID_SYS_DOS 63
74 #define CLKID_SYS_CVE 64
75 #define CLKID_SYS_VOUT 65
76 #define CLKID_SYS_VC9000E 66
77 #define CLKID_SYS_PWM_MN 67
78 #define CLKID_SYS_SD_EMMC_B 68
79 #define CLKID_AXI_SYS_NIC 69
80 #define CLKID_AXI_ISP_NIC 70
81 #define CLKID_AXI_CVE_NIC 71
82 #define CLKID_AXI_RAMB 72
83 #define CLKID_AXI_RAMA 73
84 #define CLKID_AXI_CPU_DMC 74
85 #define CLKID_AXI_NIC 75
86 #define CLKID_AXI_DMA 76
87 #define CLKID_AXI_MUX_NIC 77
88 #define CLKID_AXI_CVE 78
89 #define CLKID_AXI_DEV1_DMC 79
90 #define CLKID_AXI_DEV0_DMC 80
91 #define CLKID_AXI_DSP_DMC 81
92 #define CLKID_12_24M_IN 82
93 #define CLKID_12M_24M 83
94 #define CLKID_FCLK_25M_DIV 84
95 #define CLKID_FCLK_25M 85
96 #define CLKID_GEN_SEL 86
97 #define CLKID_GEN_DIV 87
98 #define CLKID_GEN 88
99 #define CLKID_SARADC_SEL 89
100 #define CLKID_SARADC_DIV 90
101 #define CLKID_SARADC 91
102 #define CLKID_PWM_A_SEL 92
103 #define CLKID_PWM_A_DIV 93
104 #define CLKID_PWM_A 94
105 #define CLKID_PWM_B_SEL 95
106 #define CLKID_PWM_B_DIV 96
107 #define CLKID_PWM_B 97
108 #define CLKID_PWM_C_SEL 98
109 #define CLKID_PWM_C_DIV 99
110 #define CLKID_PWM_C 100
111 #define CLKID_PWM_D_SEL 101
112 #define CLKID_PWM_D_DIV 102
113 #define CLKID_PWM_D 103
114 #define CLKID_PWM_E_SEL 104
115 #define CLKID_PWM_E_DIV 105
116 #define CLKID_PWM_E 106
117 #define CLKID_PWM_F_SEL 107
118 #define CLKID_PWM_F_DIV 108
119 #define CLKID_PWM_F 109
120 #define CLKID_PWM_G_SEL 110
121 #define CLKID_PWM_G_DIV 111
122 #define CLKID_PWM_G 112
123 #define CLKID_PWM_H_SEL 113
124 #define CLKID_PWM_H_DIV 114
125 #define CLKID_PWM_H 115
126 #define CLKID_PWM_I_SEL 116
127 #define CLKID_PWM_I_DIV 117
128 #define CLKID_PWM_I 118
129 #define CLKID_PWM_J_SEL 119
130 #define CLKID_PWM_J_DIV 120
131 #define CLKID_PWM_J 121
132 #define CLKID_PWM_K_SEL 122
133 #define CLKID_PWM_K_DIV 123
134 #define CLKID_PWM_K 124
135 #define CLKID_PWM_L_SEL 125
136 #define CLKID_PWM_L_DIV 126
137 #define CLKID_PWM_L 127
138 #define CLKID_PWM_M_SEL 128
139 #define CLKID_PWM_M_DIV 129
140 #define CLKID_PWM_M 130
141 #define CLKID_PWM_N_SEL 131
142 #define CLKID_PWM_N_DIV 132
143 #define CLKID_PWM_N 133
144 #define CLKID_SPICC_A_SEL 134
145 #define CLKID_SPICC_A_DIV 135
146 #define CLKID_SPICC_A 136
147 #define CLKID_SPICC_B_SEL 137
148 #define CLKID_SPICC_B_DIV 138
149 #define CLKID_SPICC_B 139
150 #define CLKID_SPIFC_SEL 140
151 #define CLKID_SPIFC_DIV 141
152 #define CLKID_SPIFC 142
153 #define CLKID_SD_EMMC_A_SEL 143
154 #define CLKID_SD_EMMC_A_DIV 144
155 #define CLKID_SD_EMMC_A 145
156 #define CLKID_SD_EMMC_B_SEL 146
157 #define CLKID_SD_EMMC_B_DIV 147
158 #define CLKID_SD_EMMC_B 148
159 #define CLKID_SD_EMMC_C_SEL 149
160 #define CLKID_SD_EMMC_C_DIV 150
161 #define CLKID_SD_EMMC_C 151
162 #define CLKID_TS_DIV 152
163 #define CLKID_TS 153
164 #define CLKID_ETH_125M_DIV 154
165 #define CLKID_ETH_125M 155
166 #define CLKID_ETH_RMII_DIV 156
167 #define CLKID_ETH_RMII 157
168 #define CLKID_MIPI_DSI_MEAS_SEL 158
169 #define CLKID_MIPI_DSI_MEAS_DIV 159
170 #define CLKID_MIPI_DSI_MEAS 160
171 #define CLKID_DSI_PHY_SEL 161
172 #define CLKID_DSI_PHY_DIV 162
173 #define CLKID_DSI_PHY 163
174 #define CLKID_VOUT_MCLK_SEL 164
175 #define CLKID_VOUT_MCLK_DIV 165
176 #define CLKID_VOUT_MCLK 166
177 #define CLKID_VOUT_ENC_SEL 167
178 #define CLKID_VOUT_ENC_DIV 168
179 #define CLKID_VOUT_ENC 169
180 #define CLKID_HCODEC_0_SEL 170
181 #define CLKID_HCODEC_0_DIV 171
182 #define CLKID_HCODEC_0 172
183 #define CLKID_HCODEC_1_SEL 173
184 #define CLKID_HCODEC_1_DIV 174
185 #define CLKID_HCODEC_1 175
186 #define CLKID_HCODEC 176
187 #define CLKID_VC9000E_ACLK_SEL 177
188 #define CLKID_VC9000E_ACLK_DIV 178
189 #define CLKID_VC9000E_ACLK 179
190 #define CLKID_VC9000E_CORE_SEL 180
191 #define CLKID_VC9000E_CORE_DIV 181
192 #define CLKID_VC9000E_CORE 182
193 #define CLKID_CSI_PHY0_SEL 183
194 #define CLKID_CSI_PHY0_DIV 184
195 #define CLKID_CSI_PHY0 185
196 #define CLKID_DEWARPA_SEL 186
197 #define CLKID_DEWARPA_DIV 187
198 #define CLKID_DEWARPA 188
199 #define CLKID_ISP0_SEL 189
200 #define CLKID_ISP0_DIV 190
201 #define CLKID_ISP0 191
202 #define CLKID_NNA_CORE_SEL 192
203 #define CLKID_NNA_CORE_DIV 193
204 #define CLKID_NNA_CORE 194
205 #define CLKID_GE2D_SEL 195
206 #define CLKID_GE2D_DIV 196
207 #define CLKID_GE2D 197
208 #define CLKID_VAPB_SEL 198
209 #define CLKID_VAPB_DIV 199
210 #define CLKID_VAPB 200