include/dt-bindings/clock/amlogic,c3-pll-clkc.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
   2 /*
   3  * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
   4  * Author: Chuan Liu <chuan.liu@amlogic.com>
   5  */
   6
   7 #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
   8 #define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
   9
  10 #define CLKID_FCLK_50M_EN                       0
  11 #define CLKID_FCLK_50M                          1
  12 #define CLKID_FCLK_DIV2_DIV                     2
  13 #define CLKID_FCLK_DIV2                         3
  14 #define CLKID_FCLK_DIV2P5_DIV                   4
  15 #define CLKID_FCLK_DIV2P5                       5
  16 #define CLKID_FCLK_DIV3_DIV                     6
  17 #define CLKID_FCLK_DIV3                         7
  18 #define CLKID_FCLK_DIV4_DIV                     8
  19 #define CLKID_FCLK_DIV4                         9
  20 #define CLKID_FCLK_DIV5_DIV                     10
  21 #define CLKID_FCLK_DIV5                         11
  22 #define CLKID_FCLK_DIV7_DIV                     12
  23 #define CLKID_FCLK_DIV7                         13
  24 #define CLKID_GP0_PLL_DCO                       14
  25 #define CLKID_GP0_PLL                           15
  26 #define CLKID_HIFI_PLL_DCO                      16
  27 #define CLKID_HIFI_PLL                          17
  28 #define CLKID_MCLK_PLL_DCO                      18
  29 #define CLKID_MCLK_PLL_OD                       19
  30 #define CLKID_MCLK_PLL                          20
  31 #define CLKID_MCLK0_SEL                         21
  32 #define CLKID_MCLK0_SEL_EN                      22
  33 #define CLKID_MCLK0_DIV                         23
  34 #define CLKID_MCLK0                             24
  35 #define CLKID_MCLK1_SEL                         25
  36 #define CLKID_MCLK1_SEL_EN                      26
  37 #define CLKID_MCLK1_DIV                         27
  38 #define CLKID_MCLK1                             28
  39
  40 #endif  /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */