include/dt-bindings/clock/mediatek,mt6735-infracfg.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2
   3 #ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H
   4 #define _DT_BINDINGS_CLK_MT6735_INFRACFG_H
   5
   6 #define CLK_INFRA_DBG                   0
   7 #define CLK_INFRA_GCE                   1
   8 #define CLK_INFRA_TRBG                  2
   9 #define CLK_INFRA_CPUM                  3
  10 #define CLK_INFRA_DEVAPC                4
  11 #define CLK_INFRA_AUDIO                 5
  12 #define CLK_INFRA_GCPU                  6
  13 #define CLK_INFRA_L2C_SRAM              7
  14 #define CLK_INFRA_M4U                   8
  15 #define CLK_INFRA_CLDMA                 9
  16 #define CLK_INFRA_CONNMCU_BUS           10
  17 #define CLK_INFRA_KP                    11
  18 #define CLK_INFRA_APXGPT                12
  19 #define CLK_INFRA_SEJ                   13
  20 #define CLK_INFRA_CCIF0_AP              14
  21 #define CLK_INFRA_CCIF1_AP              15
  22 #define CLK_INFRA_PMIC_SPI              16
  23 #define CLK_INFRA_PMIC_WRAP             17
  24
  25 #endif