include/dt-bindings/clock/renesas,r9a09g057-cpg.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2  *
   3  * Copyright (C) 2024 Renesas Electronics Corp.
   4  */
   5 #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
   6 #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
   7
   8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
   9
  10 /* Core Clock list */
  11 #define R9A09G057_SYS_0_PCLK                    0
  12 #define R9A09G057_CA55_0_CORE_CLK0              1
  13 #define R9A09G057_CA55_0_CORE_CLK1              2
  14 #define R9A09G057_CA55_0_CORE_CLK2              3
  15 #define R9A09G057_CA55_0_CORE_CLK3              4
  16 #define R9A09G057_CA55_0_PERIPHCLK              5
  17 #define R9A09G057_CM33_CLK0                     6
  18 #define R9A09G057_CST_0_SWCLKTCK                7
  19 #define R9A09G057_IOTOP_0_SHCLK                 8
  20
  21 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */