include/dt-bindings/clock/thead,th1520-clk-ap.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2 /*
   3  * Copyright (C) 2023 Vivo Communication Technology Co. Ltd.
   4  * Authors: Yangtao Li <frank.li@vivo.com>
   5  */
   6
   7 #ifndef _DT_BINDINGS_CLK_TH1520_H_
   8 #define _DT_BINDINGS_CLK_TH1520_H_
   9
  10 #define CLK_CPU_PLL0            0
  11 #define CLK_CPU_PLL1            1
  12 #define CLK_GMAC_PLL            2
  13 #define CLK_VIDEO_PLL           3
  14 #define CLK_DPU0_PLL            4
  15 #define CLK_DPU1_PLL            5
  16 #define CLK_TEE_PLL             6
  17 #define CLK_C910_I0             7
  18 #define CLK_C910                8
  19 #define CLK_BROM                9
  20 #define CLK_BMU                 10
  21 #define CLK_AHB2_CPUSYS_HCLK    11
  22 #define CLK_APB3_CPUSYS_PCLK    12
  23 #define CLK_AXI4_CPUSYS2_ACLK   13
  24 #define CLK_AON2CPU_A2X         14
  25 #define CLK_X2X_CPUSYS          15
  26 #define CLK_AXI_ACLK            16
  27 #define CLK_CPU2AON_X2H         17
  28 #define CLK_PERI_AHB_HCLK       18
  29 #define CLK_CPU2PERI_X2H        19
  30 #define CLK_PERI_APB_PCLK       20
  31 #define CLK_PERI2APB_PCLK       21
  32 #define CLK_PERISYS_APB1_HCLK   22
  33 #define CLK_PERISYS_APB2_HCLK   23
  34 #define CLK_PERISYS_APB3_HCLK   24
  35 #define CLK_PERISYS_APB4_HCLK   25
  36 #define CLK_OSC12M              26
  37 #define CLK_OUT1                27
  38 #define CLK_OUT2                28
  39 #define CLK_OUT3                29
  40 #define CLK_OUT4                30
  41 #define CLK_APB_PCLK            31
  42 #define CLK_NPU                 32
  43 #define CLK_NPU_AXI             33
  44 #define CLK_VI                  34
  45 #define CLK_VI_AHB              35
  46 #define CLK_VO_AXI              36
  47 #define CLK_VP_APB              37
  48 #define CLK_VP_AXI              38
  49 #define CLK_CPU2VP              39
  50 #define CLK_VENC                40
  51 #define CLK_DPU0                41
  52 #define CLK_DPU1                42
  53 #define CLK_EMMC_SDIO           43
  54 #define CLK_GMAC1               44
  55 #define CLK_PADCTRL1            45
  56 #define CLK_DSMART              46
  57 #define CLK_PADCTRL0            47
  58 #define CLK_GMAC_AXI            48
  59 #define CLK_GPIO3               49
  60 #define CLK_GMAC0               50
  61 #define CLK_PWM                 51
  62 #define CLK_QSPI0               52
  63 #define CLK_QSPI1               53
  64 #define CLK_SPI                 54
  65 #define CLK_UART0_PCLK          55
  66 #define CLK_UART1_PCLK          56
  67 #define CLK_UART2_PCLK          57
  68 #define CLK_UART3_PCLK          58
  69 #define CLK_UART4_PCLK          59
  70 #define CLK_UART5_PCLK          60
  71 #define CLK_GPIO0               61
  72 #define CLK_GPIO1               62
  73 #define CLK_GPIO2               63
  74 #define CLK_I2C0                64
  75 #define CLK_I2C1                65
  76 #define CLK_I2C2                66
  77 #define CLK_I2C3                67
  78 #define CLK_I2C4                68
  79 #define CLK_I2C5                69
  80 #define CLK_SPINLOCK            70
  81 #define CLK_DMA                 71
  82 #define CLK_MBOX0               72
  83 #define CLK_MBOX1               73
  84 #define CLK_MBOX2               74
  85 #define CLK_MBOX3               75
  86 #define CLK_WDT0                76
  87 #define CLK_WDT1                77
  88 #define CLK_TIMER0              78
  89 #define CLK_TIMER1              79
  90 #define CLK_SRAM0               80
  91 #define CLK_SRAM1               81
  92 #define CLK_SRAM2               82
  93 #define CLK_SRAM3               83
  94 #define CLK_PLL_GMAC_100M       84
  95 #define CLK_UART_SCLK           85
  96 #endif