include/uapi/linux/dpll.h

   1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
   2 /* Do not edit directly, auto-generated from: */
   3 /*      Documentation/netlink/specs/dpll.yaml */
   4 /* YNL-GEN uapi header */
   5
   6 #ifndef _UAPI_LINUX_DPLL_H
   7 #define _UAPI_LINUX_DPLL_H
   8
   9 #define DPLL_FAMILY_NAME        "dpll"
  10 #define DPLL_FAMILY_VERSION     1
  11
  12 /**
  13  * enum dpll_mode - working modes a dpll can support, differentiates if and how
  14  *   dpll selects one of its inputs to syntonize with it, valid values for
  15  *   DPLL_A_MODE attribute
  16  * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
  17  * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
  18  */
  19 enum dpll_mode {
  20         DPLL_MODE_MANUAL = 1,
  21         DPLL_MODE_AUTOMATIC,
  22
  23         /* private: */
  24         __DPLL_MODE_MAX,
  25         DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
  26 };
  27
  28 /**
  29  * enum dpll_lock_status - provides information of dpll device lock status,
  30  *   valid values for DPLL_A_LOCK_STATUS attribute
  31  * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
  32  *   forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED)
  33  * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
  34  *   available
  35  * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
  36  * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or
  37  *   was forced by disconnecting all the pins (latter possible only when dpll
  38  *   lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state
  39  *   was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain
  40  *   DPLL_LOCK_STATUS_UNLOCKED)
  41  */
  42 enum dpll_lock_status {
  43         DPLL_LOCK_STATUS_UNLOCKED = 1,
  44         DPLL_LOCK_STATUS_LOCKED,
  45         DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
  46         DPLL_LOCK_STATUS_HOLDOVER,
  47
  48         /* private: */
  49         __DPLL_LOCK_STATUS_MAX,
  50         DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)
  51 };
  52
  53 /**
  54  * enum dpll_lock_status_error - if previous status change was done due to a
  55  *   failure, this provides information of dpll device lock status error. Valid
  56  *   values for DPLL_A_LOCK_STATUS_ERROR attribute
  57  * @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without
  58  *   any error
  59  * @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due
  60  *   to undefined error. Driver fills this value up in case it is not able to
  61  *   obtain suitable exact error type.
  62  * @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed
  63  *   because of associated media got down. This may happen for example if dpll
  64  *   device was previously locked on an input pin of type
  65  *   PIN_TYPE_SYNCE_ETH_PORT.
  66  * @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO
  67  *   (Fractional Frequency Offset) between the RX and TX symbol rate on the
  68  *   media got too high. This may happen for example if dpll device was
  69  *   previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
  70  */
  71 enum dpll_lock_status_error {
  72         DPLL_LOCK_STATUS_ERROR_NONE = 1,
  73         DPLL_LOCK_STATUS_ERROR_UNDEFINED,
  74         DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN,
  75         DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH,
  76
  77         /* private: */
  78         __DPLL_LOCK_STATUS_ERROR_MAX,
  79         DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1)
  80 };
  81
  82 /*
  83  * level of quality of a clock device. This mainly applies when the dpll
  84  * lock-status is DPLL_LOCK_STATUS_HOLDOVER. The current list is defined
  85  * according to the table 11-7 contained in ITU-T G.8264/Y.1364 document. One
  86  * may extend this list freely by other ITU-T defined clock qualities, or
  87  * different ones defined by another standardization body (for those, please
  88  * use different prefix).
  89  */
  90 enum dpll_clock_quality_level {
  91         DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRC = 1,
  92         DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_A,
  93         DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_B,
  94         DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEC1,
  95         DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRTC,
  96         DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRTC,
  97         DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEEC,
  98         DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRC,
  99
 100         /* private: */
 101         __DPLL_CLOCK_QUALITY_LEVEL_MAX,
 102         DPLL_CLOCK_QUALITY_LEVEL_MAX = (__DPLL_CLOCK_QUALITY_LEVEL_MAX - 1)
 103 };
 104
 105 #define DPLL_TEMP_DIVIDER       1000
 106
 107 /**
 108  * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
 109  * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
 110  * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
 111  */
 112 enum dpll_type {
 113         DPLL_TYPE_PPS = 1,
 114         DPLL_TYPE_EEC,
 115
 116         /* private: */
 117         __DPLL_TYPE_MAX,
 118         DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1)
 119 };
 120
 121 /**
 122  * enum dpll_pin_type - defines possible types of a pin, valid values for
 123  *   DPLL_A_PIN_TYPE attribute
 124  * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins
 125  * @DPLL_PIN_TYPE_EXT: external input
 126  * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
 127  * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
 128  * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
 129  */
 130 enum dpll_pin_type {
 131         DPLL_PIN_TYPE_MUX = 1,
 132         DPLL_PIN_TYPE_EXT,
 133         DPLL_PIN_TYPE_SYNCE_ETH_PORT,
 134         DPLL_PIN_TYPE_INT_OSCILLATOR,
 135         DPLL_PIN_TYPE_GNSS,
 136
 137         /* private: */
 138         __DPLL_PIN_TYPE_MAX,
 139         DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1)
 140 };
 141
 142 /**
 143  * enum dpll_pin_direction - defines possible direction of a pin, valid values
 144  *   for DPLL_A_PIN_DIRECTION attribute
 145  * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal
 146  * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal
 147  */
 148 enum dpll_pin_direction {
 149         DPLL_PIN_DIRECTION_INPUT = 1,
 150         DPLL_PIN_DIRECTION_OUTPUT,
 151
 152         /* private: */
 153         __DPLL_PIN_DIRECTION_MAX,
 154         DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1)
 155 };
 156
 157 #define DPLL_PIN_FREQUENCY_1_HZ         1
 158 #define DPLL_PIN_FREQUENCY_10_KHZ       10000
 159 #define DPLL_PIN_FREQUENCY_77_5_KHZ     77500
 160 #define DPLL_PIN_FREQUENCY_10_MHZ       10000000
 161
 162 /**
 163  * enum dpll_pin_state - defines possible states of a pin, valid values for
 164  *   DPLL_A_PIN_STATE attribute
 165  * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop
 166  * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid
 167  *   input
 168  * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection
 169  */
 170 enum dpll_pin_state {
 171         DPLL_PIN_STATE_CONNECTED = 1,
 172         DPLL_PIN_STATE_DISCONNECTED,
 173         DPLL_PIN_STATE_SELECTABLE,
 174
 175         /* private: */
 176         __DPLL_PIN_STATE_MAX,
 177         DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1)
 178 };
 179
 180 /**
 181  * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid
 182  *   flags on DPLL_A_PIN_CAPABILITIES attribute
 183  * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed
 184  * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed
 185  * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed
 186  */
 187 enum dpll_pin_capabilities {
 188         DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1,
 189         DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2,
 190         DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
 191 };
 192
 193 #define DPLL_PHASE_OFFSET_DIVIDER       1000
 194
 195 enum dpll_a {
 196         DPLL_A_ID = 1,
 197         DPLL_A_MODULE_NAME,
 198         DPLL_A_PAD,
 199         DPLL_A_CLOCK_ID,
 200         DPLL_A_MODE,
 201         DPLL_A_MODE_SUPPORTED,
 202         DPLL_A_LOCK_STATUS,
 203         DPLL_A_TEMP,
 204         DPLL_A_TYPE,
 205         DPLL_A_LOCK_STATUS_ERROR,
 206         DPLL_A_CLOCK_QUALITY_LEVEL,
 207
 208         __DPLL_A_MAX,
 209         DPLL_A_MAX = (__DPLL_A_MAX - 1)
 210 };
 211
 212 enum dpll_a_pin {
 213         DPLL_A_PIN_ID = 1,
 214         DPLL_A_PIN_PARENT_ID,
 215         DPLL_A_PIN_MODULE_NAME,
 216         DPLL_A_PIN_PAD,
 217         DPLL_A_PIN_CLOCK_ID,
 218         DPLL_A_PIN_BOARD_LABEL,
 219         DPLL_A_PIN_PANEL_LABEL,
 220         DPLL_A_PIN_PACKAGE_LABEL,
 221         DPLL_A_PIN_TYPE,
 222         DPLL_A_PIN_DIRECTION,
 223         DPLL_A_PIN_FREQUENCY,
 224         DPLL_A_PIN_FREQUENCY_SUPPORTED,
 225         DPLL_A_PIN_FREQUENCY_MIN,
 226         DPLL_A_PIN_FREQUENCY_MAX,
 227         DPLL_A_PIN_PRIO,
 228         DPLL_A_PIN_STATE,
 229         DPLL_A_PIN_CAPABILITIES,
 230         DPLL_A_PIN_PARENT_DEVICE,
 231         DPLL_A_PIN_PARENT_PIN,
 232         DPLL_A_PIN_PHASE_ADJUST_MIN,
 233         DPLL_A_PIN_PHASE_ADJUST_MAX,
 234         DPLL_A_PIN_PHASE_ADJUST,
 235         DPLL_A_PIN_PHASE_OFFSET,
 236         DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET,
 237         DPLL_A_PIN_ESYNC_FREQUENCY,
 238         DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,
 239         DPLL_A_PIN_ESYNC_PULSE,
 240
 241         __DPLL_A_PIN_MAX,
 242         DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
 243 };
 244
 245 enum dpll_cmd {
 246         DPLL_CMD_DEVICE_ID_GET = 1,
 247         DPLL_CMD_DEVICE_GET,
 248         DPLL_CMD_DEVICE_SET,
 249         DPLL_CMD_DEVICE_CREATE_NTF,
 250         DPLL_CMD_DEVICE_DELETE_NTF,
 251         DPLL_CMD_DEVICE_CHANGE_NTF,
 252         DPLL_CMD_PIN_ID_GET,
 253         DPLL_CMD_PIN_GET,
 254         DPLL_CMD_PIN_SET,
 255         DPLL_CMD_PIN_CREATE_NTF,
 256         DPLL_CMD_PIN_DELETE_NTF,
 257         DPLL_CMD_PIN_CHANGE_NTF,
 258
 259         __DPLL_CMD_MAX,
 260         DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1)
 261 };
 262
 263 #define DPLL_MCGRP_MONITOR      "monitor"
 264
 265 #endif /* _UAPI_LINUX_DPLL_H */