include/uapi/linux/serial_core.h

   1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
   2 /*
   3  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   4  */
   5 #ifndef _UAPILINUX_SERIAL_CORE_H
   6 #define _UAPILINUX_SERIAL_CORE_H
   7
   8 #include <linux/serial.h>
   9
  10 /*
  11  * The type definitions.  These are from Ted Ts'o's serial.h
  12  * By historical reasons the values from 0 to 13 are defined
  13  * in the include/uapi/linux/serial.h, do not define them here.
  14  * Values 0 to 19 are used by setserial from busybox and must never
  15  * be modified.
  16  */
  17 #define PORT_NS16550A   14
  18 #define PORT_XSCALE     15
  19 #define PORT_RM9000     16      /* PMC-Sierra RM9xxx internal UART */
  20 #define PORT_OCTEON     17      /* Cavium OCTEON internal UART */
  21 #define PORT_AR7        18      /* Texas Instruments AR7 internal UART */
  22 #define PORT_U6_16550A  19      /* ST-Ericsson U6xxx internal UART */
  23 #define PORT_TEGRA      20      /* NVIDIA Tegra internal UART */
  24 #define PORT_XR17D15X   21      /* Exar XR17D15x UART */
  25 #define PORT_LPC3220    22      /* NXP LPC32xx SoC "Standard" UART */
  26 #define PORT_8250_CIR   23      /* CIR infrared port, has its own driver */
  27 #define PORT_XR17V35X   24      /* Exar XR17V35x UARTs */
  28 #define PORT_BRCM_TRUMANAGE     25
  29 #define PORT_ALTR_16550_F32 26  /* Altera 16550 UART with 32 FIFOs */
  30 #define PORT_ALTR_16550_F64 27  /* Altera 16550 UART with 64 FIFOs */
  31 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
  32 #define PORT_RT2880     29      /* Ralink RT2880 internal UART */
  33 #define PORT_16550A_FSL64 30    /* Freescale 16550 UART with 64 FIFOs */
  34
  35 /*
  36  * ARM specific type numbers.  These are not currently guaranteed
  37  * to be implemented, and will change in the future.  These are
  38  * separate so any additions to the old serial.c that occur before
  39  * we are merged can be easily merged here.
  40  */
  41 #define PORT_PXA        31
  42 #define PORT_AMBA       32
  43 #define PORT_CLPS711X   33
  44 #define PORT_SA1100     34
  45 #define PORT_UART00     35
  46 #define PORT_OWL        36
  47 #define PORT_21285      37
  48
  49 /* Sparc type numbers.  */
  50 #define PORT_SUNZILOG   38
  51 #define PORT_SUNSAB     39
  52
  53 /* Nuvoton UART */
  54 #define PORT_NPCM       40
  55
  56 /* NVIDIA Tegra Combined UART */
  57 #define PORT_TEGRA_TCU  41
  58
  59 /* ASPEED AST2x00 virtual UART */
  60 #define PORT_ASPEED_VUART       42
  61
  62 /* Intel EG20 */
  63 #define PORT_PCH_8LINE  44
  64 #define PORT_PCH_2LINE  45
  65
  66 /* DEC */
  67 #define PORT_DZ         46
  68 #define PORT_ZS         47
  69
  70 /* Parisc type numbers. */
  71 #define PORT_MUX        48
  72
  73 /* Atmel AT91 SoC */
  74 #define PORT_ATMEL      49
  75
  76 /* Macintosh Zilog type numbers */
  77 #define PORT_MAC_ZILOG  50      /* m68k : not yet implemented */
  78 #define PORT_PMAC_ZILOG 51
  79
  80 /* SH-SCI */
  81 #define PORT_SCI        52
  82 #define PORT_SCIF       53
  83 #define PORT_IRDA       54
  84
  85 /* SGI IP22 aka Indy / Challenge S / Indigo 2 */
  86 #define PORT_IP22ZILOG  56
  87
  88 /* PPC CPM type number */
  89 #define PORT_CPM        58
  90
  91 /* MPC52xx (and MPC512x) type numbers */
  92 #define PORT_MPC52xx    59
  93
  94 /* IBM icom */
  95 #define PORT_ICOM       60
  96
  97 /* Motorola i.MX SoC */
  98 #define PORT_IMX        62
  99
 100 /* TXX9 type number */
 101 #define PORT_TXX9       64
 102
 103 /*Digi jsm */
 104 #define PORT_JSM        69
 105
 106 /* SUN4V Hypervisor Console */
 107 #define PORT_SUNHV      72
 108
 109 /* Xilinx uartlite */
 110 #define PORT_UARTLITE   74
 111
 112 /* Broadcom BCM7271 UART */
 113 #define PORT_BCM7271    76
 114
 115 /* Broadcom SB1250, etc. SOC */
 116 #define PORT_SB1250_DUART       77
 117
 118 /* Freescale ColdFire */
 119 #define PORT_MCF        78
 120
 121 #define PORT_SC26XX     82
 122
 123 /* SH-SCI */
 124 #define PORT_SCIFA      83
 125
 126 #define PORT_S3C6400    84
 127
 128 /* MAX3100 */
 129 #define PORT_MAX3100    86
 130
 131 /* Timberdale UART */
 132 #define PORT_TIMBUART   87
 133
 134 /* Qualcomm MSM SoCs */
 135 #define PORT_MSM        88
 136
 137 /* BCM63xx family SoCs */
 138 #define PORT_BCM63XX    89
 139
 140 /* Aeroflex Gaisler GRLIB APBUART */
 141 #define PORT_APBUART    90
 142
 143 /* Altera UARTs */
 144 #define PORT_ALTERA_JTAGUART    91
 145 #define PORT_ALTERA_UART        92
 146
 147 /* SH-SCI */
 148 #define PORT_SCIFB      93
 149
 150 /* MAX310X */
 151 #define PORT_MAX310X    94
 152
 153 /* TI DA8xx/66AK2x */
 154 #define PORT_DA830      95
 155
 156 /* TI OMAP-UART */
 157 #define PORT_OMAP       96
 158
 159 /* VIA VT8500 SoC */
 160 #define PORT_VT8500     97
 161
 162 /* Cadence (Xilinx Zynq) UART */
 163 #define PORT_XUARTPS    98
 164
 165 /* Atheros AR933X SoC */
 166 #define PORT_AR933X     99
 167
 168 /* MCHP 16550A UART with 256 byte FIFOs */
 169 #define PORT_MCHP16550A 100
 170
 171 /* ARC (Synopsys) on-chip UART */
 172 #define PORT_ARC       101
 173
 174 /* Rocketport EXPRESS/INFINITY */
 175 #define PORT_RP2        102
 176
 177 /* Freescale lpuart */
 178 #define PORT_LPUART     103
 179
 180 /* SH-SCI */
 181 #define PORT_HSCIF      104
 182
 183 /* ST ASC type numbers */
 184 #define PORT_ASC       105
 185
 186 /* MEN 16z135 UART */
 187 #define PORT_MEN_Z135   107
 188
 189 /* SC16IS7xx */
 190 #define PORT_SC16IS7XX   108
 191
 192 /* MESON */
 193 #define PORT_MESON      109
 194
 195 /* Conexant Digicolor */
 196 #define PORT_DIGICOLOR  110
 197
 198 /* SPRD SERIAL  */
 199 #define PORT_SPRD       111
 200
 201 /* STM32 USART */
 202 #define PORT_STM32      113
 203
 204 /* MVEBU UART */
 205 #define PORT_MVEBU      114
 206
 207 /* Microchip PIC32 UART */
 208 #define PORT_PIC32      115
 209
 210 /* MPS2 UART */
 211 #define PORT_MPS2UART   116
 212
 213 /* MediaTek BTIF */
 214 #define PORT_MTK_BTIF   117
 215
 216 /* RDA UART */
 217 #define PORT_RDA        118
 218
 219 /* Socionext Milbeaut UART */
 220 #define PORT_MLB_USIO   119
 221
 222 /* SiFive UART */
 223 #define PORT_SIFIVE_V0  120
 224
 225 /* Sunix UART */
 226 #define PORT_SUNIX      121
 227
 228 /* Freescale LINFlexD UART */
 229 #define PORT_LINFLEXUART        122
 230
 231 /* Sunplus UART */
 232 #define PORT_SUNPLUS    123
 233
 234 /* Generic type identifier for ports which type is not important to userspace. */
 235 #define PORT_GENERIC    (-1)
 236
 237 #endif /* _UAPILINUX_SERIAL_CORE_H */