1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
3 * Copyright (c) 2016 Hisilicon Limited.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #ifndef HNS_ABI_USER_H
35 #define HNS_ABI_USER_H
37 #include <linux/types.h>
39 struct hns_roce_ib_create_cq
{
40 __aligned_u64 buf_addr
;
41 __aligned_u64 db_addr
;
46 enum hns_roce_cq_cap_flags
{
47 HNS_ROCE_CQ_FLAG_RECORD_DB
= 1 << 0,
50 struct hns_roce_ib_create_cq_resp
{
51 __aligned_u64 cqn
; /* Only 32 bits used, 64 for compat */
52 __aligned_u64 cap_flags
;
55 enum hns_roce_srq_cap_flags
{
56 HNS_ROCE_SRQ_CAP_RECORD_DB
= 1 << 0,
59 enum hns_roce_srq_cap_flags_resp
{
60 HNS_ROCE_RSP_SRQ_CAP_RECORD_DB
= 1 << 0,
63 struct hns_roce_ib_create_srq
{
64 __aligned_u64 buf_addr
;
65 __aligned_u64 db_addr
;
66 __aligned_u64 que_addr
;
67 __u32 req_cap_flags
; /* Use enum hns_roce_srq_cap_flags */
71 struct hns_roce_ib_create_srq_resp
{
73 __u32 cap_flags
; /* Use enum hns_roce_srq_cap_flags */
76 enum hns_roce_congest_type_flags
{
77 HNS_ROCE_CREATE_QP_FLAGS_DCQCN
,
78 HNS_ROCE_CREATE_QP_FLAGS_LDCP
,
79 HNS_ROCE_CREATE_QP_FLAGS_HC3
,
80 HNS_ROCE_CREATE_QP_FLAGS_DIP
,
83 enum hns_roce_create_qp_comp_mask
{
84 HNS_ROCE_CREATE_QP_MASK_CONGEST_TYPE
= 1 << 0,
87 struct hns_roce_ib_create_qp
{
88 __aligned_u64 buf_addr
;
89 __aligned_u64 db_addr
;
94 __aligned_u64 sdb_addr
;
95 __aligned_u64 comp_mask
; /* Use enum hns_roce_create_qp_comp_mask */
96 __aligned_u64 create_flags
;
97 __aligned_u64 cong_type_flags
;
100 enum hns_roce_qp_cap_flags
{
101 HNS_ROCE_QP_CAP_RQ_RECORD_DB
= 1 << 0,
102 HNS_ROCE_QP_CAP_SQ_RECORD_DB
= 1 << 1,
103 HNS_ROCE_QP_CAP_OWNER_DB
= 1 << 2,
104 HNS_ROCE_QP_CAP_DIRECT_WQE
= 1 << 5,
107 struct hns_roce_ib_create_qp_resp
{
108 __aligned_u64 cap_flags
;
109 __aligned_u64 dwqe_mmap_key
;
112 struct hns_roce_ib_modify_qp_resp
{
119 HNS_ROCE_EXSGE_FLAGS
= 1 << 0,
120 HNS_ROCE_RQ_INLINE_FLAGS
= 1 << 1,
121 HNS_ROCE_CQE_INLINE_FLAGS
= 1 << 2,
125 HNS_ROCE_RSP_EXSGE_FLAGS
= 1 << 0,
126 HNS_ROCE_RSP_RQ_INLINE_FLAGS
= 1 << 1,
127 HNS_ROCE_RSP_CQE_INLINE_FLAGS
= 1 << 2,
130 struct hns_roce_ib_alloc_ucontext_resp
{
136 __u32 max_inline_data
;
141 struct hns_roce_ib_alloc_ucontext
{
146 struct hns_roce_ib_alloc_pd_resp
{
150 struct hns_roce_ib_create_ah_resp
{
156 #endif /* HNS_ABI_USER_H */