tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json

   1 [
   2         {
   3                 "EventCode": "0xB1",
   4                 "EventName": "cycle_wait_icache_fill",
   5                 "BriefDescription": "Cycles waiting for ICACHE fill data"
   6         },
   7         {
   8                 "EventCode": "0xC1",
   9                 "EventName": "cycle_wait_dcache_fill",
  10                 "BriefDescription": "Cycles waiting for DCACHE fill data"
  11         },
  12         {
  13                 "EventCode": "0xD1",
  14                 "EventName": "uncached_ifetch_from_bus",
  15                 "BriefDescription": "Uncached ifetch data access from bus"
  16         },
  17         {
  18                 "EventCode": "0xE1",
  19                 "EventName": "uncached_load_from_bus",
  20                 "BriefDescription": "Uncached load data access from bus"
  21         },
  22         {
  23                 "EventCode": "0xF1",
  24                 "EventName": "cycle_wait_uncached_ifetch",
  25                 "BriefDescription": "Cycles waiting for uncached ifetch data from bus"
  26         },
  27         {
  28                 "EventCode": "0x101",
  29                 "EventName": "cycle_wait_uncached_load",
  30                 "BriefDescription": "Cycles waiting for uncached load data from bus"
  31         },
  32         {
  33                 "EventCode": "0x111",
  34                 "EventName": "main_itlb_access",
  35                 "BriefDescription": "Main ITLB access"
  36         },
  37         {
  38                 "EventCode": "0x121",
  39                 "EventName": "main_itlb_miss",
  40                 "BriefDescription": "Main ITLB miss"
  41         },
  42         {
  43                 "EventCode": "0x131",
  44                 "EventName": "main_dtlb_access",
  45                 "BriefDescription": "Main DTLB access"
  46         },
  47         {
  48                 "EventCode": "0x141",
  49                 "EventName": "main_dtlb_miss",
  50                 "BriefDescription": "Main DTLB miss"
  51         },
  52         {
  53                 "EventCode": "0x151",
  54                 "EventName": "cycle_wait_itlb_fill",
  55                 "BriefDescription": "Cycles waiting for Main ITLB fill data"
  56         },
  57         {
  58                 "EventCode": "0x161",
  59                 "EventName": "pipe_stall_cycle_dtlb_miss",
  60                 "BriefDescription": "Pipeline stall cycles caused by Main DTLB miss"
  61         },
  62         {
  63                 "EventCode": "0x02",
  64                 "EventName": "mispredict_condition_br",
  65                 "BriefDescription": "Misprediction of conditional branches"
  66         },
  67         {
  68                 "EventCode": "0x12",
  69                 "EventName": "mispredict_take_condition_br",
  70                 "BriefDescription": "Misprediction of taken conditional branches"
  71         },
  72         {
  73                 "EventCode": "0x22",
  74                 "EventName": "mispredict_target_ret_inst",
  75                 "BriefDescription": "Misprediction of targets of Return instructions"
  76         }
  77 ]