1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2018, Google LLC.
7 * This is a regression test for the bug fixed by the following commit:
8 * d3802286fa0f ("kvm: x86: Disallow illegal IA32_APIC_BASE MSR values")
10 * That bug allowed a user-mode program that called the KVM_SET_SREGS
11 * ioctl to put a VCPU's local APIC into an invalid state.
17 #include <sys/ioctl.h>
19 #include "test_util.h"
22 #include "processor.h"
24 #define TEST_INVALID_CR_BIT(vcpu, cr, orig, bit) \
26 struct kvm_sregs new; \
29 /* Skip the sub-test, the feature/bit is supported. */ \
33 memcpy(&new, &orig, sizeof(sregs)); \
36 rc = _vcpu_sregs_set(vcpu, &new); \
37 TEST_ASSERT(rc, "KVM allowed invalid " #cr " bit (0x%lx)", bit); \
39 /* Sanity check that KVM didn't change anything. */ \
40 vcpu_sregs_get(vcpu, &new); \
41 TEST_ASSERT(!memcmp(&new, &orig, sizeof(new)), "KVM modified sregs"); \
44 static uint64_t calc_supported_cr4_feature_bits(void)
48 cr4
= X86_CR4_VME
| X86_CR4_PVI
| X86_CR4_TSD
| X86_CR4_DE
|
49 X86_CR4_PSE
| X86_CR4_PAE
| X86_CR4_MCE
| X86_CR4_PGE
|
50 X86_CR4_PCE
| X86_CR4_OSFXSR
| X86_CR4_OSXMMEXCPT
;
51 if (kvm_cpu_has(X86_FEATURE_UMIP
))
53 if (kvm_cpu_has(X86_FEATURE_LA57
))
55 if (kvm_cpu_has(X86_FEATURE_VMX
))
57 if (kvm_cpu_has(X86_FEATURE_SMX
))
59 if (kvm_cpu_has(X86_FEATURE_FSGSBASE
))
60 cr4
|= X86_CR4_FSGSBASE
;
61 if (kvm_cpu_has(X86_FEATURE_PCID
))
63 if (kvm_cpu_has(X86_FEATURE_XSAVE
))
64 cr4
|= X86_CR4_OSXSAVE
;
65 if (kvm_cpu_has(X86_FEATURE_SMEP
))
67 if (kvm_cpu_has(X86_FEATURE_SMAP
))
69 if (kvm_cpu_has(X86_FEATURE_PKU
))
75 int main(int argc
, char *argv
[])
77 struct kvm_sregs sregs
;
78 struct kvm_vcpu
*vcpu
;
84 * Create a dummy VM, specifically to avoid doing KVM_SET_CPUID2, and
85 * use it to verify all supported CR4 bits can be set prior to defining
86 * the vCPU model, i.e. without doing KVM_SET_CPUID2.
88 vm
= vm_create_barebones();
89 vcpu
= __vm_vcpu_add(vm
, 0);
91 vcpu_sregs_get(vcpu
, &sregs
);
94 sregs
.cr4
|= calc_supported_cr4_feature_bits();
97 rc
= _vcpu_sregs_set(vcpu
, &sregs
);
98 TEST_ASSERT(!rc
, "Failed to set supported CR4 bits (0x%lx)", cr4
);
100 vcpu_sregs_get(vcpu
, &sregs
);
101 TEST_ASSERT(sregs
.cr4
== cr4
, "sregs.CR4 (0x%llx) != CR4 (0x%lx)",
104 /* Verify all unsupported features are rejected by KVM. */
105 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_UMIP
);
106 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_LA57
);
107 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_VMXE
);
108 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_SMXE
);
109 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_FSGSBASE
);
110 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_PCIDE
);
111 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_OSXSAVE
);
112 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_SMEP
);
113 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_SMAP
);
114 TEST_INVALID_CR_BIT(vcpu
, cr4
, sregs
, X86_CR4_PKE
);
116 for (i
= 32; i
< 64; i
++)
117 TEST_INVALID_CR_BIT(vcpu
, cr0
, sregs
, BIT(i
));
119 /* NW without CD is illegal, as is PG without PE. */
120 TEST_INVALID_CR_BIT(vcpu
, cr0
, sregs
, X86_CR0_NW
);
121 TEST_INVALID_CR_BIT(vcpu
, cr0
, sregs
, X86_CR0_PG
);
125 /* Create a "real" VM and verify APIC_BASE can be set. */
126 vm
= vm_create_with_one_vcpu(&vcpu
, NULL
);
128 vcpu_sregs_get(vcpu
, &sregs
);
129 sregs
.apic_base
= 1 << 10;
130 rc
= _vcpu_sregs_set(vcpu
, &sregs
);
131 TEST_ASSERT(rc
, "Set IA32_APIC_BASE to %llx (invalid)",
133 sregs
.apic_base
= 1 << 11;
134 rc
= _vcpu_sregs_set(vcpu
, &sregs
);
135 TEST_ASSERT(!rc
, "Couldn't set IA32_APIC_BASE to %llx (valid)",