1 What: /sys/bus/coresight/devices/etm<N>/enable_source
4 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
5 Description: (RW) Enable/disable tracing on this specific trace entiry.
6 Enabling a source implies the source has been configured
7 properly and a sink has been identidifed for it. The path
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/etm<N>/cpu
14 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
15 Description: (Read) The CPU this tracing entity is associated with.
17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
20 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
21 Description: (Read) Indicates the number of PE comparator inputs that are
22 available for tracing.
24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
27 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
28 Description: (Read) Indicates the number of address comparator pairs that are
29 available for tracing.
31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr
34 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
35 Description: (Read) Indicates the number of counters that are available for
38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
41 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
42 Description: (Read) Indicates how many external inputs are implemented.
44 What: /sys/bus/coresight/devices/etm<N>/numcidc
47 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
48 Description: (Read) Indicates the number of Context ID comparators that are
49 available for tracing.
51 What: /sys/bus/coresight/devices/etm<N>/numvmidc
54 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
55 Description: (Read) Indicates the number of VMID comparators that are available
58 What: /sys/bus/coresight/devices/etm<N>/nrseqstate
61 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
62 Description: (Read) Indicates the number of sequencer states that are
65 What: /sys/bus/coresight/devices/etm<N>/nr_resource
68 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
69 Description: (Read) Indicates the number of resource selection pairs that are
70 available for tracing.
72 What: /sys/bus/coresight/devices/etm<N>/nr_ss_cmp
75 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
76 Description: (Read) Indicates the number of single-shot comparator controls that
77 are available for tracing.
79 What: /sys/bus/coresight/devices/etm<N>/reset
82 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
83 Description: (Write) Cancels all configuration on a trace unit and set it back
84 to its boot configuration.
86 What: /sys/bus/coresight/devices/etm<N>/mode
89 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
90 Description: (RW) Controls various modes supported by this ETM, for example
91 P0 instruction tracing, branch broadcast, cycle counting and
94 What: /sys/bus/coresight/devices/etm<N>/pe
97 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
98 Description: (RW) Controls which PE to trace.
100 What: /sys/bus/coresight/devices/etm<N>/event
103 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
104 Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3.
106 What: /sys/bus/coresight/devices/etm<N>/event_instren
109 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
110 Description: (RW) Controls the behavior of the events in bank 0 to 3.
112 What: /sys/bus/coresight/devices/etm<N>/event_ts
115 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
116 Description: (RW) Controls the insertion of global timestamps in the trace
119 What: /sys/bus/coresight/devices/etm<N>/syncfreq
122 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
123 Description: (RW) Controls how often trace synchronization requests occur.
125 What: /sys/bus/coresight/devices/etm<N>/cyc_threshold
128 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
129 Description: (RW) Sets the threshold value for cycle counting.
131 What: /sys/bus/coresight/devices/etm<N>/bb_ctrl
134 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
135 Description: (RW) Controls which regions in the memory map are enabled to
136 use branch broadcasting.
138 What: /sys/bus/coresight/devices/etm<N>/event_vinst
141 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
142 Description: (RW) Controls instruction trace filtering.
144 What: /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
147 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
148 Description: (RW) In Secure state, each bit controls whether instruction
149 tracing is enabled for the corresponding exception level.
151 What: /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
154 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
155 Description: (RW) In non-secure state, each bit controls whether instruction
156 tracing is enabled for the corresponding exception level.
158 What: /sys/bus/coresight/devices/etm<N>/addr_idx
161 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
162 Description: (RW) Select which address comparator or pair (of comparators) to
165 What: /sys/bus/coresight/devices/etm<N>/addr_instdatatype
168 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
169 Description: (RW) Controls what type of comparison the trace unit performs.
171 What: /sys/bus/coresight/devices/etm<N>/addr_single
174 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
175 Description: (RW) Used to setup single address comparator values.
177 What: /sys/bus/coresight/devices/etm<N>/addr_range
180 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
181 Description: (RW) Used to setup address range comparator values.
183 What: /sys/bus/coresight/devices/etm<N>/seq_idx
186 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
187 Description: (RW) Select which sequensor.
189 What: /sys/bus/coresight/devices/etm<N>/seq_state
192 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
193 Description: (RW) Use this to set, or read, the sequencer state.
195 What: /sys/bus/coresight/devices/etm<N>/seq_event
198 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
199 Description: (RW) Moves the sequencer state to a specific state.
201 What: /sys/bus/coresight/devices/etm<N>/seq_reset_event
204 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
205 Description: (RW) Moves the sequencer to state 0 when a programmed event
208 What: /sys/bus/coresight/devices/etm<N>/cntr_idx
211 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
212 Description: (RW) Select which counter unit to work with.
214 What: /sys/bus/coresight/devices/etm<N>/cntrldvr
217 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
218 Description: (RW) This sets or returns the reload count value of the
221 What: /sys/bus/coresight/devices/etm<N>/cntr_val
224 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
225 Description: (RW) This sets or returns the current count value of the
228 What: /sys/bus/coresight/devices/etm<N>/cntr_ctrl
231 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
232 Description: (RW) Controls the operation of the selected counter.
234 What: /sys/bus/coresight/devices/etm<N>/res_idx
237 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
238 Description: (RW) Select which resource selection unit to work with.
240 What: /sys/bus/coresight/devices/etm<N>/res_ctrl
243 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
244 Description: (RW) Controls the selection of the resources in the trace unit.
246 What: /sys/bus/coresight/devices/etm<N>/ctxid_idx
249 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
250 Description: (RW) Select which context ID comparator to work with.
252 What: /sys/bus/coresight/devices/etm<N>/ctxid_pid
255 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
256 Description: (RW) Get/Set the context ID comparator value to trigger on.
258 What: /sys/bus/coresight/devices/etm<N>/ctxid_masks
261 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
262 Description: (RW) Mask for all 8 context ID comparator value
263 registers (if implemented).
265 What: /sys/bus/coresight/devices/etm<N>/vmid_idx
268 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
269 Description: (RW) Select which virtual machine ID comparator to work with.
271 What: /sys/bus/coresight/devices/etm<N>/vmid_val
274 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
275 Description: (RW) Get/Set the virtual machine ID comparator value to
278 What: /sys/bus/coresight/devices/etm<N>/vmid_masks
281 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
282 Description: (RW) Mask for all 8 virtual machine ID comparator value
283 registers (if implemented).
285 What: /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
288 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
289 Description: (RW) Set the Exception Level matching bits for secure and
290 non-secure exception levels.
292 What: /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
295 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
296 Description: (RW) Access the start stop control register for PE input
299 What: /sys/bus/coresight/devices/etm<N>/addr_cmp_view
302 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
303 Description: (Read) Print the current settings for the selected address
306 What: /sys/bus/coresight/devices/etm<N>/sshot_idx
309 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
310 Description: (RW) Select the single shot control register to access.
312 What: /sys/bus/coresight/devices/etm<N>/sshot_ctrl
315 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
316 Description: (RW) Access the selected single shot control register.
318 What: /sys/bus/coresight/devices/etm<N>/sshot_status
321 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
322 Description: (Read) Print the current value of the selected single shot
325 What: /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
328 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
329 Description: (RW) Access the selected single show PE comparator control
332 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
335 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
336 Description: (Read) Print the content of the OS Lock Status Register (0x304).
337 The value it taken directly from the HW.
339 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
342 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
343 Description: (Read) Print the content of the Power Down Control Register
344 (0x310). The value is taken directly from the HW.
346 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
349 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
350 Description: (Read) Print the content of the Power Down Status Register
351 (0x314). The value is taken directly from the HW.
353 What: /sys/bus/coresight/devices/etm<N>/mgmt/trclsr
356 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
357 Description: (Read) Print the content of the SW Lock Status Register
358 (0xFB4). The value is taken directly from the HW.
360 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
363 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
364 Description: (Read) Print the content of the Authentication Status Register
365 (0xFB8). The value is taken directly from the HW.
367 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
370 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
371 Description: (Read) Print the content of the Device ID Register
372 (0xFC8). The value is taken directly from the HW.
374 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevarch
377 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
378 Description: (Read) Print the content of the Device Architecture Register
379 (offset 0xFBC). The value is taken directly read
382 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
385 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
386 Description: (Read) Print the content of the Device Type Register
387 (0xFCC). The value is taken directly from the HW.
389 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
392 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
393 Description: (Read) Print the content of the Peripheral ID0 Register
394 (0xFE0). The value is taken directly from the HW.
396 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
399 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
400 Description: (Read) Print the content of the Peripheral ID1 Register
401 (0xFE4). The value is taken directly from the HW.
403 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
406 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
407 Description: (Read) Print the content of the Peripheral ID2 Register
408 (0xFE8). The value is taken directly from the HW.
410 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
413 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
414 Description: (Read) Print the content of the Peripheral ID3 Register
415 (0xFEC). The value is taken directly from the HW.
417 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
420 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
421 Description: (Read) Print the content of the trace configuration register
422 (0x010) as currently set by SW.
424 What: /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
427 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
428 Description: (Read) Print the content of the trace ID register (0x040).
430 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
433 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
434 Description: (Read) Returns the tracing capabilities of the trace unit (0x1E0).
435 The value is taken directly from the HW.
437 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
440 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
441 Description: (Read) Returns the tracing capabilities of the trace unit (0x1E4).
442 The value is taken directly from the HW.
444 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
447 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
448 Description: (Read) Returns the maximum size of the data value, data address,
449 VMID, context ID and instruction address in the trace unit
450 (0x1E8). The value is taken directly from the HW.
452 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
455 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
456 Description: (Read) Returns the value associated with various resources
457 available to the trace unit. See the Trace Macrocell
458 architecture specification for more details (0x1E8).
459 The value is taken directly from the HW.
461 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
464 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
465 Description: (Read) Returns how many resources the trace unit supports (0x1F0).
466 The value is taken directly from the HW.
468 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
471 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
472 Description: (Read) Returns how many resources the trace unit supports (0x1F4).
473 The value is taken directly from the HW.
475 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
478 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
479 Description: (Read) Returns the maximum speculation depth of the instruction
480 trace stream. (0x180). The value is taken directly from the HW.
482 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
485 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
486 Description: (Read) Returns the number of P0 right-hand keys that the trace unit
487 can use (0x184). The value is taken directly from the HW.
489 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
492 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
493 Description: (Read) Returns the number of P1 right-hand keys that the trace unit
494 can use (0x188). The value is taken directly from the HW.
496 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
499 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
500 Description: (Read) Returns the number of special P1 right-hand keys that the
501 trace unit can use (0x18C). The value is taken directly from
504 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
507 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
508 Description: (Read) Returns the number of conditional P1 right-hand keys that
509 the trace unit can use (0x190). The value is taken directly
512 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
515 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
516 Description: (Read) Returns the number of special conditional P1 right-hand keys
517 that the trace unit can use (0x194). The value is taken
518 directly from the HW.
520 What: /sys/bus/coresight/devices/etm<N>/ts_source
523 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> or Suzuki K Poulose <suzuki.poulose@arm.com>
524 Description: (Read) When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for
525 trace session. Otherwise -1 indicates an unknown time source. Check
526 trcidr0.tssize to see if a global timestamp is available.