1 .. SPDX-License-Identifier: GPL-2.0
3 ===========================
4 AMD64 Specific Boot Options
5 ===========================
7 There are many others (usually documented in driver documentation), but
8 only the AMD64 specific ones are listed here.
12 Please see Documentation/arch/x86/x86_64/machinecheck.rst for sysfs runtime tunables.
17 Disable CMCI(Corrected Machine Check Interrupt) that
18 Intel processor supports. Usually this disablement is
19 not recommended, but it might be handy if your hardware
21 Note that you'll get more problems without CMCI than with
22 due to the shared banks, i.e. you might get duplicated
25 Don't make logs for corrected errors. All events reported
26 as corrected are silently cleared by OS.
27 This option will be useful if you have no interest in any
30 Disable features for corrected errors, e.g. polling timer
31 and CMCI. All events reported as corrected are not cleared
32 by OS and remained in its error banks.
33 Usually this disablement is not recommended, however if
34 there is an agent checking/clearing corrected errors
35 (e.g. BIOS or hardware monitoring applications), conflicting
36 with OS's error handling, and you cannot deactivate the agent,
37 then this option will be a help.
39 Do not opt-in to Local MCE delivery. Use legacy method
42 Enable logging of machine checks left over from booting.
43 Disabled by default on AMD Fam10h and older because some BIOS
45 If your BIOS doesn't do that it's a good idea to enable though
46 to make sure you log even machine check events that result
47 in a reboot. On Intel systems it is enabled by default.
49 Disable boot machine check logging.
50 mce=monarchtimeout (number)
52 Sets the time in us to wait for other CPUs on machine checks. 0
54 mce=bios_cmci_threshold
55 Don't overwrite the bios-set CMCI threshold. This boot option
56 prevents Linux from overwriting the CMCI threshold set by the
57 bios. Without this option, Linux always sets the CMCI
58 threshold to 1. Enabling this may make memory predictive failure
59 analysis less effective if the bios sets thresholds for memory
60 errors since we will not see details for all errors.
62 Force-enable recoverable machine check code paths
64 nomce (for compatibility with i386)
67 Everything else is in sysfs now.
76 Don't use the IO-APIC.
79 Don't use the local APIC
82 Don't use the local APIC (alias for i386 compatibility)
85 See Documentation/arch/x86/i386/IO-APIC.rst
88 Don't set up the APIC timer
91 Don't check the IO-APIC timer. This can work around
92 problems with incorrect timer initialization on some boards.
95 Do APIC timer calibration using the pmtimer. Implies
96 apicmaintimer. Useful when your PIT timer is totally broken.
102 Deprecated, use tsc=unstable instead.
105 Don't use the HPET timer.
111 Don't do power saving in the idle loop using HLT, but poll for rescheduling
112 event. This will make the CPUs eat a lot more power, but may be useful
113 to get slightly better performance in multiprocessor benchmarks. It also
114 makes some profiling using performance counters more accurate.
115 Please note that on systems with MONITOR/MWAIT support (like Intel EM64T
116 CPUs) this option has no performance advantage over the normal idle loop.
117 It may also interact badly with hyperthreading.
122 reboot=b[ios] | t[riple] | k[bd] | a[cpi] | e[fi] | p[ci] [, [w]arm | [c]old]
124 Use the CPU reboot vector for warm reset
126 Don't set the cold reboot flag
128 Set the cold reboot flag
130 Force a triple fault (init)
132 Use the keyboard controller. cold reset (default)
134 Use the ACPI RESET_REG in the FADT. If ACPI is not configured or
135 the ACPI reset does not work, the reboot path attempts the reset
136 using the keyboard controller.
138 Use efi reset_system runtime service. If EFI is not configured or
139 the EFI reset does not work, the reboot path attempts the reset using
140 the keyboard controller.
142 Use a write to the PCI config space register 0xcf9 to trigger reboot.
144 Using warm reset will be much faster especially on big memory
145 systems because the BIOS will not go through the memory check.
146 Disadvantage is that not all hardware will be completely reinitialized
147 on reboot so there may be boot problems on some systems.
150 Don't stop other CPUs on reboot. This can make reboot more reliable
154 There are some built-in platform specific "quirks" - you may see:
155 "reboot: <name> series board detected. Selecting <type> for reboots."
156 In the case where you think the quirk is in error (e.g. you have
157 newer BIOS, or newer board) using this option will ignore the built-in
158 quirk table, and use the generic default reboot actions.
164 Only set up a single NUMA node spanning all memory.
167 Don't parse the SRAT table for NUMA setup
170 Don't parse the HMAT table for NUMA setup, or soft-reserved memory
179 Use ACPI boot table parsing, but don't enable ACPI interpreter
181 Force ACPI on (currently not needed)
183 Disable out of spec ACPI workarounds.
184 acpi_sci={edge,level,high,low}
185 Set up ACPI SCI interrupt.
187 Don't route interrupts
189 Disable firmware first mode for corrected errors. This
190 disables parsing the HEST CMC error source to check if
191 firmware has set the FF flag. This may result in
192 duplicate corrected error reports.
208 Set PCI interrupt mask to MASK
210 Scan up to NUMBER busses, no matter what the mptable says.
212 Don't use ACPI to set up PCI interrupt routing.
214 IOMMU (input/output memory management unit)
215 ===========================================
216 Multiple x86-64 PCI-DMA mapping implementations exist, for example:
218 1. <kernel/dma/direct.c>: use no hardware/software IOMMU at all
219 (e.g. because you have < 3 GB memory).
220 Kernel boot message: "PCI-DMA: Disabling IOMMU"
222 2. <arch/x86/kernel/amd_gart_64.c>: AMD GART based hardware IOMMU.
223 Kernel boot message: "PCI-DMA: using GART IOMMU"
225 3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used
226 e.g. if there is no hardware IOMMU in the system and it is need because
227 you have >3GB memory or told the kernel to us it (iommu=soft))
228 Kernel boot message: "PCI-DMA: Using software bounce buffering
233 iommu=[<size>][,noagp][,off][,force][,noforce]
234 [,memaper[=<order>]][,merge][,fullflush][,nomerge]
237 General iommu options:
240 Don't initialize and use any kind of IOMMU.
242 Don't force hardware IOMMU usage when it is not needed. (default).
244 Force the use of the hardware IOMMU even when it is
245 not actually needed (e.g. because < 3 GB memory).
247 Use software bounce buffering (SWIOTLB) (default for
248 Intel machines). This can be used to prevent the usage
249 of an available hardware IOMMU.
251 iommu options only relevant to the AMD GART hardware IOMMU:
254 Set the size of the remapping area in bytes.
256 Overwrite iommu off workarounds for specific chipsets.
258 Flush IOMMU on each allocation (default).
260 Don't use IOMMU fullflush.
262 Allocate an own aperture over RAM with size 32MB<<order.
263 (default: order=1, i.e. 64MB)
265 Do scatter-gather (SG) merging. Implies "force" (experimental).
267 Don't do scatter-gather (SG) merging.
269 Ask the IOMMU not to touch the aperture for AGP.
271 Don't initialize the AGP driver and use full aperture.
273 Always panic when IOMMU overflows.
275 iommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU
278 swiotlb=<slots>[,force,noforce]
280 Prereserve that many 2K slots for the software IO bounce buffering.
282 Force all IO through the software TLB.
284 Do not initialize the software TLB.
291 Do not use GB pages for kernel direct mappings.
293 Use GB pages for kernel direct mappings.
296 AMD SEV (Secure Encrypted Virtualization)
297 =========================================
298 Options relating to AMD SEV, specified via the following format:
302 sev=option1[,option2]
304 The available options are:
307 Enable debug messages.
310 Do not enable SEV-SNP (applies to host/hypervisor only). Setting
311 'nosnp' avoids the RMP check overhead in memory accesses when
312 users do not want to run SEV-SNP guests.