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1 MediaTek Gen2 PCIe controller
3 Required properties:
4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
13 - reg-names: Names of the above areas to use during resource lookup.
14 - #address-cells: Address representation for root ports (must be 3)
15 - #size-cells: Size representation for root ports (must be 2)
16 - clocks: Must contain an entry for each entry in clock-names.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names:
19 Mandatory entries:
20 - sys_ckN :transaction layer and data link layer clock
21 Required entries for MT2701/MT7623:
22 - free_ck :for reference clock of PCIe subsys
23 Required entries for MT2712/MT7622:
24 - ahb_ckN :AHB slave interface operating clock for CSR access and RC
25 initiated MMIO access
26 Required entries for MT7622:
27 - axi_ckN :application layer MMIO channel operating clock
28 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
29 pcie_mac_ck/pcie_pipe_ck is turned off
30 - obff_ckN :OBFF functional block operating clock
31 - pipe_ckN :LTSSM and PHY/MAC layer operating clock
32 where N starting from 0 to one less than the number of root ports.
33 - phys: List of PHY specifiers (used by generic PHY framework).
34 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
35 number of PHYs as specified in *phys* property.
36 - power-domains: A phandle and power domain specifier pair to the power domain
37 which is responsible for collapsing and restoring power to the peripheral.
38 - bus-range: Range of bus numbers associated with this controller.
39 - ranges: Ranges for the PCI memory and I/O regions.
41 Required properties for MT7623/MT2701:
42 - #interrupt-cells: Size representation for interrupts (must be 1)
43 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
44 Please refer to the standard PCI bus binding document for a more detailed
45 explanation.
46 - resets: Must contain an entry for each entry in reset-names.
47 See ../reset/reset.txt for details.
48 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
49 number of root ports.
51 Required properties for MT2712/MT7622/MT7629:
52 -interrupts: A list of interrupt outputs of the controller, must have one
53 entry for each PCIe port
54 - interrupt-names: Must include the following entries:
55 - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
56 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
58 In addition, the device tree node must have sub-nodes describing each
59 PCIe port interface, having the following mandatory properties:
61 Required properties:
62 - device_type: Must be "pci"
63 - reg: Only the first four bytes are used to refer to the correct bus number
64 and device number.
65 - #address-cells: Must be 3
66 - #size-cells: Must be 2
67 - #interrupt-cells: Must be 1
68 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
69 Please refer to the standard PCI bus binding document for a more detailed
70 explanation.
71 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
72 property is sufficient.
74 Examples for MT7623:
76 hifsys: syscon@1a000000 {
77 compatible = "mediatek,mt7623-hifsys",
78 "mediatek,mt2701-hifsys",
79 "syscon";
80 reg = <0 0x1a000000 0 0x1000>;
81 #clock-cells = <1>;
82 #reset-cells = <1>;
83 };
85 pcie: pcie@1a140000 {
86 compatible = "mediatek,mt7623-pcie";
87 device_type = "pci";
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89 <0 0x1a142000 0 0x1000>, /* Port0 registers */
90 <0 0x1a143000 0 0x1000>, /* Port1 registers */
91 <0 0x1a144000 0 0x1000>; /* Port2 registers */
92 reg-names = "subsys", "port0", "port1", "port2";
93 #address-cells = <3>;
94 #size-cells = <2>;
95 #interrupt-cells = <1>;
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
100 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
101 <&hifsys CLK_HIFSYS_PCIE0>,
102 <&hifsys CLK_HIFSYS_PCIE1>,
103 <&hifsys CLK_HIFSYS_PCIE2>;
104 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
105 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
106 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
107 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
108 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
109 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
110 <&pcie2_phy PHY_TYPE_PCIE>;
111 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
112 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
113 bus-range = <0x00 0xff>;
114 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
115 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
117 pcie@0,0 {
118 reg = <0x0000 0 0 0 0>;
119 #address-cells = <3>;
120 #size-cells = <2>;
121 #interrupt-cells = <1>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
124 ranges;
125 };
127 pcie@1,0 {
128 reg = <0x0800 0 0 0 0>;
129 #address-cells = <3>;
130 #size-cells = <2>;
131 #interrupt-cells = <1>;
132 interrupt-map-mask = <0 0 0 0>;
133 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
134 ranges;
135 };
137 pcie@2,0 {
138 reg = <0x1000 0 0 0 0>;
139 #address-cells = <3>;
140 #size-cells = <2>;
141 #interrupt-cells = <1>;
142 interrupt-map-mask = <0 0 0 0>;
143 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
144 ranges;
145 };
146 };
148 Examples for MT2712:
150 pcie1: pcie@112ff000 {
151 compatible = "mediatek,mt2712-pcie";
152 device_type = "pci";
153 reg = <0 0x112ff000 0 0x1000>;
154 reg-names = "port1";
155 linux,pci-domain = <1>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-names = "pcie_irq";
160 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
161 <&pericfg CLK_PERI_PCIE1>;
162 clock-names = "sys_ck1", "ahb_ck1";
163 phys = <&u3port1 PHY_TYPE_PCIE>;
164 phy-names = "pcie-phy1";
165 bus-range = <0x00 0xff>;
166 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
167 status = "disabled";
169 #interrupt-cells = <1>;
170 interrupt-map-mask = <0 0 0 7>;
171 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
172 <0 0 0 2 &pcie_intc1 1>,
173 <0 0 0 3 &pcie_intc1 2>,
174 <0 0 0 4 &pcie_intc1 3>;
175 pcie_intc1: interrupt-controller {
176 interrupt-controller;
177 #address-cells = <0>;
178 #interrupt-cells = <1>;
179 };
180 };
182 pcie0: pcie@11700000 {
183 compatible = "mediatek,mt2712-pcie";
184 device_type = "pci";
185 reg = <0 0x11700000 0 0x1000>;
186 reg-names = "port0";
187 linux,pci-domain = <0>;
188 #address-cells = <3>;
189 #size-cells = <2>;
190 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-names = "pcie_irq";
192 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
193 <&pericfg CLK_PERI_PCIE0>;
194 clock-names = "sys_ck0", "ahb_ck0";
195 phys = <&u3port0 PHY_TYPE_PCIE>;
196 phy-names = "pcie-phy0";
197 bus-range = <0x00 0xff>;
198 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
199 status = "disabled";
201 #interrupt-cells = <1>;
202 interrupt-map-mask = <0 0 0 7>;
203 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
204 <0 0 0 2 &pcie_intc0 1>,
205 <0 0 0 3 &pcie_intc0 2>,
206 <0 0 0 4 &pcie_intc0 3>;
207 pcie_intc0: interrupt-controller {
208 interrupt-controller;
209 #address-cells = <0>;
210 #interrupt-cells = <1>;
211 };
212 };
214 Examples for MT7622:
216 pcie0: pcie@1a143000 {
217 compatible = "mediatek,mt7622-pcie";
218 device_type = "pci";
219 reg = <0 0x1a143000 0 0x1000>;
220 reg-names = "port0";
221 linux,pci-domain = <0>;
222 #address-cells = <3>;
223 #size-cells = <2>;
224 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
225 interrupt-names = "pcie_irq";
226 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
227 <&pciesys CLK_PCIE_P0_AHB_EN>,
228 <&pciesys CLK_PCIE_P0_AUX_EN>,
229 <&pciesys CLK_PCIE_P0_AXI_EN>,
230 <&pciesys CLK_PCIE_P0_OBFF_EN>,
231 <&pciesys CLK_PCIE_P0_PIPE_EN>;
232 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
233 "axi_ck0", "obff_ck0", "pipe_ck0";
235 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
236 bus-range = <0x00 0xff>;
237 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
238 status = "disabled";
240 #interrupt-cells = <1>;
241 interrupt-map-mask = <0 0 0 7>;
242 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
243 <0 0 0 2 &pcie_intc0 1>,
244 <0 0 0 3 &pcie_intc0 2>,
245 <0 0 0 4 &pcie_intc0 3>;
246 pcie_intc0: interrupt-controller {
247 interrupt-controller;
248 #address-cells = <0>;
249 #interrupt-cells = <1>;
250 };
251 };
253 pcie1: pcie@1a145000 {
254 compatible = "mediatek,mt7622-pcie";
255 device_type = "pci";
256 reg = <0 0x1a145000 0 0x1000>;
257 reg-names = "port1";
258 linux,pci-domain = <1>;
259 #address-cells = <3>;
260 #size-cells = <2>;
261 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
262 interrupt-names = "pcie_irq";
263 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
264 /* designer has connect RC1 with p0_ahb clock */
265 <&pciesys CLK_PCIE_P0_AHB_EN>,
266 <&pciesys CLK_PCIE_P1_AUX_EN>,
267 <&pciesys CLK_PCIE_P1_AXI_EN>,
268 <&pciesys CLK_PCIE_P1_OBFF_EN>,
269 <&pciesys CLK_PCIE_P1_PIPE_EN>;
270 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
271 "axi_ck1", "obff_ck1", "pipe_ck1";
273 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
274 bus-range = <0x00 0xff>;
275 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
276 status = "disabled";
278 #interrupt-cells = <1>;
279 interrupt-map-mask = <0 0 0 7>;
280 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
281 <0 0 0 2 &pcie_intc1 1>,
282 <0 0 0 3 &pcie_intc1 2>,
283 <0 0 0 4 &pcie_intc1 3>;
284 pcie_intc1: interrupt-controller {
285 interrupt-controller;
286 #address-cells = <0>;
287 #interrupt-cells = <1>;
288 };
289 };