1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (UFS, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
21 - qcom,qcs615-qmp-ufs-phy
22 - const: qcom,sm6115-qmp-ufs-phy
25 - qcom,qcs8300-qmp-ufs-phy
26 - const: qcom,sa8775p-qmp-ufs-phy
28 - qcom,msm8996-qmp-ufs-phy
29 - qcom,msm8998-qmp-ufs-phy
30 - qcom,sa8775p-qmp-ufs-phy
31 - qcom,sc7180-qmp-ufs-phy
32 - qcom,sc7280-qmp-ufs-phy
33 - qcom,sc8180x-qmp-ufs-phy
34 - qcom,sc8280xp-qmp-ufs-phy
35 - qcom,sdm845-qmp-ufs-phy
36 - qcom,sm6115-qmp-ufs-phy
37 - qcom,sm6125-qmp-ufs-phy
38 - qcom,sm6350-qmp-ufs-phy
39 - qcom,sm7150-qmp-ufs-phy
40 - qcom,sm8150-qmp-ufs-phy
41 - qcom,sm8250-qmp-ufs-phy
42 - qcom,sm8350-qmp-ufs-phy
43 - qcom,sm8450-qmp-ufs-phy
44 - qcom,sm8475-qmp-ufs-phy
45 - qcom,sm8550-qmp-ufs-phy
46 - qcom,sm8650-qmp-ufs-phy
96 - qcom,msm8998-qmp-ufs-phy
97 - qcom,sa8775p-qmp-ufs-phy
98 - qcom,sc7180-qmp-ufs-phy
99 - qcom,sc7280-qmp-ufs-phy
100 - qcom,sc8180x-qmp-ufs-phy
101 - qcom,sc8280xp-qmp-ufs-phy
102 - qcom,sdm845-qmp-ufs-phy
103 - qcom,sm6115-qmp-ufs-phy
104 - qcom,sm6125-qmp-ufs-phy
105 - qcom,sm6350-qmp-ufs-phy
106 - qcom,sm7150-qmp-ufs-phy
107 - qcom,sm8150-qmp-ufs-phy
108 - qcom,sm8250-qmp-ufs-phy
109 - qcom,sm8350-qmp-ufs-phy
110 - qcom,sm8450-qmp-ufs-phy
111 - qcom,sm8475-qmp-ufs-phy
112 - qcom,sm8550-qmp-ufs-phy
113 - qcom,sm8650-qmp-ufs-phy
130 - qcom,msm8996-qmp-ufs-phy
146 - qcom,msm8996-qmp-ufs-phy
147 - qcom,msm8998-qmp-ufs-phy
156 additionalProperties: false
160 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
161 #include <dt-bindings/clock/qcom,rpmh.h>
163 ufs_mem_phy: phy@1d87000 {
164 compatible = "qcom,sc8280xp-qmp-ufs-phy";
165 reg = <0x01d87000 0x1000>;
167 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
168 <&gcc GCC_UFS_REF_CLKREF_CLK>;
170 clock-names = "ref", "ref_aux", "qref";
172 power-domains = <&gcc UFS_PHY_GDSC>;
174 resets = <&ufs_mem_hc 0>;
175 reset-names = "ufsphy";
177 vdda-phy-supply = <&vreg_l6b>;
178 vdda-pll-supply = <&vreg_l3b>;