1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 - $ref: dai-common.yaml#
19 - renesas,r9a07g043-ssi # RZ/G2UL and RZ/Five
20 - renesas,r9a07g044-ssi # RZ/G2{L,LC}
21 - renesas,r9a07g054-ssi # RZ/V2L
22 - renesas,r9a08g045-ssi # RZ/G3S
23 - const: renesas,rz-ssi
74 $ref: audio-graph-port.yaml#/definitions/port-base
75 description: Connection to controller providing I2S signals
87 unevaluatedProperties: false
91 #include <dt-bindings/interrupt-controller/arm-gic.h>
92 #include <dt-bindings/clock/r9a07g044-cpg.h>
95 compatible = "renesas,r9a07g044-ssi",
97 reg = <0x10049c00 0x400>;
98 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
100 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
101 interrupt-names = "int_req", "dma_rx", "dma_tx";
102 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
103 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
106 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
107 power-domains = <&cpg>;
108 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
109 dmas = <&dmac 0x2655>,
111 dma-names = "tx", "rx";
112 #sound-dai-cells = <0>;