| blob | acfef063295f354b33083a82c077a58123e464a6 |
1 /*
2 * DaVinci Power & Sleep Controller (PSC) defines
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27 #ifndef __ASM_ARCH_PSC_H
28 #define __ASM_ARCH_PSC_H
30 /* Power and Sleep Controller (PSC) Domains */
31 #define DAVINCI_GPSC_ARMDOMAIN 0
32 #define DAVINCI_GPSC_DSPDOMAIN 1
34 #define DAVINCI_LPSC_VPSSMSTR 0
35 #define DAVINCI_LPSC_VPSSSLV 1
36 #define DAVINCI_LPSC_TPCC 2
37 #define DAVINCI_LPSC_TPTC0 3
38 #define DAVINCI_LPSC_TPTC1 4
39 #define DAVINCI_LPSC_EMAC 5
40 #define DAVINCI_LPSC_EMAC_WRAPPER 6
41 #define DAVINCI_LPSC_USB 9
42 #define DAVINCI_LPSC_ATA 10
43 #define DAVINCI_LPSC_VLYNQ 11
44 #define DAVINCI_LPSC_UHPI 12
45 #define DAVINCI_LPSC_DDR_EMIF 13
46 #define DAVINCI_LPSC_AEMIF 14
47 #define DAVINCI_LPSC_MMC_SD 15
48 #define DAVINCI_LPSC_McBSP 17
49 #define DAVINCI_LPSC_I2C 18
50 #define DAVINCI_LPSC_UART0 19
51 #define DAVINCI_LPSC_UART1 20
52 #define DAVINCI_LPSC_UART2 21
53 #define DAVINCI_LPSC_SPI 22
54 #define DAVINCI_LPSC_PWM0 23
55 #define DAVINCI_LPSC_PWM1 24
56 #define DAVINCI_LPSC_PWM2 25
57 #define DAVINCI_LPSC_GPIO 26
58 #define DAVINCI_LPSC_TIMER0 27
59 #define DAVINCI_LPSC_TIMER1 28
60 #define DAVINCI_LPSC_TIMER2 29
61 #define DAVINCI_LPSC_SYSTEM_SUBSYS 30
62 #define DAVINCI_LPSC_ARM 31
63 #define DAVINCI_LPSC_SCR2 32
64 #define DAVINCI_LPSC_SCR3 33
65 #define DAVINCI_LPSC_SCR4 34
66 #define DAVINCI_LPSC_CROSSBAR 35
67 #define DAVINCI_LPSC_CFG27 36
68 #define DAVINCI_LPSC_CFG3 37
69 #define DAVINCI_LPSC_CFG5 38
70 #define DAVINCI_LPSC_GEM 39
71 #define DAVINCI_LPSC_IMCOP 40
73 /* PSC0 defines */
74 #define DA8XX_LPSC0_TPCC 0
75 #define DA8XX_LPSC0_TPTC0 1
76 #define DA8XX_LPSC0_TPTC1 2
77 #define DA8XX_LPSC0_EMIF25 3
78 #define DA8XX_LPSC0_SPI0 4
79 #define DA8XX_LPSC0_MMC_SD 5
80 #define DA8XX_LPSC0_AINTC 6
81 #define DA8XX_LPSC0_ARM_RAM_ROM 7
82 #define DA8XX_LPSC0_SECU_MGR 8
83 #define DA8XX_LPSC0_UART0 9
84 #define DA8XX_LPSC0_SCR0_SS 10
85 #define DA8XX_LPSC0_SCR1_SS 11
86 #define DA8XX_LPSC0_SCR2_SS 12
87 #define DA8XX_LPSC0_PRUSS 13
88 #define DA8XX_LPSC0_ARM 14
89 #define DA8XX_LPSC0_GEM 15
91 /* PSC1 defines */
92 #define DA850_LPSC1_TPCC1 0
93 #define DA8XX_LPSC1_USB20 1
94 #define DA8XX_LPSC1_USB11 2
95 #define DA8XX_LPSC1_GPIO 3
96 #define DA8XX_LPSC1_UHPI 4
97 #define DA8XX_LPSC1_CPGMAC 5
98 #define DA8XX_LPSC1_EMIF3C 6
99 #define DA8XX_LPSC1_McASP0 7
100 #define DA830_LPSC1_McASP1 8
101 #define DA850_LPSC1_SATA 8
102 #define DA830_LPSC1_McASP2 9
103 #define DA850_LPSC1_VPIF 9
104 #define DA8XX_LPSC1_SPI1 10
105 #define DA8XX_LPSC1_I2C 11
106 #define DA8XX_LPSC1_UART1 12
107 #define DA8XX_LPSC1_UART2 13
108 #define DA850_LPSC1_McBSP0 14
109 #define DA850_LPSC1_McBSP1 15
110 #define DA8XX_LPSC1_LCDC 16
111 #define DA8XX_LPSC1_PWM 17
112 #define DA850_LPSC1_MMC_SD1 18
113 #define DA8XX_LPSC1_ECAP 20
114 #define DA830_LPSC1_EQEP 21
115 #define DA850_LPSC1_TPTC2 21
116 #define DA8XX_LPSC1_SCR_P0_SS 24
117 #define DA8XX_LPSC1_SCR_P1_SS 25
118 #define DA8XX_LPSC1_CR_P3_SS 26
119 #define DA8XX_LPSC1_L3_CBA_RAM 31
121 /* PSC register offsets */
122 #define EPCPR 0x070
123 #define PTCMD 0x120
124 #define PTSTAT 0x128
125 #define PDSTAT 0x200
126 #define PDCTL 0x300
127 #define MDSTAT 0x800
128 #define MDCTL 0xA00
130 /* PSC module states */
131 #define PSC_STATE_SWRSTDISABLE 0
132 #define PSC_STATE_SYNCRST 1
133 #define PSC_STATE_DISABLE 2
134 #define PSC_STATE_ENABLE 3
136 #define MDSTAT_STATE_MASK 0x3f
137 #define PDSTAT_STATE_MASK 0x1f
138 #define MDCTL_LRST BIT(8)
139 #define MDCTL_FORCE BIT(31)
140 #define PDCTL_NEXT BIT(0)
141 #define PDCTL_EPCGOOD BIT(8)