arch/arm/mach-omap1/timer32k.c

   1 /*
   2  * linux/arch/arm/mach-omap1/timer32k.c
   3  *
   4  * OMAP 32K Timer
   5  *
   6  * Copyright (C) 2004 - 2005 Nokia Corporation
   7  * Partial timer rewrite and additional dynamic tick timer support by
   8  * Tony Lindgen <tony@atomide.com> and
   9  * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  * OMAP Dual-mode timer framework support by Timo Teras
  11  *
  12  * MPU timer code based on the older MPU timer code for OMAP
  13  * Copyright (C) 2000 RidgeRun, Inc.
  14  * Author: Greg Lonnon <glonnon@ridgerun.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  24  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * You should have received a copy of the  GNU General Public License along
  33  * with this program; if not, write  to the Free Software Foundation, Inc.,
  34  * 675 Mass Ave, Cambridge, MA 02139, USA.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/delay.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/sched.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/err.h>
  44 #include <linux/clk.h>
  45 #include <linux/clocksource.h>
  46 #include <linux/clockchips.h>
  47 #include <linux/io.h>
  48 #include <linux/sched_clock.h>
  49
  50 #include <asm/irq.h>
  51 #include <asm/mach/irq.h>
  52 #include <asm/mach/time.h>
  53
  54 #include "hardware.h"
  55 #include "common.h"
  56
  57 /*
  58  * ---------------------------------------------------------------------------
  59  * 32KHz OS timer
  60  *
  61  * This currently works only on 16xx, as 1510 does not have the continuous
  62  * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
  63  * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
  64  * on 1510 would be possible, but the timer would not be as accurate as
  65  * with the 32KHz synchronized timer.
  66  * ---------------------------------------------------------------------------
  67  */
  68
  69 /* 16xx specific defines */
  70 #define OMAP1_32K_TIMER_BASE            0xfffb9000
  71 #define OMAP1_32KSYNC_TIMER_BASE        0xfffbc400
  72 #define OMAP1_32K_TIMER_CR              0x08
  73 #define OMAP1_32K_TIMER_TVR             0x00
  74 #define OMAP1_32K_TIMER_TCR             0x04
  75
  76 #define OMAP_32K_TICKS_PER_SEC          (32768)
  77
  78 /*
  79  * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
  80  * so with HZ = 128, TVR = 255.
  81  */
  82 #define OMAP_32K_TIMER_TICK_PERIOD      ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
  83
  84 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate)                     \
  85                                 (((nr_jiffies) * (clock_rate)) / HZ)
  86
  87 static inline void omap_32k_timer_write(int val, int reg)
  88 {
  89         omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
  90 }
  91
  92 static inline void omap_32k_timer_start(unsigned long load_val)
  93 {
  94         if (!load_val)
  95                 load_val = 1;
  96         omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
  97         omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
  98 }
  99
 100 static inline void omap_32k_timer_stop(void)
 101 {
 102         omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
 103 }
 104
 105 #define omap_32k_timer_ack_irq()
 106
 107 static int omap_32k_timer_set_next_event(unsigned long delta,
 108                                          struct clock_event_device *dev)
 109 {
 110         omap_32k_timer_start(delta);
 111
 112         return 0;
 113 }
 114
 115 static int omap_32k_timer_shutdown(struct clock_event_device *evt)
 116 {
 117         omap_32k_timer_stop();
 118         return 0;
 119 }
 120
 121 static int omap_32k_timer_set_periodic(struct clock_event_device *evt)
 122 {
 123         omap_32k_timer_stop();
 124         omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
 125         return 0;
 126 }
 127
 128 static struct clock_event_device clockevent_32k_timer = {
 129         .name                   = "32k-timer",
 130         .features               = CLOCK_EVT_FEAT_PERIODIC |
 131                                   CLOCK_EVT_FEAT_ONESHOT,
 132         .set_next_event         = omap_32k_timer_set_next_event,
 133         .set_state_shutdown     = omap_32k_timer_shutdown,
 134         .set_state_periodic     = omap_32k_timer_set_periodic,
 135         .set_state_oneshot      = omap_32k_timer_shutdown,
 136         .tick_resume            = omap_32k_timer_shutdown,
 137 };
 138
 139 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
 140 {
 141         struct clock_event_device *evt = &clockevent_32k_timer;
 142         omap_32k_timer_ack_irq();
 143
 144         evt->event_handler(evt);
 145
 146         return IRQ_HANDLED;
 147 }
 148
 149 static __init void omap_init_32k_timer(void)
 150 {
 151         if (request_irq(INT_OS_TIMER, omap_32k_timer_interrupt,
 152                         IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL))
 153                 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER);
 154
 155         clockevent_32k_timer.cpumask = cpumask_of(0);
 156         clockevents_config_and_register(&clockevent_32k_timer,
 157                                         OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe);
 158 }
 159
 160 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
 161 #define OMAP2_32KSYNCNT_REV_OFF         0x0
 162 #define OMAP2_32KSYNCNT_REV_SCHEME      (0x3 << 30)
 163 #define OMAP2_32KSYNCNT_CR_OFF_LOW      0x10
 164 #define OMAP2_32KSYNCNT_CR_OFF_HIGH     0x30
 165
 166 /*
 167  * 32KHz clocksource ... always available, on pretty most chips except
 168  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
 169  * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
 170  * but systems won't necessarily want to spend resources that way.
 171  */
 172 static void __iomem *sync32k_cnt_reg;
 173
 174 static u64 notrace omap_32k_read_sched_clock(void)
 175 {
 176         return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
 177 }
 178
 179 static struct timespec64 persistent_ts;
 180 static cycles_t cycles;
 181 static unsigned int persistent_mult, persistent_shift;
 182
 183 /**
 184  * omap_read_persistent_clock64 -  Return time from a persistent clock.
 185  * @ts: &struct timespec64 for the returned time
 186  *
 187  * Reads the time from a source which isn't disabled during PM, the
 188  * 32k sync timer.  Convert the cycles elapsed since last read into
 189  * nsecs and adds to a monotonically increasing timespec64.
 190  */
 191 static void omap_read_persistent_clock64(struct timespec64 *ts)
 192 {
 193         unsigned long long nsecs;
 194         cycles_t last_cycles;
 195
 196         last_cycles = cycles;
 197         cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
 198
 199         nsecs = clocksource_cyc2ns(cycles - last_cycles,
 200                                         persistent_mult, persistent_shift);
 201
 202         timespec64_add_ns(&persistent_ts, nsecs);
 203
 204         *ts = persistent_ts;
 205 }
 206
 207 /**
 208  * omap_init_clocksource_32k - setup and register counter 32k as a
 209  * kernel clocksource
 210  * @vbase: base addr of counter_32k module
 211  *
 212  * Returns: %0 upon success or negative error code upon failure.
 213  *
 214  */
 215 static int __init omap_init_clocksource_32k(void __iomem *vbase)
 216 {
 217         int ret;
 218
 219         /*
 220          * 32k sync Counter IP register offsets vary between the
 221          * highlander version and the legacy ones.
 222          * The 'SCHEME' bits(30-31) of the revision register is used
 223          * to identify the version.
 224          */
 225         if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
 226                                                 OMAP2_32KSYNCNT_REV_SCHEME)
 227                 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
 228         else
 229                 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
 230
 231         /*
 232          * 120000 rough estimate from the calculations in
 233          * __clocksource_update_freq_scale.
 234          */
 235         clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
 236                         32768, NSEC_PER_SEC, 120000);
 237
 238         ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
 239                                 250, 32, clocksource_mmio_readl_up);
 240         if (ret) {
 241                 pr_err("32k_counter: can't register clocksource\n");
 242                 return ret;
 243         }
 244
 245         sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
 246         register_persistent_clock(omap_read_persistent_clock64);
 247         pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
 248
 249         return 0;
 250 }
 251
 252 /*
 253  * ---------------------------------------------------------------------------
 254  * Timer initialization
 255  * ---------------------------------------------------------------------------
 256  */
 257 int __init omap_32k_timer_init(void)
 258 {
 259         int ret = -ENODEV;
 260
 261         if (cpu_is_omap16xx()) {
 262                 void __iomem *base;
 263                 struct clk *sync32k_ick;
 264
 265                 base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K);
 266                 if (!base) {
 267                         pr_err("32k_counter: failed to map base addr\n");
 268                         return -ENODEV;
 269                 }
 270
 271                 sync32k_ick = clk_get(NULL, "omap_32ksync_ick");
 272                 if (!IS_ERR(sync32k_ick))
 273                         clk_prepare_enable(sync32k_ick);
 274
 275                 ret = omap_init_clocksource_32k(base);
 276         }
 277
 278         if (!ret)
 279                 omap_init_32k_timer();
 280
 281         return ret;
 282 }