arch/arm/mach-omap2/clock.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  linux/arch/arm/mach-omap2/clock.c
   4  *
   5  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   6  *  Copyright (C) 2004-2010 Nokia Corporation
   7  *
   8  *  Contacts:
   9  *  Richard Woodruff <r-woodruff2@ti.com>
  10  *  Paul Walmsley
  11  */
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/export.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/delay.h>
  20 #include <linux/clk.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/io.h>
  23 #include <linux/bitops.h>
  24 #include <linux/of_address.h>
  25 #include <asm/cpu.h>
  26
  27 #include <trace/events/power.h>
  28
  29 #include "soc.h"
  30 #include "clockdomain.h"
  31 #include "clock.h"
  32 #include "cm.h"
  33 #include "cm2xxx.h"
  34 #include "cm3xxx.h"
  35 #include "cm-regbits-24xx.h"
  36 #include "cm-regbits-34xx.h"
  37 #include "common.h"
  38
  39 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
  40 #define OMAP3430_DPLL_FINT_BAND1_MIN    750000
  41 #define OMAP3430_DPLL_FINT_BAND1_MAX    2100000
  42 #define OMAP3430_DPLL_FINT_BAND2_MIN    7500000
  43 #define OMAP3430_DPLL_FINT_BAND2_MAX    21000000
  44
  45 /*
  46  * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
  47  * From device data manual section 4.3 "DPLL and DLL Specifications".
  48  */
  49 #define OMAP3PLUS_DPLL_FINT_MIN         32000
  50 #define OMAP3PLUS_DPLL_FINT_MAX         52000000
  51
  52 struct ti_clk_ll_ops omap_clk_ll_ops = {
  53         .clkdm_clk_enable = clkdm_clk_enable,
  54         .clkdm_clk_disable = clkdm_clk_disable,
  55         .clkdm_lookup = clkdm_lookup,
  56         .cm_wait_module_ready = omap_cm_wait_module_ready,
  57         .cm_split_idlest_reg = cm_split_idlest_reg,
  58 };
  59
  60 /**
  61  * omap2_clk_setup_ll_ops - setup clock driver low-level ops
  62  *
  63  * Sets up clock driver low-level platform ops. These are needed
  64  * for register accesses and various other misc platform operations.
  65  * Returns 0 on success, -EBUSY if low level ops have been registered
  66  * already.
  67  */
  68 int __init omap2_clk_setup_ll_ops(void)
  69 {
  70         return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
  71 }
  72
  73 /*
  74  * OMAP2+ specific clock functions
  75  */
  76
  77 /**
  78  * ti_clk_init_features - init clock features struct for the SoC
  79  *
  80  * Initializes the clock features struct based on the SoC type.
  81  */
  82 void __init ti_clk_init_features(void)
  83 {
  84         struct ti_clk_features features = { 0 };
  85         /* Fint setup for DPLLs */
  86         if (cpu_is_omap3430()) {
  87                 features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
  88                 features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
  89                 features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
  90                 features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
  91         } else {
  92                 features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
  93                 features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
  94         }
  95
  96         /* Bypass value setup for DPLLs */
  97         if (cpu_is_omap24xx()) {
  98                 features.dpll_bypass_vals |=
  99                         (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
 100                         (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
 101         } else if (cpu_is_omap34xx()) {
 102                 features.dpll_bypass_vals |=
 103                         (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
 104                         (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
 105         } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
 106                    soc_is_omap54xx() || soc_is_dra7xx()) {
 107                 features.dpll_bypass_vals |=
 108                         (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
 109                         (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
 110                         (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
 111         }
 112
 113         /* Jitter correction only available on OMAP343X */
 114         if (cpu_is_omap343x())
 115                 features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
 116
 117         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 118                 features.flags |= TI_CLK_DEVICE_TYPE_GP;
 119
 120         /* Idlest value for interface clocks.
 121          * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
 122          * 34xx reverses this, just to keep us on our toes
 123          * AM35xx uses both, depending on the module.
 124          */
 125         if (cpu_is_omap24xx())
 126                 features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
 127         else if (cpu_is_omap34xx())
 128                 features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
 129
 130         /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
 131         if (omap_rev() == OMAP3430_REV_ES1_0)
 132                 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
 133
 134         /* Errata I810 for omap5 / dra7 */
 135         if (soc_is_omap54xx() || soc_is_dra7xx())
 136                 features.flags |= TI_CLK_ERRATA_I810;
 137
 138         ti_clk_setup_features(&features);
 139 }