arch/arm/mach-omap2/cm33xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * AM33XX CM offset macros
   4  *
   5  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
   6  * Vaibhav Hiremath <hvaibhav@ti.com>
   7  */
   8
   9 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
  10 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
  11
  12 #include "cm.h"
  13 #include "cm-regbits-33xx.h"
  14 #include "prcm-common.h"
  15
  16 /* CM base address */
  17 #define AM33XX_CM_BASE          0x44e00000
  18
  19 #define AM33XX_CM_REGADDR(inst, reg)                            \
  20         AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
  21
  22 /* CM instances */
  23 #define AM33XX_CM_PER_MOD               0x0000
  24 #define AM33XX_CM_WKUP_MOD              0x0400
  25 #define AM33XX_CM_DPLL_MOD              0x0500
  26 #define AM33XX_CM_MPU_MOD               0x0600
  27 #define AM33XX_CM_DEVICE_MOD            0x0700
  28 #define AM33XX_CM_RTC_MOD               0x0800
  29 #define AM33XX_CM_GFX_MOD               0x0900
  30 #define AM33XX_CM_CEFUSE_MOD            0x0A00
  31
  32 /* CM.PER_CM register offsets */
  33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET             0x0000
  34 #define AM33XX_CM_PER_L4LS_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
  35 #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET              0x0004
  36 #define AM33XX_CM_PER_L3S_CLKSTCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
  37 #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET             0x0008
  38 #define AM33XX_CM_PER_L4FW_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
  39 #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET               0x000c
  40 #define AM33XX_CM_PER_L3_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
  41 #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET               0x0028
  42 #define AM33XX_CM_PER_EMIF_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
  43 #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET             0x011c
  44 #define AM33XX_CM_PER_L4HS_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
  45 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET         0x012c
  46 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL                AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
  47 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET            0x0140
  48 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
  49 #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET             0x0144
  50 #define AM33XX_CM_PER_CPSW_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
  51 #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET             0x0148
  52 #define AM33XX_CM_PER_LCDC_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
  53 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET        0x0150
  54 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL               AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
  55
  56 /* CM.WKUP_CM register offsets */
  57 #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET                 0x0000
  58 #define AM33XX_CM_WKUP_CLKSTCTRL                        AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
  59 #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET               0x0018
  60 #define AM33XX_CM_L3_AON_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
  61 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET          0x00cc
  62 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
  63
  64 /* CM.DPLL_CM register offsets */
  65 #define AM33XX_CLKSEL_GFX_FCLK                          AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
  66
  67 /* CM.MPU_CM register offsets */
  68 #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET                  0x0000
  69 #define AM33XX_CM_MPU_CLKSTCTRL                         AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
  70 #define AM33XX_CM_MPU_MPU_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
  71
  72 /* CM.DEVICE_CM register offsets */
  73
  74 /* CM.RTC_CM register offsets */
  75 #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET                  0x0004
  76 #define AM33XX_CM_RTC_CLKSTCTRL                         AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
  77
  78 /* CM.GFX_CM register offsets */
  79 #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET               0x0000
  80 #define AM33XX_CM_GFX_L3_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
  81 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET      0x000c
  82 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1             AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
  83
  84 /* CM.CEFUSE_CM register offsets */
  85 #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET               0x0000
  86 #define AM33XX_CM_CEFUSE_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
  87
  88
  89 #ifndef __ASSEMBLER__
  90 int am33xx_cm_init(const struct omap_prcm_init_data *data);
  91 #endif /* ASSEMBLER */
  92 #endif