| blob | 79860b23030de3dea5fa5e2627b7f10ca3945fa5 |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * OMAP2/3 System Control Module register access
4 *
5 * Copyright (C) 2007, 2012 Texas Instruments, Inc.
6 * Copyright (C) 2007 Nokia Corporation
7 *
8 * Written by Paul Walmsley
9 */
10 #undef DEBUG
12 #include <linux/kernel.h>
13 #include <linux/io.h>
14 #include <linux/of_address.h>
15 #include <linux/regmap.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/cpu_pm.h>
31 /* Used by omap3_ctrl_save_padconf() */
32 #define START_PADCONF_SAVE 0x2
33 #define PADCONF_SAVE_DONE 0x1
38 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
40 u32 boot_config_ptr;
41 u32 public_restore_ptr;
42 u32 secure_ram_restore_ptr;
43 u32 sdrc_module_semaphore;
44 u32 prcm_block_offset;
45 u32 sdrc_block_offset;
46 };
51 u32 prcm_block_size;
52 };
55 u16 sysconfig;
56 u16 cs_cfg;
57 u16 sharing;
58 u16 err_type;
59 u32 dll_a_ctrl;
60 u32 dll_b_ctrl;
61 u32 power;
62 u32 cs_0;
63 u32 mcfg_0;
64 u16 mr_0;
65 u16 emr_1_0;
66 u16 emr_2_0;
67 u16 emr_3_0;
68 u32 actim_ctrla_0;
69 u32 actim_ctrlb_0;
70 u32 rfr_ctrl_0;
71 u32 cs_1;
72 u32 mcfg_1;
73 u16 mr_1;
74 u16 emr_1_1;
75 u16 emr_2_1;
76 u16 emr_3_1;
77 u32 actim_ctrla_1;
78 u32 actim_ctrlb_1;
79 u32 rfr_ctrl_1;
80 u16 dcdl_1_ctrl;
81 u16 dcdl_2_ctrl;
82 u32 flags;
83 u32 block_size;
84 };
88 /*
89 * This is used to store ARM registers in SDRAM before attempting
90 * an MPU OFF. The save and restore happens from the SRAM sleep code.
91 * The address is stored in scratchpad, so that it can be used
92 * during the restore path.
93 */
97 u32 sysconfig;
98 u32 devconf0;
99 u32 mem_dftrw0;
100 u32 mem_dftrw1;
101 u32 msuspendmux_0;
102 u32 msuspendmux_1;
103 u32 msuspendmux_2;
104 u32 msuspendmux_3;
105 u32 msuspendmux_4;
106 u32 msuspendmux_5;
107 u32 sec_ctrl;
108 u32 devconf1;
109 u32 csirxfe;
110 u32 iva2_bootaddr;
111 u32 iva2_bootmod;
112 u32 wkup_ctrl;
113 u32 debobs_0;
114 u32 debobs_1;
115 u32 debobs_2;
116 u32 debobs_3;
117 u32 debobs_4;
118 u32 debobs_5;
119 u32 debobs_6;
120 u32 debobs_7;
121 u32 debobs_8;
122 u32 prog_io0;
123 u32 prog_io1;
124 u32 dss_dpll_spreading;
125 u32 core_dpll_spreading;
126 u32 per_dpll_spreading;
127 u32 usbhost_dpll_spreading;
128 u32 pbias_lite;
129 u32 temp_sensor;
130 u32 sramldo4;
131 u32 sramldo5;
132 u32 csi;
133 u32 padconf_sys_nirq;
134 };
140 {
141 u32 val;
147 }
150 {
151 u32 val;
157 }
160 {
164 }
167 {
168 u32 tmp;
177 }
180 {
181 u32 tmp;
190 }
193 {
196 }
198 #ifdef CONFIG_ARCH_OMAP3
200 /**
201 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
202 * @bootmode: 8-bit value to pass to some boot code
203 *
204 * Set the bootmode in the scratchpad RAM. This is used after the
205 * system restarts. Not sure what actually uses this - it may be the
206 * bootloader, rather than the boot ROM - contrary to the preserved
207 * comment below. No return value.
208 */
210 {
211 u32 l;
215 /*
216 * Reserve the first word in scratchpad for communicating
217 * with the boot ROM. A pointer to a data structure
218 * describing the boot process can be stored there,
219 * cf. OMAP34xx TRM, Initialization / Software Booting
220 * Configuration.
221 *
222 * XXX This should use some omap_ctrl_writel()-type function
223 */
225 }
227 #endif
229 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
230 /* Populate the scratchpad structure with restore structure */
232 {
234 u32 arm_context_addr;
239 /*
240 * Populate the Scratchpad contents
241 *
242 * The "get_*restore_pointer" functions are used to provide a
243 * physical restore address where the ROM code jumps while waking
244 * up from MPU OFF/OSWR state.
245 * The restore pointer is stored into the scratchpad.
246 */
256 else
262 else
269 /* Populate the PRCM block contents */
275 /* Populate the SDRC block contents */
286 /*
287 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
288 * be programed to issue automatic self refresh on timeout
289 * of AUTO_CNT = 1 prior to any transition to OFF mode.
290 */
295 SDRC_POWER_CLKCTRL_MASK)) |
297 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
298 else
332 /* Copy all the contents to the scratchpad location */
336 /* Scratchpad contents being 32 bits, a divide by 4 done here */
343 /*
344 * Copies the address of the location in SDRAM where ARM
345 * registers get saved during a MPU OFF transition.
346 */
350 }
353 {
408 }
411 {
415 OMAP343X_CONTROL_MEM_DFTRW0);
417 OMAP343X_CONTROL_MEM_DFTRW1);
419 OMAP2_CONTROL_MSUSPENDMUX_0);
421 OMAP2_CONTROL_MSUSPENDMUX_1);
423 OMAP2_CONTROL_MSUSPENDMUX_2);
425 OMAP2_CONTROL_MSUSPENDMUX_3);
427 OMAP2_CONTROL_MSUSPENDMUX_4);
429 OMAP2_CONTROL_MSUSPENDMUX_5);
434 OMAP343X_CONTROL_IVA2_BOOTADDR);
436 OMAP343X_CONTROL_IVA2_BOOTMOD);
450 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
452 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
454 OMAP343X_CONTROL_PER_DPLL_SPREADING);
456 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
458 OMAP343X_CONTROL_PBIAS_LITE);
460 OMAP343X_CONTROL_TEMP_SENSOR);
465 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
466 }
469 {
473 }
475 /**
476 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
477 *
478 * Tell the SCM to start saving the padconf registers, then wait for
479 * the process to complete. Returns 0 unconditionally, although it
480 * should also eventually be able to return -ETIMEDOUT, if the save
481 * does not complete.
482 *
483 * XXX This function is missing a timeout. What should it be?
484 */
486 {
487 u32 cpo;
489 /* Save the padconf registers */
494 /* wait for the save to complete */
500 }
502 /**
503 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
504 *
505 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
506 * force disable IVA2 so that it does not prevent any low-power states.
507 */
509 {
511 OMAP343X_CONTROL_IVA2_BOOTMOD);
512 }
514 /**
515 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
516 *
517 * Sets up the pads controlling the stacked modem in such way that the
518 * device can enter idle.
519 */
521 {
524 /*
525 * In a stand alone OMAP3430 where there is not a stacked
526 * modem for the D2D Idle Ack and D2D MStandby must be pulled
527 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
528 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
529 */
538 }
540 /**
541 * omap3_ctrl_init - does static initializations for control module
542 *
543 * Initializes system control module. This sets up the sysconfig autoidle,
544 * and sets up modem and iva2 so that they can be idled properly.
545 */
547 {
553 }
557 AM33XX_CONTROL_SYSCONFIG_OFFSET,
558 AM33XX_CONTROL_STATUS_OFFSET,
559 AM43XX_CONTROL_MPU_L2_CTRL_OFFSET,
560 AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET,
561 AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET,
562 AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET,
563 AM33XX_CONTROL_BANDGAP_CTRL_OFFSET,
564 AM33XX_CONTROL_BANDGAP_TRIM_OFFSET,
565 AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET,
566 AM33XX_CONTROL_MOSC_CTRL_OFFSET,
567 AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET,
568 AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET,
569 AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET,
570 AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET,
571 AM33XX_CONTROL_TPTC_CFG_OFFSET,
572 AM33XX_CONTROL_USB_CTRL0_OFFSET,
573 AM33XX_CONTROL_USB_CTRL1_OFFSET,
574 AM43XX_CONTROL_USB_CTRL2_OFFSET,
575 AM43XX_CONTROL_GMII_SEL_OFFSET,
576 AM43XX_CONTROL_MPUSS_CTRL_OFFSET,
577 AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET,
578 AM43XX_CONTROL_PWMSS_CTRL_OFFSET,
579 AM33XX_CONTROL_MREQPRIO_0_OFFSET,
580 AM33XX_CONTROL_MREQPRIO_1_OFFSET,
581 AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET,
582 AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET,
583 AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET,
584 AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET,
585 AM33XX_CONTROL_SMRT_CTRL_OFFSET,
586 AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET,
587 AM43XX_CONTROL_CQDETECT_STS_OFFSET,
588 AM43XX_CONTROL_CQDETECT_STS2_OFFSET,
589 AM43XX_CONTROL_VTP_CTRL_OFFSET,
590 AM33XX_CONTROL_VREF_CTRL_OFFSET,
591 AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET,
592 AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET,
593 AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET,
594 AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET,
595 AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET,
596 AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET,
597 AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET,
598 AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET,
599 AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET,
600 AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET,
601 AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET,
602 AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET,
603 AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET,
604 AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET,
605 AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET,
606 AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET,
607 AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET,
608 AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET,
609 AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET,
610 AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET,
611 AM33XX_CONTROL_RESET_ISO_OFFSET,
612 };
616 /**
617 * am43xx_control_save_context - Save the wakeup domain registers
618 *
619 * Save the wkup domain registers
620 */
622 {
628 }
630 /**
631 * am43xx_control_restore_context - Restore the wakeup domain registers
632 *
633 * Restore the wkup domain registers
634 */
636 {
642 }
645 {
655 }
658 }
663 s16 offset;
664 };
668 };
673 };
677 };
690 { }
691 };
693 /**
694 * omap2_control_base_init - initialize iomappings for the control driver
695 *
696 * Detects and initializes the iomappings for the control driver, based
697 * on the DT data. Returns 0 in success, negative error value
698 * otherwise.
699 */
701 {
714 }
719 }
722 }
725 }
727 /**
728 * omap_control_init - low level init for the control driver
729 *
730 * Initializes the low level clock infrastructure for control driver.
731 * Returns 0 in success, negative error value in failure.
732 */
734 {
745 /*
746 * Check if we have scm_conf node, if yes, use this to
747 * access clock registers.
748 */
757 }
765 }
767 /* No scm_conf found, direct access */
772 }
773 }
775 /* Only AM43XX can lose ctrl registers context during rtc-ddr suspend */
779 }
783 of_node_put:
787 }