| blob | a70c47cfa6bcb5e2fe99f476555661569bfaaad0 |
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * IRQ definitions for Orion SoC
4 *
5 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
6 */
8 #ifndef __ASM_ARCH_IRQS_H
9 #define __ASM_ARCH_IRQS_H
11 /*
12 * Orion Main Interrupt Controller
13 */
14 #define IRQ_ORION5X_BRIDGE (1 + 0)
15 #define IRQ_ORION5X_DOORBELL_H2C (1 + 1)
16 #define IRQ_ORION5X_DOORBELL_C2H (1 + 2)
17 #define IRQ_ORION5X_UART0 (1 + 3)
18 #define IRQ_ORION5X_UART1 (1 + 4)
19 #define IRQ_ORION5X_I2C (1 + 5)
20 #define IRQ_ORION5X_GPIO_0_7 (1 + 6)
21 #define IRQ_ORION5X_GPIO_8_15 (1 + 7)
22 #define IRQ_ORION5X_GPIO_16_23 (1 + 8)
23 #define IRQ_ORION5X_GPIO_24_31 (1 + 9)
24 #define IRQ_ORION5X_PCIE0_ERR (1 + 10)
25 #define IRQ_ORION5X_PCIE0_INT (1 + 11)
26 #define IRQ_ORION5X_USB1_CTRL (1 + 12)
27 #define IRQ_ORION5X_DEV_BUS_ERR (1 + 14)
28 #define IRQ_ORION5X_PCI_ERR (1 + 15)
29 #define IRQ_ORION5X_USB_BR_ERR (1 + 16)
30 #define IRQ_ORION5X_USB0_CTRL (1 + 17)
31 #define IRQ_ORION5X_ETH_RX (1 + 18)
32 #define IRQ_ORION5X_ETH_TX (1 + 19)
33 #define IRQ_ORION5X_ETH_MISC (1 + 20)
34 #define IRQ_ORION5X_ETH_SUM (1 + 21)
35 #define IRQ_ORION5X_ETH_ERR (1 + 22)
36 #define IRQ_ORION5X_IDMA_ERR (1 + 23)
37 #define IRQ_ORION5X_IDMA_0 (1 + 24)
38 #define IRQ_ORION5X_IDMA_1 (1 + 25)
39 #define IRQ_ORION5X_IDMA_2 (1 + 26)
40 #define IRQ_ORION5X_IDMA_3 (1 + 27)
41 #define IRQ_ORION5X_CESA (1 + 28)
42 #define IRQ_ORION5X_SATA (1 + 29)
43 #define IRQ_ORION5X_XOR0 (1 + 30)
44 #define IRQ_ORION5X_XOR1 (1 + 31)
46 /*
47 * Orion General Purpose Pins
48 */
49 #define IRQ_ORION5X_GPIO_START 33
50 #define NR_GPIO_IRQS 32
52 #define ORION5X_NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
55 #endif