2 * Low-level PXA250/210 sleep/wakeUp support
5 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
7 * Adapted for PXA by Nicolas Pitre:
8 * Copyright (c) 2002 Monta Vista Software, Inc.
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License.
14 #include <linux/linkage.h>
15 #include <asm/assembler.h>
17 #include "pxa2xx-regs.h"
19 #define MDREFR_KDIV 0x200a4000 // all banks
20 #define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
21 #define CCCR_N_MASK 0x00000380
22 #define CCCR_M_MASK 0x00000060
23 #define CCCR_L_MASK 0x0000001f
28 * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
30 ENTRY(pxa3xx_finish_suspend)
31 mov r0, #0x06 @ S2D3C4 mode
32 mcr p14, 0, r0, c7, c0, 0 @ enter sleep
34 20: b 20b @ waiting for sleep
35 #endif /* CONFIG_PXA3xx */
39 * pxa27x_finish_suspend()
41 * Forces CPU into sleep state.
43 * r0 = value for PWRMODE M field for desired sleep state
45 ENTRY(pxa27x_finish_suspend)
46 @ Put the processor to sleep
47 @ (also workaround for sighting 28071)
49 @ prepare value for sleep mode
50 mov r1, r0 @ sleep mode
52 @ prepare pointer to physical address 0 (virtual mapping in generic.c)
53 mov r2, #UNCACHED_PHYS_0
55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
60 orr r5, r5, #MDREFR_SLFRSH
62 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
66 @ Intel PXA270 Specification Update notes problems sleeping
67 @ with core operating above 91 MHz
68 @ (see Errata 50, ...processor does not exit from sleep...)
71 ldr r8, [r6] @ keep original value for resume
73 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
74 mov r0, #0x2 @ prepare value for CLKCFG
76 @ align execution to a cache line
82 * pxa25x_finish_suspend()
84 * Forces CPU into sleep state.
86 * r0 = value for PWRMODE M field for desired sleep state
89 ENTRY(pxa25x_finish_suspend)
90 @ prepare value for sleep mode
91 mov r1, r0 @ sleep mode
93 @ prepare pointer to physical address 0 (virtual mapping in generic.c)
94 mov r2, #UNCACHED_PHYS_0
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
101 orr r5, r5, #MDREFR_SLFRSH
103 @ Intel PXA255 Specification Update notes problems
104 @ about suspending with PXBus operating above 133MHz
105 @ (see Errata 31, GPIO output signals, ... unpredictable in sleep
107 @ We keep the change-down close to the actual suspend on SDRAM
108 @ as possible to eliminate messing about with the refresh clock
109 @ as the system will restore with the original speed settings
111 @ Ben Dooks, 13-Sep-2004
114 ldr r8, [r6] @ keep original value for resume
116 @ ensure x1 for run and turbo mode with memory clock
117 bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK
118 orr r7, r7, #(1<<5) | (2<<7)
120 @ check that the memory frequency is within limits
121 and r14, r7, #CCCR_L_MASK
123 bicne r7, r7, #CCCR_L_MASK
124 orrne r7, r7, #1 @@ 99.53MHz
126 @ get ready for the change
128 @ note, turbo is not preserved over sleep so there is no
129 @ point in preserving it here. we save it on the stack with the
130 @ other CP registers instead.
132 mcr p14, 0, r0, c6, c0, 0
133 orr r0, r0, #2 @ initiate change bit
141 @ All needed values are now in registers.
142 @ These last instructions should be in cache
144 @ initiate the frequency change...
146 mcr p14, 0, r0, c6, c0, 0
148 @ restore the original cpu speed value for resume
151 @ need 6 13-MHz cycles before changing PWRMODE
152 @ just set frequency to 91-MHz... 6*91/13 = 42
159 @ Intel PXA270 Specification Update notes problems performing
160 @ external accesses after SDRAM is put in self-refresh mode
161 @ (see Errata 38 ...hangs when entering self-refresh mode)
163 @ force address lines low by reading at physical address 0
166 @ put SDRAM into self-refresh
170 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
172 20: b 20b @ loop waiting for sleep