1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/plat-spear/time.c
5 * Copyright (C) 2010 ST Microelectronics
6 * Shiraz Hashim<shiraz.linux.kernel@gmail.com>
10 #include <linux/clockchips.h>
11 #include <linux/clocksource.h>
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
17 #include <linux/kernel.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
20 #include <linux/time.h>
21 #include <linux/irq.h>
22 #include <asm/mach/time.h>
26 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
27 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
28 * they share same functional clock. Any change in one's functional clock will
29 * also affect other timer.
32 #define CLKEVT 0 /* gpt0, channel0 as clockevent */
33 #define CLKSRC 1 /* gpt0, channel1 as clocksource */
35 /* Register offsets, x is channel number */
36 #define CR(x) ((x) * 0x80 + 0x80)
37 #define IR(x) ((x) * 0x80 + 0x84)
38 #define LOAD(x) ((x) * 0x80 + 0x88)
39 #define COUNT(x) ((x) * 0x80 + 0x8C)
41 /* Reg bit definitions */
42 #define CTRL_INT_ENABLE 0x0100
43 #define CTRL_ENABLE 0x0020
44 #define CTRL_ONE_SHOT 0x0010
46 #define CTRL_PRESCALER1 0x0
47 #define CTRL_PRESCALER2 0x1
48 #define CTRL_PRESCALER4 0x2
49 #define CTRL_PRESCALER8 0x3
50 #define CTRL_PRESCALER16 0x4
51 #define CTRL_PRESCALER32 0x5
52 #define CTRL_PRESCALER64 0x6
53 #define CTRL_PRESCALER128 0x7
54 #define CTRL_PRESCALER256 0x8
56 #define INT_STATUS 0x1
59 * Minimum clocksource/clockevent timer range in seconds
61 #define SPEAR_MIN_RANGE 4
63 static __iomem
void *gpt_base
;
64 static struct clk
*gpt_clk
;
66 static int clockevent_next_event(unsigned long evt
,
67 struct clock_event_device
*clk_event_dev
);
69 static void __init
spear_clocksource_init(void)
74 /* program the prescaler (/256)*/
75 writew(CTRL_PRESCALER256
, gpt_base
+ CR(CLKSRC
));
77 /* find out actual clock driving Timer */
78 tick_rate
= clk_get_rate(gpt_clk
);
79 tick_rate
>>= CTRL_PRESCALER256
;
81 writew(0xFFFF, gpt_base
+ LOAD(CLKSRC
));
83 val
= readw(gpt_base
+ CR(CLKSRC
));
84 val
&= ~CTRL_ONE_SHOT
; /* autoreload mode */
86 writew(val
, gpt_base
+ CR(CLKSRC
));
88 /* register the clocksource */
89 clocksource_mmio_init(gpt_base
+ COUNT(CLKSRC
), "tmr1", tick_rate
,
90 200, 16, clocksource_mmio_readw_up
);
93 static inline void spear_timer_shutdown(struct clock_event_device
*evt
)
95 u16 val
= readw(gpt_base
+ CR(CLKEVT
));
99 writew(val
, gpt_base
+ CR(CLKEVT
));
102 static int spear_shutdown(struct clock_event_device
*evt
)
104 spear_timer_shutdown(evt
);
109 static int spear_set_oneshot(struct clock_event_device
*evt
)
114 spear_timer_shutdown(evt
);
116 val
= readw(gpt_base
+ CR(CLKEVT
));
117 val
|= CTRL_ONE_SHOT
;
118 writew(val
, gpt_base
+ CR(CLKEVT
));
123 static int spear_set_periodic(struct clock_event_device
*evt
)
129 spear_timer_shutdown(evt
);
131 period
= clk_get_rate(gpt_clk
) / HZ
;
132 period
>>= CTRL_PRESCALER16
;
133 writew(period
, gpt_base
+ LOAD(CLKEVT
));
135 val
= readw(gpt_base
+ CR(CLKEVT
));
136 val
&= ~CTRL_ONE_SHOT
;
137 val
|= CTRL_ENABLE
| CTRL_INT_ENABLE
;
138 writew(val
, gpt_base
+ CR(CLKEVT
));
143 static struct clock_event_device clkevt
= {
145 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
146 .set_state_shutdown
= spear_shutdown
,
147 .set_state_periodic
= spear_set_periodic
,
148 .set_state_oneshot
= spear_set_oneshot
,
149 .tick_resume
= spear_shutdown
,
150 .set_next_event
= clockevent_next_event
,
151 .shift
= 0, /* to be computed */
154 static int clockevent_next_event(unsigned long cycles
,
155 struct clock_event_device
*clk_event_dev
)
157 u16 val
= readw(gpt_base
+ CR(CLKEVT
));
159 if (val
& CTRL_ENABLE
)
160 writew(val
& ~CTRL_ENABLE
, gpt_base
+ CR(CLKEVT
));
162 writew(cycles
, gpt_base
+ LOAD(CLKEVT
));
164 val
|= CTRL_ENABLE
| CTRL_INT_ENABLE
;
165 writew(val
, gpt_base
+ CR(CLKEVT
));
170 static irqreturn_t
spear_timer_interrupt(int irq
, void *dev_id
)
172 struct clock_event_device
*evt
= &clkevt
;
174 writew(INT_STATUS
, gpt_base
+ IR(CLKEVT
));
176 evt
->event_handler(evt
);
181 static void __init
spear_clockevent_init(int irq
)
185 /* program the prescaler */
186 writew(CTRL_PRESCALER16
, gpt_base
+ CR(CLKEVT
));
188 tick_rate
= clk_get_rate(gpt_clk
);
189 tick_rate
>>= CTRL_PRESCALER16
;
191 clkevt
.cpumask
= cpumask_of(0);
193 clockevents_config_and_register(&clkevt
, tick_rate
, 3, 0xfff0);
195 if (request_irq(irq
, spear_timer_interrupt
, IRQF_TIMER
, "timer", NULL
))
196 pr_err("Failed to request irq %d (timer)\n", irq
);
199 static const struct of_device_id timer_of_match
[] __initconst
= {
200 { .compatible
= "st,spear-timer", },
204 void __init
spear_setup_of_timer(void)
206 struct device_node
*np
;
209 np
= of_find_matching_node(NULL
, timer_of_match
);
211 pr_err("%s: No timer passed via DT\n", __func__
);
215 irq
= irq_of_parse_and_map(np
, 0);
217 pr_err("%s: No irq passed for timer via DT\n", __func__
);
221 gpt_base
= of_iomap(np
, 0);
223 pr_err("%s: of iomap failed\n", __func__
);
227 gpt_clk
= clk_get_sys("gpt0", NULL
);
228 if (IS_ERR(gpt_clk
)) {
229 pr_err("%s:couldn't get clk for gpt\n", __func__
);
233 ret
= clk_prepare_enable(gpt_clk
);
235 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__
);
236 goto err_prepare_enable_clk
;
241 spear_clockevent_init(irq
);
242 spear_clocksource_init();
246 err_prepare_enable_clk
: