| blob | 64f031bf6eff5a5c6f733fde9abbc94bb1a9047d |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
4 *
5 * Copyright (C) 2000 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 *
9 * These are the low level assembler for performing cache and TLB
10 * functions on the arm1020e.
11 */
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <linux/cfi_types.h>
15 #include <linux/pgtable.h>
16 #include <asm/assembler.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/hwcap.h>
19 #include <asm/pgtable-hwdef.h>
20 #include <asm/ptrace.h>
22 #include "proc-macros.S"
24 /*
25 * This is the maximum size of an area which will be invalidated
26 * using the single invalidate entry instructions. Anything larger
27 * than this, and we go for the whole cache.
28 *
29 * This value should be chosen such that we choose the cheapest
30 * alternative.
31 */
32 #define MAX_AREA_SIZE 32768
34 /*
35 * The size of one data cache line.
36 */
37 #define CACHE_DLINESIZE 32
39 /*
40 * The number of data cache segments.
41 */
42 #define CACHE_DSEGMENTS 16
44 /*
45 * The number of lines in a cache segment.
46 */
47 #define CACHE_DENTRIES 64
49 /*
50 * This is the size at which it becomes more efficient to
51 * clean the whole cache, rather than using the individual
52 * cache line maintenance instructions.
53 */
54 #define CACHE_DLIMIT 32768
56 .text
57 /*
58 * cpu_arm1020e_proc_init()
59 */
60 SYM_TYPED_FUNC_START(cpu_arm1020e_proc_init)
61 ret lr
62 SYM_FUNC_END(cpu_arm1020e_proc_init)
64 /*
65 * cpu_arm1020e_proc_fin()
66 */
67 SYM_TYPED_FUNC_START(cpu_arm1020e_proc_fin)
68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 bic r0, r0, #0x1000 @ ...i............
70 bic r0, r0, #0x000e @ ............wca.
71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 ret lr
73 SYM_FUNC_END(cpu_arm1020e_proc_fin)
75 /*
76 * cpu_arm1020e_reset(loc)
77 *
78 * Perform a soft reset of the system. Put the CPU into the
79 * same state as it would be if it had been reset, and branch
80 * to what would be the reset vector.
81 *
82 * loc: location to jump to for soft reset
83 */
84 .align 5
85 .pushsection .idmap.text, "ax"
86 SYM_TYPED_FUNC_START(cpu_arm1020e_reset)
87 mov ip, #0
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
90 #ifdef CONFIG_MMU
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
92 #endif
93 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
94 bic ip, ip, #0x000f @ ............wcam
95 bic ip, ip, #0x1100 @ ...i...s........
96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
97 ret r0
98 SYM_FUNC_END(cpu_arm1020e_reset)
99 .popsection
101 /*
102 * cpu_arm1020e_do_idle()
103 */
104 .align 5
105 SYM_TYPED_FUNC_START(cpu_arm1020e_do_idle)
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
107 ret lr
108 SYM_FUNC_END(cpu_arm1020e_do_idle)
110 /* ================================= CACHE ================================ */
112 .align 5
114 /*
115 * flush_icache_all()
116 *
117 * Unconditionally clean and invalidate the entire icache.
118 */
119 SYM_TYPED_FUNC_START(arm1020e_flush_icache_all)
120 #ifndef CONFIG_CPU_ICACHE_DISABLE
121 mov r0, #0
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
123 #endif
124 ret lr
125 SYM_FUNC_END(arm1020e_flush_icache_all)
127 /*
128 * flush_user_cache_all()
129 *
130 * Invalidate all cache entries in a particular address
131 * space.
132 */
133 SYM_FUNC_ALIAS(arm1020e_flush_user_cache_all, arm1020e_flush_kern_cache_all)
135 /*
136 * flush_kern_cache_all()
137 *
138 * Clean and invalidate the entire cache.
139 */
140 SYM_TYPED_FUNC_START(arm1020e_flush_kern_cache_all)
141 mov r2, #VM_EXEC
142 mov ip, #0
143 __flush_whole_cache:
144 #ifndef CONFIG_CPU_DCACHE_DISABLE
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
146 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
147 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
149 subs r3, r3, #1 << 26
150 bcs 2b @ entries 63 to 0
151 subs r1, r1, #1 << 5
152 bcs 1b @ segments 15 to 0
153 #endif
154 tst r2, #VM_EXEC
155 #ifndef CONFIG_CPU_ICACHE_DISABLE
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 #endif
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
159 ret lr
160 SYM_FUNC_END(arm1020e_flush_kern_cache_all)
162 /*
163 * flush_user_cache_range(start, end, flags)
164 *
165 * Invalidate a range of cache entries in the specified
166 * address space.
167 *
168 * - start - start address (inclusive)
169 * - end - end address (exclusive)
170 * - flags - vm_flags for this space
171 */
172 SYM_TYPED_FUNC_START(arm1020e_flush_user_cache_range)
173 mov ip, #0
174 sub r3, r1, r0 @ calculate total size
175 cmp r3, #CACHE_DLIMIT
176 bhs __flush_whole_cache
178 #ifndef CONFIG_CPU_DCACHE_DISABLE
179 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
180 add r0, r0, #CACHE_DLINESIZE
181 cmp r0, r1
182 blo 1b
183 #endif
184 tst r2, #VM_EXEC
185 #ifndef CONFIG_CPU_ICACHE_DISABLE
186 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
187 #endif
188 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
189 ret lr
190 SYM_FUNC_END(arm1020e_flush_user_cache_range)
192 /*
193 * coherent_kern_range(start, end)
194 *
195 * Ensure coherency between the Icache and the Dcache in the
196 * region described by start. If you have non-snooping
197 * Harvard caches, you need to implement this function.
198 *
199 * - start - virtual start address
200 * - end - virtual end address
201 */
202 SYM_TYPED_FUNC_START(arm1020e_coherent_kern_range)
203 #ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
204 b arm1020e_coherent_user_range
205 #endif
206 SYM_FUNC_END(arm1020e_coherent_kern_range)
208 /*
209 * coherent_user_range(start, end)
210 *
211 * Ensure coherency between the Icache and the Dcache in the
212 * region described by start. If you have non-snooping
213 * Harvard caches, you need to implement this function.
214 *
215 * - start - virtual start address
216 * - end - virtual end address
217 */
218 SYM_TYPED_FUNC_START(arm1020e_coherent_user_range)
219 mov ip, #0
220 bic r0, r0, #CACHE_DLINESIZE - 1
221 1:
222 #ifndef CONFIG_CPU_DCACHE_DISABLE
223 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
224 #endif
225 #ifndef CONFIG_CPU_ICACHE_DISABLE
226 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
227 #endif
228 add r0, r0, #CACHE_DLINESIZE
229 cmp r0, r1
230 blo 1b
231 mcr p15, 0, ip, c7, c10, 4 @ drain WB
232 mov r0, #0
233 ret lr
234 SYM_FUNC_END(arm1020e_coherent_user_range)
236 /*
237 * flush_kern_dcache_area(void *addr, size_t size)
238 *
239 * Ensure no D cache aliasing occurs, either with itself or
240 * the I cache
241 *
242 * - addr - kernel address
243 * - size - region size
244 */
245 SYM_TYPED_FUNC_START(arm1020e_flush_kern_dcache_area)
246 mov ip, #0
247 #ifndef CONFIG_CPU_DCACHE_DISABLE
248 add r1, r0, r1
249 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
250 add r0, r0, #CACHE_DLINESIZE
251 cmp r0, r1
252 blo 1b
253 #endif
254 mcr p15, 0, ip, c7, c10, 4 @ drain WB
255 ret lr
256 SYM_FUNC_END(arm1020e_flush_kern_dcache_area)
258 /*
259 * dma_inv_range(start, end)
260 *
261 * Invalidate (discard) the specified virtual address range.
262 * May not write back any entries. If 'start' or 'end'
263 * are not cache line aligned, those lines must be written
264 * back.
265 *
266 * - start - virtual start address
267 * - end - virtual end address
268 *
269 * (same as v4wb)
270 */
271 arm1020e_dma_inv_range:
272 mov ip, #0
273 #ifndef CONFIG_CPU_DCACHE_DISABLE
274 tst r0, #CACHE_DLINESIZE - 1
275 bic r0, r0, #CACHE_DLINESIZE - 1
276 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
277 tst r1, #CACHE_DLINESIZE - 1
278 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
279 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
280 add r0, r0, #CACHE_DLINESIZE
281 cmp r0, r1
282 blo 1b
283 #endif
284 mcr p15, 0, ip, c7, c10, 4 @ drain WB
285 ret lr
287 /*
288 * dma_clean_range(start, end)
289 *
290 * Clean the specified virtual address range.
291 *
292 * - start - virtual start address
293 * - end - virtual end address
294 *
295 * (same as v4wb)
296 */
297 arm1020e_dma_clean_range:
298 mov ip, #0
299 #ifndef CONFIG_CPU_DCACHE_DISABLE
300 bic r0, r0, #CACHE_DLINESIZE - 1
301 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
302 add r0, r0, #CACHE_DLINESIZE
303 cmp r0, r1
304 blo 1b
305 #endif
306 mcr p15, 0, ip, c7, c10, 4 @ drain WB
307 ret lr
309 /*
310 * dma_flush_range(start, end)
311 *
312 * Clean and invalidate the specified virtual address range.
313 *
314 * - start - virtual start address
315 * - end - virtual end address
316 */
317 SYM_TYPED_FUNC_START(arm1020e_dma_flush_range)
318 mov ip, #0
319 #ifndef CONFIG_CPU_DCACHE_DISABLE
320 bic r0, r0, #CACHE_DLINESIZE - 1
321 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
322 add r0, r0, #CACHE_DLINESIZE
323 cmp r0, r1
324 blo 1b
325 #endif
326 mcr p15, 0, ip, c7, c10, 4 @ drain WB
327 ret lr
328 SYM_FUNC_END(arm1020e_dma_flush_range)
330 /*
331 * dma_map_area(start, size, dir)
332 * - start - kernel virtual start address
333 * - size - size of region
334 * - dir - DMA direction
335 */
336 SYM_TYPED_FUNC_START(arm1020e_dma_map_area)
337 add r1, r1, r0
338 cmp r2, #DMA_TO_DEVICE
339 beq arm1020e_dma_clean_range
340 bcs arm1020e_dma_inv_range
341 b arm1020e_dma_flush_range
342 SYM_FUNC_END(arm1020e_dma_map_area)
344 /*
345 * dma_unmap_area(start, size, dir)
346 * - start - kernel virtual start address
347 * - size - size of region
348 * - dir - DMA direction
349 */
350 SYM_TYPED_FUNC_START(arm1020e_dma_unmap_area)
351 ret lr
352 SYM_FUNC_END(arm1020e_dma_unmap_area)
354 .align 5
355 SYM_TYPED_FUNC_START(cpu_arm1020e_dcache_clean_area)
356 #ifndef CONFIG_CPU_DCACHE_DISABLE
357 mov ip, #0
358 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
359 add r0, r0, #CACHE_DLINESIZE
360 subs r1, r1, #CACHE_DLINESIZE
361 bhi 1b
362 #endif
363 ret lr
364 SYM_FUNC_END(cpu_arm1020e_dcache_clean_area)
366 /* =============================== PageTable ============================== */
368 /*
369 * cpu_arm1020e_switch_mm(pgd)
370 *
371 * Set the translation base pointer to be as described by pgd.
372 *
373 * pgd: new page tables
374 */
375 .align 5
376 SYM_TYPED_FUNC_START(cpu_arm1020e_switch_mm)
377 #ifdef CONFIG_MMU
378 #ifndef CONFIG_CPU_DCACHE_DISABLE
379 mcr p15, 0, r3, c7, c10, 4
380 mov r1, #0xF @ 16 segments
381 1: mov r3, #0x3F @ 64 entries
382 2: mov ip, r3, LSL #26 @ shift up entry
383 orr ip, ip, r1, LSL #5 @ shift in/up index
384 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
385 mov ip, #0
386 subs r3, r3, #1
387 cmp r3, #0
388 bge 2b @ entries 3F to 0
389 subs r1, r1, #1
390 cmp r1, #0
391 bge 1b @ segments 15 to 0
393 #endif
394 mov r1, #0
395 #ifndef CONFIG_CPU_ICACHE_DISABLE
396 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
397 #endif
398 mcr p15, 0, r1, c7, c10, 4 @ drain WB
399 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
400 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
401 #endif
402 ret lr
403 SYM_FUNC_END(cpu_arm1020e_switch_mm)
405 /*
406 * cpu_arm1020e_set_pte(ptep, pte)
407 *
408 * Set a PTE and flush it out
409 */
410 .align 5
411 SYM_TYPED_FUNC_START(cpu_arm1020e_set_pte_ext)
412 #ifdef CONFIG_MMU
413 armv3_set_pte_ext
414 mov r0, r0
415 #ifndef CONFIG_CPU_DCACHE_DISABLE
416 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
417 #endif
418 #endif /* CONFIG_MMU */
419 ret lr
420 SYM_FUNC_END(cpu_arm1020e_set_pte_ext)
422 .type __arm1020e_setup, #function
423 __arm1020e_setup:
424 mov r0, #0
425 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
426 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
427 #ifdef CONFIG_MMU
428 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
429 #endif
430 adr r5, arm1020e_crval
431 ldmia r5, {r5, r6}
432 mrc p15, 0, r0, c1, c0 @ get control register v4
433 bic r0, r0, r5
434 orr r0, r0, r6
435 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
436 orr r0, r0, #0x4000 @ .R.. .... .... ....
437 #endif
438 ret lr
439 .size __arm1020e_setup, . - __arm1020e_setup
441 /*
442 * R
443 * .RVI ZFRS BLDP WCAM
444 * .011 1001 ..11 0101
445 */
446 .type arm1020e_crval, #object
447 arm1020e_crval:
448 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
450 __INITDATA
451 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
452 define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
454 .section ".rodata"
456 string cpu_arch_name, "armv5te"
457 string cpu_elf_name, "v5"
458 string cpu_arm1020e_name, "ARM1020E"
460 .align
462 .section ".proc.info.init", "a"
464 .type __arm1020e_proc_info,#object
465 __arm1020e_proc_info:
466 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
467 .long 0xff0ffff0
468 .long PMD_TYPE_SECT | \
469 PMD_BIT4 | \
470 PMD_SECT_AP_WRITE | \
471 PMD_SECT_AP_READ
472 .long PMD_TYPE_SECT | \
473 PMD_BIT4 | \
474 PMD_SECT_AP_WRITE | \
475 PMD_SECT_AP_READ
476 initfn __arm1020e_setup, __arm1020e_proc_info
477 .long cpu_arch_name
478 .long cpu_elf_name
479 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
480 .long cpu_arm1020e_name
481 .long arm1020e_processor_functions
482 .long v4wbi_tlb_fns
483 .long v4wb_user_fns
484 .long arm1020e_cache_fns
485 .size __arm1020e_proc_info, . - __arm1020e_proc_info