| blob | 6f43d6af2d9a7ac874bd0bd76329c629a62225d8 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
4 *
5 * Copyright (C) 1999-2001 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 *
9 * These are the low level assembler for performing cache and TLB
10 * functions on the arm926.
11 *
12 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
13 */
14 #include <linux/linkage.h>
15 #include <linux/init.h>
16 #include <linux/cfi_types.h>
17 #include <linux/pgtable.h>
18 #include <asm/assembler.h>
19 #include <asm/hwcap.h>
20 #include <asm/pgtable-hwdef.h>
21 #include <asm/page.h>
22 #include <asm/ptrace.h>
23 #include "proc-macros.S"
25 /*
26 * This is the maximum size of an area which will be invalidated
27 * using the single invalidate entry instructions. Anything larger
28 * than this, and we go for the whole cache.
29 *
30 * This value should be chosen such that we choose the cheapest
31 * alternative.
32 */
33 #define CACHE_DLIMIT 16384
35 /*
36 * the cache line size of the I and D cache
37 */
38 #define CACHE_DLINESIZE 32
40 .text
41 /*
42 * cpu_arm926_proc_init()
43 */
44 SYM_TYPED_FUNC_START(cpu_arm926_proc_init)
45 ret lr
46 SYM_FUNC_END(cpu_arm926_proc_init)
48 /*
49 * cpu_arm926_proc_fin()
50 */
51 SYM_TYPED_FUNC_START(cpu_arm926_proc_fin)
52 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
53 bic r0, r0, #0x1000 @ ...i............
54 bic r0, r0, #0x000e @ ............wca.
55 mcr p15, 0, r0, c1, c0, 0 @ disable caches
56 ret lr
57 SYM_FUNC_END(cpu_arm926_proc_fin)
59 /*
60 * cpu_arm926_reset(loc)
61 *
62 * Perform a soft reset of the system. Put the CPU into the
63 * same state as it would be if it had been reset, and branch
64 * to what would be the reset vector.
65 *
66 * loc: location to jump to for soft reset
67 */
68 .align 5
69 .pushsection .idmap.text, "ax"
70 SYM_TYPED_FUNC_START(cpu_arm926_reset)
71 mov ip, #0
72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
73 mcr p15, 0, ip, c7, c10, 4 @ drain WB
74 #ifdef CONFIG_MMU
75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
76 #endif
77 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
78 bic ip, ip, #0x000f @ ............wcam
79 bic ip, ip, #0x1100 @ ...i...s........
80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
81 ret r0
82 SYM_FUNC_END(cpu_arm926_reset)
83 .popsection
85 /*
86 * cpu_arm926_do_idle()
87 *
88 * Called with IRQs disabled
89 */
90 .align 10
91 SYM_TYPED_FUNC_START(cpu_arm926_do_idle)
92 mov r0, #0
93 mrc p15, 0, r1, c1, c0, 0 @ Read control register
94 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
95 bic r2, r1, #1 << 12
96 mrs r3, cpsr @ Disable FIQs while Icache
97 orr ip, r3, #PSR_F_BIT @ is disabled
98 msr cpsr_c, ip
99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
101 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
102 msr cpsr_c, r3 @ Restore FIQ state
103 ret lr
104 SYM_FUNC_END(cpu_arm926_do_idle)
106 /*
107 * flush_icache_all()
108 *
109 * Unconditionally clean and invalidate the entire icache.
110 */
111 SYM_TYPED_FUNC_START(arm926_flush_icache_all)
112 mov r0, #0
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 ret lr
115 SYM_FUNC_END(arm926_flush_icache_all)
117 /*
118 * flush_user_cache_all()
119 *
120 * Clean and invalidate all cache entries in a particular
121 * address space.
122 */
123 SYM_FUNC_ALIAS(arm926_flush_user_cache_all, arm926_flush_kern_cache_all)
125 /*
126 * flush_kern_cache_all()
127 *
128 * Clean and invalidate the entire cache.
129 */
130 SYM_TYPED_FUNC_START(arm926_flush_kern_cache_all)
131 mov r2, #VM_EXEC
132 mov ip, #0
133 __flush_whole_cache:
134 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
135 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
136 #else
137 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
138 bne 1b
139 #endif
140 tst r2, #VM_EXEC
141 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
142 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
143 ret lr
144 SYM_FUNC_END(arm926_flush_kern_cache_all)
146 /*
147 * flush_user_cache_range(start, end, flags)
148 *
149 * Clean and invalidate a range of cache entries in the
150 * specified address range.
151 *
152 * - start - start address (inclusive)
153 * - end - end address (exclusive)
154 * - flags - vm_flags describing address space
155 */
156 SYM_TYPED_FUNC_START(arm926_flush_user_cache_range)
157 mov ip, #0
158 sub r3, r1, r0 @ calculate total size
159 cmp r3, #CACHE_DLIMIT
160 bgt __flush_whole_cache
161 1: tst r2, #VM_EXEC
162 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
163 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
164 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
165 add r0, r0, #CACHE_DLINESIZE
166 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
168 add r0, r0, #CACHE_DLINESIZE
169 #else
170 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
171 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
172 add r0, r0, #CACHE_DLINESIZE
173 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0, #CACHE_DLINESIZE
176 #endif
177 cmp r0, r1
178 blo 1b
179 tst r2, #VM_EXEC
180 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
181 ret lr
182 SYM_FUNC_END(arm926_flush_user_cache_range)
184 /*
185 * coherent_kern_range(start, end)
186 *
187 * Ensure coherency between the Icache and the Dcache in the
188 * region described by start, end. If you have non-snooping
189 * Harvard caches, you need to implement this function.
190 *
191 * - start - virtual start address
192 * - end - virtual end address
193 */
194 SYM_TYPED_FUNC_START(arm926_coherent_kern_range)
195 #ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
196 b arm926_coherent_user_range
197 #endif
198 SYM_FUNC_END(arm926_coherent_kern_range)
200 /*
201 * coherent_user_range(start, end)
202 *
203 * Ensure coherency between the Icache and the Dcache in the
204 * region described by start, end. If you have non-snooping
205 * Harvard caches, you need to implement this function.
206 *
207 * - start - virtual start address
208 * - end - virtual end address
209 */
210 SYM_TYPED_FUNC_START(arm926_coherent_user_range)
211 bic r0, r0, #CACHE_DLINESIZE - 1
212 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
213 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
214 add r0, r0, #CACHE_DLINESIZE
215 cmp r0, r1
216 blo 1b
217 mcr p15, 0, r0, c7, c10, 4 @ drain WB
218 mov r0, #0
219 ret lr
220 SYM_FUNC_END(arm926_coherent_user_range)
222 /*
223 * flush_kern_dcache_area(void *addr, size_t size)
224 *
225 * Ensure no D cache aliasing occurs, either with itself or
226 * the I cache
227 *
228 * - addr - kernel address
229 * - size - region size
230 */
231 SYM_TYPED_FUNC_START(arm926_flush_kern_dcache_area)
232 add r1, r0, r1
233 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
234 add r0, r0, #CACHE_DLINESIZE
235 cmp r0, r1
236 blo 1b
237 mov r0, #0
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
239 mcr p15, 0, r0, c7, c10, 4 @ drain WB
240 ret lr
241 SYM_FUNC_END(arm926_flush_kern_dcache_area)
243 /*
244 * dma_inv_range(start, end)
245 *
246 * Invalidate (discard) the specified virtual address range.
247 * May not write back any entries. If 'start' or 'end'
248 * are not cache line aligned, those lines must be written
249 * back.
250 *
251 * - start - virtual start address
252 * - end - virtual end address
253 *
254 * (same as v4wb)
255 */
256 arm926_dma_inv_range:
257 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
258 tst r0, #CACHE_DLINESIZE - 1
259 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
260 tst r1, #CACHE_DLINESIZE - 1
261 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
262 #endif
263 bic r0, r0, #CACHE_DLINESIZE - 1
264 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
265 add r0, r0, #CACHE_DLINESIZE
266 cmp r0, r1
267 blo 1b
268 mcr p15, 0, r0, c7, c10, 4 @ drain WB
269 ret lr
271 /*
272 * dma_clean_range(start, end)
273 *
274 * Clean the specified virtual address range.
275 *
276 * - start - virtual start address
277 * - end - virtual end address
278 *
279 * (same as v4wb)
280 */
281 arm926_dma_clean_range:
282 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
283 bic r0, r0, #CACHE_DLINESIZE - 1
284 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
285 add r0, r0, #CACHE_DLINESIZE
286 cmp r0, r1
287 blo 1b
288 #endif
289 mcr p15, 0, r0, c7, c10, 4 @ drain WB
290 ret lr
292 /*
293 * dma_flush_range(start, end)
294 *
295 * Clean and invalidate the specified virtual address range.
296 *
297 * - start - virtual start address
298 * - end - virtual end address
299 */
300 SYM_TYPED_FUNC_START(arm926_dma_flush_range)
301 bic r0, r0, #CACHE_DLINESIZE - 1
302 1:
303 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
304 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
305 #else
306 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
307 #endif
308 add r0, r0, #CACHE_DLINESIZE
309 cmp r0, r1
310 blo 1b
311 mcr p15, 0, r0, c7, c10, 4 @ drain WB
312 ret lr
313 SYM_FUNC_END(arm926_dma_flush_range)
315 /*
316 * dma_map_area(start, size, dir)
317 * - start - kernel virtual start address
318 * - size - size of region
319 * - dir - DMA direction
320 */
321 SYM_TYPED_FUNC_START(arm926_dma_map_area)
322 add r1, r1, r0
323 cmp r2, #DMA_TO_DEVICE
324 beq arm926_dma_clean_range
325 bcs arm926_dma_inv_range
326 b arm926_dma_flush_range
327 SYM_FUNC_END(arm926_dma_map_area)
329 /*
330 * dma_unmap_area(start, size, dir)
331 * - start - kernel virtual start address
332 * - size - size of region
333 * - dir - DMA direction
334 */
335 SYM_TYPED_FUNC_START(arm926_dma_unmap_area)
336 ret lr
337 SYM_FUNC_END(arm926_dma_unmap_area)
339 SYM_TYPED_FUNC_START(cpu_arm926_dcache_clean_area)
340 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
341 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
342 add r0, r0, #CACHE_DLINESIZE
343 subs r1, r1, #CACHE_DLINESIZE
344 bhi 1b
345 #endif
346 mcr p15, 0, r0, c7, c10, 4 @ drain WB
347 ret lr
348 SYM_FUNC_END(cpu_arm926_dcache_clean_area)
350 /* =============================== PageTable ============================== */
352 /*
353 * cpu_arm926_switch_mm(pgd)
354 *
355 * Set the translation base pointer to be as described by pgd.
356 *
357 * pgd: new page tables
358 */
359 .align 5
361 SYM_TYPED_FUNC_START(cpu_arm926_switch_mm)
362 #ifdef CONFIG_MMU
363 mov ip, #0
364 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
365 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
366 #else
367 @ && 'Clean & Invalidate whole DCache'
368 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
369 bne 1b
370 #endif
371 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
372 mcr p15, 0, ip, c7, c10, 4 @ drain WB
373 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
374 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
375 #endif
376 ret lr
377 SYM_FUNC_END(cpu_arm926_switch_mm)
379 /*
380 * cpu_arm926_set_pte_ext(ptep, pte, ext)
381 *
382 * Set a PTE and flush it out
383 */
384 .align 5
385 SYM_TYPED_FUNC_START(cpu_arm926_set_pte_ext)
386 #ifdef CONFIG_MMU
387 armv3_set_pte_ext
388 mov r0, r0
389 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
390 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
391 #endif
392 mcr p15, 0, r0, c7, c10, 4 @ drain WB
393 #endif
394 ret lr
395 SYM_FUNC_END(cpu_arm926_set_pte_ext)
397 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
398 .globl cpu_arm926_suspend_size
399 .equ cpu_arm926_suspend_size, 4 * 3
400 #ifdef CONFIG_ARM_CPU_SUSPEND
401 SYM_TYPED_FUNC_START(cpu_arm926_do_suspend)
402 stmfd sp!, {r4 - r6, lr}
403 mrc p15, 0, r4, c13, c0, 0 @ PID
404 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
405 mrc p15, 0, r6, c1, c0, 0 @ Control register
406 stmia r0, {r4 - r6}
407 ldmfd sp!, {r4 - r6, pc}
408 SYM_FUNC_END(cpu_arm926_do_suspend)
410 SYM_TYPED_FUNC_START(cpu_arm926_do_resume)
411 mov ip, #0
412 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
413 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
414 ldmia r0, {r4 - r6}
415 mcr p15, 0, r4, c13, c0, 0 @ PID
416 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
417 mcr p15, 0, r1, c2, c0, 0 @ TTB address
418 mov r0, r6 @ control register
419 b cpu_resume_mmu
420 SYM_FUNC_END(cpu_arm926_do_resume)
421 #endif
423 .type __arm926_setup, #function
424 __arm926_setup:
425 mov r0, #0
426 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
427 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
428 #ifdef CONFIG_MMU
429 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
430 #endif
433 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
434 mov r0, #4 @ disable write-back on caches explicitly
435 mcr p15, 7, r0, c15, c0, 0
436 #endif
438 adr r5, arm926_crval
439 ldmia r5, {r5, r6}
440 mrc p15, 0, r0, c1, c0 @ get control register v4
441 bic r0, r0, r5
442 orr r0, r0, r6
443 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
444 orr r0, r0, #0x4000 @ .1.. .... .... ....
445 #endif
446 ret lr
447 .size __arm926_setup, . - __arm926_setup
449 /*
450 * R
451 * .RVI ZFRS BLDP WCAM
452 * .011 0001 ..11 0101
453 *
454 */
455 .type arm926_crval, #object
456 arm926_crval:
457 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
459 __INITDATA
461 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
462 define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1
464 .section ".rodata"
466 string cpu_arch_name, "armv5tej"
467 string cpu_elf_name, "v5"
468 string cpu_arm926_name, "ARM926EJ-S"
470 .align
472 .section ".proc.info.init", "a"
474 .type __arm926_proc_info,#object
475 __arm926_proc_info:
476 .long 0x41069260 @ ARM926EJ-S (v5TEJ)
477 .long 0xff0ffff0
478 .long PMD_TYPE_SECT | \
479 PMD_SECT_BUFFERABLE | \
480 PMD_SECT_CACHEABLE | \
481 PMD_BIT4 | \
482 PMD_SECT_AP_WRITE | \
483 PMD_SECT_AP_READ
484 .long PMD_TYPE_SECT | \
485 PMD_BIT4 | \
486 PMD_SECT_AP_WRITE | \
487 PMD_SECT_AP_READ
488 initfn __arm926_setup, __arm926_proc_info
489 .long cpu_arch_name
490 .long cpu_elf_name
491 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
492 .long cpu_arm926_name
493 .long arm926_processor_functions
494 .long v4wbi_tlb_fns
495 .long v4wb_user_fns
496 .long arm926_cache_fns
497 .size __arm926_proc_info, . - __arm926_proc_info