arch/arm64/kernel/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Based on arch/arm/kernel/setup.c
   4  *
   5  * Copyright (C) 1995-2001 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/export.h>
  11 #include <linux/kernel.h>
  12 #include <linux/stddef.h>
  13 #include <linux/ioport.h>
  14 #include <linux/delay.h>
  15 #include <linux/initrd.h>
  16 #include <linux/console.h>
  17 #include <linux/cache.h>
  18 #include <linux/screen_info.h>
  19 #include <linux/init.h>
  20 #include <linux/kexec.h>
  21 #include <linux/root_dev.h>
  22 #include <linux/cpu.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/smp.h>
  25 #include <linux/fs.h>
  26 #include <linux/panic_notifier.h>
  27 #include <linux/proc_fs.h>
  28 #include <linux/memblock.h>
  29 #include <linux/of_fdt.h>
  30 #include <linux/efi.h>
  31 #include <linux/psci.h>
  32 #include <linux/sched/task.h>
  33 #include <linux/scs.h>
  34 #include <linux/mm.h>
  35
  36 #include <asm/acpi.h>
  37 #include <asm/fixmap.h>
  38 #include <asm/cpu.h>
  39 #include <asm/cputype.h>
  40 #include <asm/daifflags.h>
  41 #include <asm/elf.h>
  42 #include <asm/cpufeature.h>
  43 #include <asm/cpu_ops.h>
  44 #include <asm/kasan.h>
  45 #include <asm/numa.h>
  46 #include <asm/rsi.h>
  47 #include <asm/scs.h>
  48 #include <asm/sections.h>
  49 #include <asm/setup.h>
  50 #include <asm/smp_plat.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/tlbflush.h>
  53 #include <asm/traps.h>
  54 #include <asm/efi.h>
  55 #include <asm/xen/hypervisor.h>
  56 #include <asm/mmu_context.h>
  57
  58 static int num_standard_resources;
  59 static struct resource *standard_resources;
  60
  61 phys_addr_t __fdt_pointer __initdata;
  62 u64 mmu_enabled_at_boot __initdata;
  63
  64 /*
  65  * Standard memory resources
  66  */
  67 static struct resource mem_res[] = {
  68         {
  69                 .name = "Kernel code",
  70                 .start = 0,
  71                 .end = 0,
  72                 .flags = IORESOURCE_SYSTEM_RAM
  73         },
  74         {
  75                 .name = "Kernel data",
  76                 .start = 0,
  77                 .end = 0,
  78                 .flags = IORESOURCE_SYSTEM_RAM
  79         }
  80 };
  81
  82 #define kernel_code mem_res[0]
  83 #define kernel_data mem_res[1]
  84
  85 /*
  86  * The recorded values of x0 .. x3 upon kernel entry.
  87  */
  88 u64 __cacheline_aligned boot_args[4];
  89
  90 void __init smp_setup_processor_id(void)
  91 {
  92         u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
  93         set_cpu_logical_map(0, mpidr);
  94
  95         pr_info("Booting Linux on physical CPU 0x%010lx [0x%08x]\n",
  96                 (unsigned long)mpidr, read_cpuid_id());
  97 }
  98
  99 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
 100 {
 101         return phys_id == cpu_logical_map(cpu);
 102 }
 103
 104 struct mpidr_hash mpidr_hash;
 105 /**
 106  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
 107  *                        level in order to build a linear index from an
 108  *                        MPIDR value. Resulting algorithm is a collision
 109  *                        free hash carried out through shifting and ORing
 110  */
 111 static void __init smp_build_mpidr_hash(void)
 112 {
 113         u32 i, affinity, fs[4], bits[4], ls;
 114         u64 mask = 0;
 115         /*
 116          * Pre-scan the list of MPIDRS and filter out bits that do
 117          * not contribute to affinity levels, ie they never toggle.
 118          */
 119         for_each_possible_cpu(i)
 120                 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
 121         pr_debug("mask of set bits %#llx\n", mask);
 122         /*
 123          * Find and stash the last and first bit set at all affinity levels to
 124          * check how many bits are required to represent them.
 125          */
 126         for (i = 0; i < 4; i++) {
 127                 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
 128                 /*
 129                  * Find the MSB bit and LSB bits position
 130                  * to determine how many bits are required
 131                  * to express the affinity level.
 132                  */
 133                 ls = fls(affinity);
 134                 fs[i] = affinity ? ffs(affinity) - 1 : 0;
 135                 bits[i] = ls - fs[i];
 136         }
 137         /*
 138          * An index can be created from the MPIDR_EL1 by isolating the
 139          * significant bits at each affinity level and by shifting
 140          * them in order to compress the 32 bits values space to a
 141          * compressed set of values. This is equivalent to hashing
 142          * the MPIDR_EL1 through shifting and ORing. It is a collision free
 143          * hash though not minimal since some levels might contain a number
 144          * of CPUs that is not an exact power of 2 and their bit
 145          * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
 146          */
 147         mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
 148         mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
 149         mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
 150                                                 (bits[1] + bits[0]);
 151         mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
 152                                   fs[3] - (bits[2] + bits[1] + bits[0]);
 153         mpidr_hash.mask = mask;
 154         mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
 155         pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
 156                 mpidr_hash.shift_aff[0],
 157                 mpidr_hash.shift_aff[1],
 158                 mpidr_hash.shift_aff[2],
 159                 mpidr_hash.shift_aff[3],
 160                 mpidr_hash.mask,
 161                 mpidr_hash.bits);
 162         /*
 163          * 4x is an arbitrary value used to warn on a hash table much bigger
 164          * than expected on most systems.
 165          */
 166         if (mpidr_hash_size() > 4 * num_possible_cpus())
 167                 pr_warn("Large number of MPIDR hash buckets detected\n");
 168 }
 169
 170 static void __init setup_machine_fdt(phys_addr_t dt_phys)
 171 {
 172         int size;
 173         void *dt_virt = fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL);
 174         const char *name;
 175
 176         if (dt_virt)
 177                 memblock_reserve(dt_phys, size);
 178
 179         /*
 180          * dt_virt is a fixmap address, hence __pa(dt_virt) can't be used.
 181          * Pass dt_phys directly.
 182          */
 183         if (!early_init_dt_scan(dt_virt, dt_phys)) {
 184                 pr_crit("\n"
 185                         "Error: invalid device tree blob at physical address %pa (virtual address 0x%px)\n"
 186                         "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
 187                         "\nPlease check your bootloader.",
 188                         &dt_phys, dt_virt);
 189
 190                 /*
 191                  * Note that in this _really_ early stage we cannot even BUG()
 192                  * or oops, so the least terrible thing to do is cpu_relax(),
 193                  * or else we could end-up printing non-initialized data, etc.
 194                  */
 195                 while (true)
 196                         cpu_relax();
 197         }
 198
 199         /* Early fixups are done, map the FDT as read-only now */
 200         fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL_RO);
 201
 202         name = of_flat_dt_get_machine_name();
 203         if (!name)
 204                 return;
 205
 206         pr_info("Machine model: %s\n", name);
 207         dump_stack_set_arch_desc("%s (DT)", name);
 208 }
 209
 210 static void __init request_standard_resources(void)
 211 {
 212         struct memblock_region *region;
 213         struct resource *res;
 214         unsigned long i = 0;
 215         size_t res_size;
 216
 217         kernel_code.start   = __pa_symbol(_stext);
 218         kernel_code.end     = __pa_symbol(__init_begin - 1);
 219         kernel_data.start   = __pa_symbol(_sdata);
 220         kernel_data.end     = __pa_symbol(_end - 1);
 221         insert_resource(&iomem_resource, &kernel_code);
 222         insert_resource(&iomem_resource, &kernel_data);
 223
 224         num_standard_resources = memblock.memory.cnt;
 225         res_size = num_standard_resources * sizeof(*standard_resources);
 226         standard_resources = memblock_alloc(res_size, SMP_CACHE_BYTES);
 227         if (!standard_resources)
 228                 panic("%s: Failed to allocate %zu bytes\n", __func__, res_size);
 229
 230         for_each_mem_region(region) {
 231                 res = &standard_resources[i++];
 232                 if (memblock_is_nomap(region)) {
 233                         res->name  = "reserved";
 234                         res->flags = IORESOURCE_MEM;
 235                         res->start = __pfn_to_phys(memblock_region_reserved_base_pfn(region));
 236                         res->end = __pfn_to_phys(memblock_region_reserved_end_pfn(region)) - 1;
 237                 } else {
 238                         res->name  = "System RAM";
 239                         res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
 240                         res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
 241                         res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
 242                 }
 243
 244                 insert_resource(&iomem_resource, res);
 245         }
 246 }
 247
 248 static int __init reserve_memblock_reserved_regions(void)
 249 {
 250         u64 i, j;
 251
 252         for (i = 0; i < num_standard_resources; ++i) {
 253                 struct resource *mem = &standard_resources[i];
 254                 phys_addr_t r_start, r_end, mem_size = resource_size(mem);
 255
 256                 if (!memblock_is_region_reserved(mem->start, mem_size))
 257                         continue;
 258
 259                 for_each_reserved_mem_range(j, &r_start, &r_end) {
 260                         resource_size_t start, end;
 261
 262                         start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start);
 263                         end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end);
 264
 265                         if (start > mem->end || end < mem->start)
 266                                 continue;
 267
 268                         reserve_region_with_split(mem, start, end, "reserved");
 269                 }
 270         }
 271
 272         return 0;
 273 }
 274 arch_initcall(reserve_memblock_reserved_regions);
 275
 276 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
 277
 278 u64 cpu_logical_map(unsigned int cpu)
 279 {
 280         return __cpu_logical_map[cpu];
 281 }
 282
 283 void __init __no_sanitize_address setup_arch(char **cmdline_p)
 284 {
 285         setup_initial_init_mm(_stext, _etext, _edata, _end);
 286
 287         *cmdline_p = boot_command_line;
 288
 289         kaslr_init();
 290
 291         early_fixmap_init();
 292         early_ioremap_init();
 293
 294         setup_machine_fdt(__fdt_pointer);
 295
 296         /*
 297          * Initialise the static keys early as they may be enabled by the
 298          * cpufeature code and early parameters.
 299          */
 300         jump_label_init();
 301         parse_early_param();
 302
 303         dynamic_scs_init();
 304
 305         /*
 306          * The primary CPU enters the kernel with all DAIF exceptions masked.
 307          *
 308          * We must unmask Debug and SError before preemption or scheduling is
 309          * possible to ensure that these are consistently unmasked across
 310          * threads, and we want to unmask SError as soon as possible after
 311          * initializing earlycon so that we can report any SErrors immediately.
 312          *
 313          * IRQ and FIQ will be unmasked after the root irqchip has been
 314          * detected and initialized.
 315          */
 316         local_daif_restore(DAIF_PROCCTX_NOIRQ);
 317
 318         /*
 319          * TTBR0 is only used for the identity mapping at this stage. Make it
 320          * point to zero page to avoid speculatively fetching new entries.
 321          */
 322         cpu_uninstall_idmap();
 323
 324         xen_early_init();
 325         efi_init();
 326
 327         if (!efi_enabled(EFI_BOOT)) {
 328                 if ((u64)_text % MIN_KIMG_ALIGN)
 329                         pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
 330                 WARN_TAINT(mmu_enabled_at_boot, TAINT_FIRMWARE_WORKAROUND,
 331                            FW_BUG "Booted with MMU enabled!");
 332         }
 333
 334         arm64_memblock_init();
 335
 336         paging_init();
 337
 338         acpi_table_upgrade();
 339
 340         /* Parse the ACPI tables for possible boot-time configuration */
 341         acpi_boot_table_init();
 342
 343         if (acpi_disabled)
 344                 unflatten_device_tree();
 345
 346         bootmem_init();
 347
 348         kasan_init();
 349
 350         request_standard_resources();
 351
 352         early_ioremap_reset();
 353
 354         if (acpi_disabled)
 355                 psci_dt_init();
 356         else
 357                 psci_acpi_init();
 358
 359         arm64_rsi_init();
 360
 361         init_bootcpu_ops();
 362         smp_init_cpus();
 363         smp_build_mpidr_hash();
 364
 365 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
 366         /*
 367          * Make sure init_thread_info.ttbr0 always generates translation
 368          * faults in case uaccess_enable() is inadvertently called by the init
 369          * thread.
 370          */
 371         init_task.thread_info.ttbr0 = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
 372 #endif
 373
 374         if (boot_args[1] || boot_args[2] || boot_args[3]) {
 375                 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
 376                         "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
 377                         "This indicates a broken bootloader or old kernel\n",
 378                         boot_args[1], boot_args[2], boot_args[3]);
 379         }
 380 }
 381
 382 static inline bool cpu_can_disable(unsigned int cpu)
 383 {
 384 #ifdef CONFIG_HOTPLUG_CPU
 385         const struct cpu_operations *ops = get_cpu_ops(cpu);
 386
 387         if (ops && ops->cpu_can_disable)
 388                 return ops->cpu_can_disable(cpu);
 389 #endif
 390         return false;
 391 }
 392
 393 bool arch_cpu_is_hotpluggable(int num)
 394 {
 395         return cpu_can_disable(num);
 396 }
 397
 398 static void dump_kernel_offset(void)
 399 {
 400         const unsigned long offset = kaslr_offset();
 401
 402         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) {
 403                 pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n",
 404                          offset, KIMAGE_VADDR);
 405                 pr_emerg("PHYS_OFFSET: 0x%llx\n", PHYS_OFFSET);
 406         } else {
 407                 pr_emerg("Kernel Offset: disabled\n");
 408         }
 409 }
 410
 411 static int arm64_panic_block_dump(struct notifier_block *self,
 412                                   unsigned long v, void *p)
 413 {
 414         dump_kernel_offset();
 415         dump_cpu_features();
 416         dump_mem_limit();
 417         return 0;
 418 }
 419
 420 static struct notifier_block arm64_panic_block = {
 421         .notifier_call = arm64_panic_block_dump
 422 };
 423
 424 static int __init register_arm64_panic_block(void)
 425 {
 426         atomic_notifier_chain_register(&panic_notifier_list,
 427                                        &arm64_panic_block);
 428         return 0;
 429 }
 430 device_initcall(register_arm64_panic_block);
 431
 432 static int __init check_mmu_enabled_at_boot(void)
 433 {
 434         if (!efi_enabled(EFI_BOOT) && mmu_enabled_at_boot)
 435                 panic("Non-EFI boot detected with MMU and caches enabled");
 436         return 0;
 437 }
 438 device_initcall_sync(check_mmu_enabled_at_boot);