arch/csky/include/asm/barrier.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef __ASM_CSKY_BARRIER_H
   4 #define __ASM_CSKY_BARRIER_H
   5
   6 #ifndef __ASSEMBLY__
   7
   8 #define nop()   asm volatile ("nop\n":::"memory")
   9
  10 #ifdef CONFIG_SMP
  11
  12 /*
  13  * bar.brwarws: ordering barrier for all load/store instructions
  14  *              before/after
  15  *
  16  * |31|30 26|25 21|20 16|15  10|9   5|4           0|
  17  *  1  10000 00000 00000 100001 00001 0 bw br aw ar
  18  *
  19  * b: before
  20  * a: after
  21  * r: read
  22  * w: write
  23  *
  24  * Here are all combinations:
  25  *
  26  * bar.brw
  27  * bar.br
  28  * bar.bw
  29  * bar.arw
  30  * bar.ar
  31  * bar.aw
  32  * bar.brwarw
  33  * bar.brarw
  34  * bar.bwarw
  35  * bar.brwar
  36  * bar.brwaw
  37  * bar.brar
  38  * bar.bwaw
  39  */
  40 #define FULL_FENCE              ".long 0x842fc000\n"
  41 #define ACQUIRE_FENCE           ".long 0x8427c000\n"
  42 #define RELEASE_FENCE           ".long 0x842ec000\n"
  43
  44 #define __bar_brw()     asm volatile (".long 0x842cc000\n":::"memory")
  45 #define __bar_br()      asm volatile (".long 0x8424c000\n":::"memory")
  46 #define __bar_bw()      asm volatile (".long 0x8428c000\n":::"memory")
  47 #define __bar_arw()     asm volatile (".long 0x8423c000\n":::"memory")
  48 #define __bar_ar()      asm volatile (".long 0x8421c000\n":::"memory")
  49 #define __bar_aw()      asm volatile (".long 0x8422c000\n":::"memory")
  50 #define __bar_brwarw()  asm volatile (FULL_FENCE:::"memory")
  51 #define __bar_brarw()   asm volatile (ACQUIRE_FENCE:::"memory")
  52 #define __bar_bwarw()   asm volatile (".long 0x842bc000\n":::"memory")
  53 #define __bar_brwar()   asm volatile (".long 0x842dc000\n":::"memory")
  54 #define __bar_brwaw()   asm volatile (RELEASE_FENCE:::"memory")
  55 #define __bar_brar()    asm volatile (".long 0x8425c000\n":::"memory")
  56 #define __bar_brar()    asm volatile (".long 0x8425c000\n":::"memory")
  57 #define __bar_bwaw()    asm volatile (".long 0x842ac000\n":::"memory")
  58
  59 #define __smp_mb()      __bar_brwarw()
  60 #define __smp_rmb()     __bar_brar()
  61 #define __smp_wmb()     __bar_bwaw()
  62
  63 #define __smp_acquire_fence()   __bar_brarw()
  64 #define __smp_release_fence()   __bar_brwaw()
  65
  66 #endif /* CONFIG_SMP */
  67
  68 /*
  69  * sync:        completion barrier, all sync.xx instructions
  70  *              guarantee the last response received by bus transaction
  71  *              made by ld/st instructions before sync.s
  72  * sync.s:      inherit from sync, but also shareable to other cores
  73  * sync.i:      inherit from sync, but also flush cpu pipeline
  74  * sync.is:     the same with sync.i + sync.s
  75  */
  76 #define mb()            asm volatile ("sync\n":::"memory")
  77
  78 #ifdef CONFIG_CPU_HAS_CACHEV2
  79 /*
  80  * Using three sync.is to prevent speculative PTW
  81  */
  82 #define sync_is()       asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory")
  83 #endif
  84
  85 #include <asm-generic/barrier.h>
  86
  87 #endif /* __ASSEMBLY__ */
  88 #endif /* __ASM_CSKY_BARRIER_H */