arch/mips/include/asm/asmmacro.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Ralf Baechle
   7  */
   8 #ifndef _ASM_ASMMACRO_H
   9 #define _ASM_ASMMACRO_H
  10
  11 #include <asm/hazards.h>
  12 #include <asm/asm-offsets.h>
  13 #include <asm/msa.h>
  14
  15 #ifdef CONFIG_32BIT
  16 #include <asm/asmmacro-32.h>
  17 #endif
  18 #ifdef CONFIG_64BIT
  19 #include <asm/asmmacro-64.h>
  20 #endif
  21
  22 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
  23 #undef fp
  24
  25 /*
  26  * Helper macros for generating raw instruction encodings.
  27  */
  28 #ifdef CONFIG_CPU_MICROMIPS
  29         .macro  insn32_if_mm enc
  30         .insn
  31         .hword ((\enc) >> 16)
  32         .hword ((\enc) & 0xffff)
  33         .endm
  34
  35         .macro  insn_if_mips enc
  36         .endm
  37 #else
  38         .macro  insn32_if_mm enc
  39         .endm
  40
  41         .macro  insn_if_mips enc
  42         .insn
  43         .word (\enc)
  44         .endm
  45 #endif
  46
  47 #ifdef CONFIG_CPU_HAS_DIEI
  48         .macro  local_irq_enable
  49         ei
  50         irq_enable_hazard
  51         .endm
  52
  53         .macro  local_irq_disable
  54         di
  55         irq_disable_hazard
  56         .endm
  57 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
  58         .macro  local_irq_enable reg=t0
  59         mfc0    \reg, CP0_STATUS
  60         ori     \reg, \reg, 1
  61         mtc0    \reg, CP0_STATUS
  62         irq_enable_hazard
  63         .endm
  64
  65         .macro  local_irq_disable reg=t0
  66 #ifdef CONFIG_PREEMPTION
  67         lw      \reg, TI_PRE_COUNT($28)
  68         addi    \reg, \reg, 1
  69         sw      \reg, TI_PRE_COUNT($28)
  70 #endif
  71         mfc0    \reg, CP0_STATUS
  72         ori     \reg, \reg, 1
  73         xori    \reg, \reg, 1
  74         mtc0    \reg, CP0_STATUS
  75         irq_disable_hazard
  76 #ifdef CONFIG_PREEMPTION
  77         lw      \reg, TI_PRE_COUNT($28)
  78         addi    \reg, \reg, -1
  79         sw      \reg, TI_PRE_COUNT($28)
  80 #endif
  81         .endm
  82 #endif  /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
  83
  84         .macro  fpu_save_16even thread tmp=t0
  85         .set    push
  86         .set    hardfloat
  87         cfc1    \tmp, fcr31
  88         sdc1    $f0,  THREAD_FPR0(\thread)
  89         sdc1    $f2,  THREAD_FPR2(\thread)
  90         sdc1    $f4,  THREAD_FPR4(\thread)
  91         sdc1    $f6,  THREAD_FPR6(\thread)
  92         sdc1    $f8,  THREAD_FPR8(\thread)
  93         sdc1    $f10, THREAD_FPR10(\thread)
  94         sdc1    $f12, THREAD_FPR12(\thread)
  95         sdc1    $f14, THREAD_FPR14(\thread)
  96         sdc1    $f16, THREAD_FPR16(\thread)
  97         sdc1    $f18, THREAD_FPR18(\thread)
  98         sdc1    $f20, THREAD_FPR20(\thread)
  99         sdc1    $f22, THREAD_FPR22(\thread)
 100         sdc1    $f24, THREAD_FPR24(\thread)
 101         sdc1    $f26, THREAD_FPR26(\thread)
 102         sdc1    $f28, THREAD_FPR28(\thread)
 103         sdc1    $f30, THREAD_FPR30(\thread)
 104         sw      \tmp, THREAD_FCR31(\thread)
 105         .set    pop
 106         .endm
 107
 108         .macro  fpu_save_16odd thread
 109         .set    push
 110         .set    mips64r2
 111         .set    fp=64
 112         .set    hardfloat
 113         sdc1    $f1,  THREAD_FPR1(\thread)
 114         sdc1    $f3,  THREAD_FPR3(\thread)
 115         sdc1    $f5,  THREAD_FPR5(\thread)
 116         sdc1    $f7,  THREAD_FPR7(\thread)
 117         sdc1    $f9,  THREAD_FPR9(\thread)
 118         sdc1    $f11, THREAD_FPR11(\thread)
 119         sdc1    $f13, THREAD_FPR13(\thread)
 120         sdc1    $f15, THREAD_FPR15(\thread)
 121         sdc1    $f17, THREAD_FPR17(\thread)
 122         sdc1    $f19, THREAD_FPR19(\thread)
 123         sdc1    $f21, THREAD_FPR21(\thread)
 124         sdc1    $f23, THREAD_FPR23(\thread)
 125         sdc1    $f25, THREAD_FPR25(\thread)
 126         sdc1    $f27, THREAD_FPR27(\thread)
 127         sdc1    $f29, THREAD_FPR29(\thread)
 128         sdc1    $f31, THREAD_FPR31(\thread)
 129         .set    pop
 130         .endm
 131
 132         .macro  fpu_save_double thread status tmp
 133 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
 134     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
 135         sll     \tmp, \status, 5
 136         bgez    \tmp, 10f
 137         fpu_save_16odd \thread
 138 10:
 139 #endif
 140         fpu_save_16even \thread \tmp
 141         .endm
 142
 143         .macro  fpu_restore_16even thread tmp=t0
 144         .set    push
 145         .set    hardfloat
 146         lw      \tmp, THREAD_FCR31(\thread)
 147         ldc1    $f0,  THREAD_FPR0(\thread)
 148         ldc1    $f2,  THREAD_FPR2(\thread)
 149         ldc1    $f4,  THREAD_FPR4(\thread)
 150         ldc1    $f6,  THREAD_FPR6(\thread)
 151         ldc1    $f8,  THREAD_FPR8(\thread)
 152         ldc1    $f10, THREAD_FPR10(\thread)
 153         ldc1    $f12, THREAD_FPR12(\thread)
 154         ldc1    $f14, THREAD_FPR14(\thread)
 155         ldc1    $f16, THREAD_FPR16(\thread)
 156         ldc1    $f18, THREAD_FPR18(\thread)
 157         ldc1    $f20, THREAD_FPR20(\thread)
 158         ldc1    $f22, THREAD_FPR22(\thread)
 159         ldc1    $f24, THREAD_FPR24(\thread)
 160         ldc1    $f26, THREAD_FPR26(\thread)
 161         ldc1    $f28, THREAD_FPR28(\thread)
 162         ldc1    $f30, THREAD_FPR30(\thread)
 163         ctc1    \tmp, fcr31
 164         .set    pop
 165         .endm
 166
 167         .macro  fpu_restore_16odd thread
 168         .set    push
 169         .set    mips64r2
 170         .set    fp=64
 171         .set    hardfloat
 172         ldc1    $f1,  THREAD_FPR1(\thread)
 173         ldc1    $f3,  THREAD_FPR3(\thread)
 174         ldc1    $f5,  THREAD_FPR5(\thread)
 175         ldc1    $f7,  THREAD_FPR7(\thread)
 176         ldc1    $f9,  THREAD_FPR9(\thread)
 177         ldc1    $f11, THREAD_FPR11(\thread)
 178         ldc1    $f13, THREAD_FPR13(\thread)
 179         ldc1    $f15, THREAD_FPR15(\thread)
 180         ldc1    $f17, THREAD_FPR17(\thread)
 181         ldc1    $f19, THREAD_FPR19(\thread)
 182         ldc1    $f21, THREAD_FPR21(\thread)
 183         ldc1    $f23, THREAD_FPR23(\thread)
 184         ldc1    $f25, THREAD_FPR25(\thread)
 185         ldc1    $f27, THREAD_FPR27(\thread)
 186         ldc1    $f29, THREAD_FPR29(\thread)
 187         ldc1    $f31, THREAD_FPR31(\thread)
 188         .set    pop
 189         .endm
 190
 191         .macro  fpu_restore_double thread status tmp
 192 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
 193     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
 194         sll     \tmp, \status, 5
 195         bgez    \tmp, 10f                               # 16 register mode?
 196
 197         fpu_restore_16odd \thread
 198 10:
 199 #endif
 200         fpu_restore_16even \thread \tmp
 201         .endm
 202
 203 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
 204     defined(CONFIG_CPU_MIPSR6)
 205         .macro  _EXT    rd, rs, p, s
 206         ext     \rd, \rs, \p, \s
 207         .endm
 208 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
 209         .macro  _EXT    rd, rs, p, s
 210         srl     \rd, \rs, \p
 211         andi    \rd, \rd, (1 << \s) - 1
 212         .endm
 213 #endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
 214
 215 /*
 216  * Temporary until all gas have MT ASE support
 217  */
 218         .macro  DMT     reg=0
 219         insn_if_mips    0x41600bc1 | (\reg << 16)
 220         insn32_if_mm    0x0000057C | (\reg << 21)
 221         .endm
 222
 223         .macro  EMT     reg=0
 224         insn_if_mips    0x41600be1 | (\reg << 16)
 225         insn32_if_mm    0x0000257C | (\reg << 21)
 226         .endm
 227
 228         .macro  DVPE    reg=0
 229         insn_if_mips    0x41600001 | (\reg << 16)
 230         insn32_if_mm    0x0000157C | (\reg << 21)
 231         .endm
 232
 233         .macro  EVPE    reg=0
 234         insn_if_mips    0x41600021 | (\reg << 16)
 235         insn32_if_mm    0x0000357C | (\reg << 21)
 236         .endm
 237
 238         .macro  MFTR    rs=0, rt=0, u=0, sel=0
 239         insn_if_mips    0x41000000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel)
 240         insn32_if_mm    0x0000000E | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
 241         .endm
 242
 243         .macro  MTTR    rt=0, rs=0, u=0, sel=0
 244         insn_if_mips    0x41800000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel)
 245         insn32_if_mm    0x00000006 | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
 246         .endm
 247
 248 #ifdef TOOLCHAIN_SUPPORTS_MSA
 249         .macro  _cfcmsa rd, cs
 250         .set    push
 251         .set    mips32r2
 252         .set    fp=64
 253         .set    msa
 254         cfcmsa  \rd, $\cs
 255         .set    pop
 256         .endm
 257
 258         .macro  _ctcmsa cd, rs
 259         .set    push
 260         .set    mips32r2
 261         .set    fp=64
 262         .set    msa
 263         ctcmsa  $\cd, \rs
 264         .set    pop
 265         .endm
 266
 267         .macro  ld_b    wd, off, base
 268         .set    push
 269         .set    mips32r2
 270         .set    fp=64
 271         .set    msa
 272         ld.b    $w\wd, \off(\base)
 273         .set    pop
 274         .endm
 275
 276         .macro  ld_h    wd, off, base
 277         .set    push
 278         .set    mips32r2
 279         .set    fp=64
 280         .set    msa
 281         ld.h    $w\wd, \off(\base)
 282         .set    pop
 283         .endm
 284
 285         .macro  ld_w    wd, off, base
 286         .set    push
 287         .set    mips32r2
 288         .set    fp=64
 289         .set    msa
 290         ld.w    $w\wd, \off(\base)
 291         .set    pop
 292         .endm
 293
 294         .macro  ld_d    wd, off, base
 295         .set    push
 296         .set    mips32r2
 297         .set    fp=64
 298         .set    msa
 299         ld.d    $w\wd, \off(\base)
 300         .set    pop
 301         .endm
 302
 303         .macro  st_b    wd, off, base
 304         .set    push
 305         .set    mips32r2
 306         .set    fp=64
 307         .set    msa
 308         st.b    $w\wd, \off(\base)
 309         .set    pop
 310         .endm
 311
 312         .macro  st_h    wd, off, base
 313         .set    push
 314         .set    mips32r2
 315         .set    fp=64
 316         .set    msa
 317         st.h    $w\wd, \off(\base)
 318         .set    pop
 319         .endm
 320
 321         .macro  st_w    wd, off, base
 322         .set    push
 323         .set    mips32r2
 324         .set    fp=64
 325         .set    msa
 326         st.w    $w\wd, \off(\base)
 327         .set    pop
 328         .endm
 329
 330         .macro  st_d    wd, off, base
 331         .set    push
 332         .set    mips32r2
 333         .set    fp=64
 334         .set    msa
 335         st.d    $w\wd, \off(\base)
 336         .set    pop
 337         .endm
 338
 339         .macro  copy_s_w        ws, n
 340         .set    push
 341         .set    mips32r2
 342         .set    fp=64
 343         .set    msa
 344         copy_s.w $1, $w\ws[\n]
 345         .set    pop
 346         .endm
 347
 348         .macro  copy_s_d        ws, n
 349         .set    push
 350         .set    mips64r2
 351         .set    fp=64
 352         .set    msa
 353         copy_s.d $1, $w\ws[\n]
 354         .set    pop
 355         .endm
 356
 357         .macro  insert_w        wd, n
 358         .set    push
 359         .set    mips32r2
 360         .set    fp=64
 361         .set    msa
 362         insert.w $w\wd[\n], $1
 363         .set    pop
 364         .endm
 365
 366         .macro  insert_d        wd, n
 367         .set    push
 368         .set    mips64r2
 369         .set    fp=64
 370         .set    msa
 371         insert.d $w\wd[\n], $1
 372         .set    pop
 373         .endm
 374 #else
 375
 376         /*
 377          * Temporary until all toolchains in use include MSA support.
 378          */
 379         .macro  _cfcmsa rd, cs
 380         .set    push
 381         .set    noat
 382         .set    hardfloat
 383         insn_if_mips 0x787e0059 | (\cs << 11)
 384         insn32_if_mm 0x587e0056 | (\cs << 11)
 385         move    \rd, $1
 386         .set    pop
 387         .endm
 388
 389         .macro  _ctcmsa cd, rs
 390         .set    push
 391         .set    noat
 392         .set    hardfloat
 393         move    $1, \rs
 394         insn_if_mips 0x783e0819 | (\cd << 6)
 395         insn32_if_mm 0x583e0816 | (\cd << 6)
 396         .set    pop
 397         .endm
 398
 399         .macro  ld_b    wd, off, base
 400         .set    push
 401         .set    noat
 402         .set    hardfloat
 403         PTR_ADDU $1, \base, \off
 404         insn_if_mips 0x78000820 | (\wd << 6)
 405         insn32_if_mm 0x58000807 | (\wd << 6)
 406         .set    pop
 407         .endm
 408
 409         .macro  ld_h    wd, off, base
 410         .set    push
 411         .set    noat
 412         .set    hardfloat
 413         PTR_ADDU $1, \base, \off
 414         insn_if_mips 0x78000821 | (\wd << 6)
 415         insn32_if_mm 0x58000817 | (\wd << 6)
 416         .set    pop
 417         .endm
 418
 419         .macro  ld_w    wd, off, base
 420         .set    push
 421         .set    noat
 422         .set    hardfloat
 423         PTR_ADDU $1, \base, \off
 424         insn_if_mips 0x78000822 | (\wd << 6)
 425         insn32_if_mm 0x58000827 | (\wd << 6)
 426         .set    pop
 427         .endm
 428
 429         .macro  ld_d    wd, off, base
 430         .set    push
 431         .set    noat
 432         .set    hardfloat
 433         PTR_ADDU $1, \base, \off
 434         insn_if_mips 0x78000823 | (\wd << 6)
 435         insn32_if_mm 0x58000837 | (\wd << 6)
 436         .set    pop
 437         .endm
 438
 439         .macro  st_b    wd, off, base
 440         .set    push
 441         .set    noat
 442         .set    hardfloat
 443         PTR_ADDU $1, \base, \off
 444         insn_if_mips 0x78000824 | (\wd << 6)
 445         insn32_if_mm 0x5800080f | (\wd << 6)
 446         .set    pop
 447         .endm
 448
 449         .macro  st_h    wd, off, base
 450         .set    push
 451         .set    noat
 452         .set    hardfloat
 453         PTR_ADDU $1, \base, \off
 454         insn_if_mips 0x78000825 | (\wd << 6)
 455         insn32_if_mm 0x5800081f | (\wd << 6)
 456         .set    pop
 457         .endm
 458
 459         .macro  st_w    wd, off, base
 460         .set    push
 461         .set    noat
 462         .set    hardfloat
 463         PTR_ADDU $1, \base, \off
 464         insn_if_mips 0x78000826 | (\wd << 6)
 465         insn32_if_mm 0x5800082f | (\wd << 6)
 466         .set    pop
 467         .endm
 468
 469         .macro  st_d    wd, off, base
 470         .set    push
 471         .set    noat
 472         .set    hardfloat
 473         PTR_ADDU $1, \base, \off
 474         insn_if_mips 0x78000827 | (\wd << 6)
 475         insn32_if_mm 0x5800083f | (\wd << 6)
 476         .set    pop
 477         .endm
 478
 479         .macro  copy_s_w        ws, n
 480         .set    push
 481         .set    noat
 482         .set    hardfloat
 483         insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
 484         insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
 485         .set    pop
 486         .endm
 487
 488         .macro  copy_s_d        ws, n
 489         .set    push
 490         .set    noat
 491         .set    hardfloat
 492         insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
 493         insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
 494         .set    pop
 495         .endm
 496
 497         .macro  insert_w        wd, n
 498         .set    push
 499         .set    noat
 500         .set    hardfloat
 501         insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
 502         insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
 503         .set    pop
 504         .endm
 505
 506         .macro  insert_d        wd, n
 507         .set    push
 508         .set    noat
 509         .set    hardfloat
 510         insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
 511         insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
 512         .set    pop
 513         .endm
 514 #endif
 515
 516 #ifdef TOOLCHAIN_SUPPORTS_MSA
 517 #define FPR_BASE_OFFS   THREAD_FPR0
 518 #define FPR_BASE        $1
 519 #else
 520 #define FPR_BASE_OFFS   0
 521 #define FPR_BASE        \thread
 522 #endif
 523
 524         .macro  msa_save_all    thread
 525         .set    push
 526         .set    noat
 527 #ifdef TOOLCHAIN_SUPPORTS_MSA
 528         PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
 529 #endif
 530         st_d     0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
 531         st_d     1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
 532         st_d     2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
 533         st_d     3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
 534         st_d     4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
 535         st_d     5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
 536         st_d     6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
 537         st_d     7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
 538         st_d     8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
 539         st_d     9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
 540         st_d    10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
 541         st_d    11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
 542         st_d    12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
 543         st_d    13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
 544         st_d    14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
 545         st_d    15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
 546         st_d    16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
 547         st_d    17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
 548         st_d    18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
 549         st_d    19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
 550         st_d    20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
 551         st_d    21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
 552         st_d    22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
 553         st_d    23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
 554         st_d    24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
 555         st_d    25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
 556         st_d    26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
 557         st_d    27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
 558         st_d    28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
 559         st_d    29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
 560         st_d    30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
 561         st_d    31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
 562         .set    hardfloat
 563         _cfcmsa $1, MSA_CSR
 564         sw      $1, THREAD_MSA_CSR(\thread)
 565         .set    pop
 566         .endm
 567
 568         .macro  msa_restore_all thread
 569         .set    push
 570         .set    noat
 571         .set    hardfloat
 572         lw      $1, THREAD_MSA_CSR(\thread)
 573         _ctcmsa MSA_CSR, $1
 574 #ifdef TOOLCHAIN_SUPPORTS_MSA
 575         PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
 576 #endif
 577         ld_d     0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
 578         ld_d     1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
 579         ld_d     2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
 580         ld_d     3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
 581         ld_d     4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
 582         ld_d     5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
 583         ld_d     6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
 584         ld_d     7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
 585         ld_d     8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
 586         ld_d     9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
 587         ld_d    10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
 588         ld_d    11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
 589         ld_d    12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
 590         ld_d    13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
 591         ld_d    14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
 592         ld_d    15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
 593         ld_d    16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
 594         ld_d    17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
 595         ld_d    18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
 596         ld_d    19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
 597         ld_d    20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
 598         ld_d    21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
 599         ld_d    22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
 600         ld_d    23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
 601         ld_d    24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
 602         ld_d    25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
 603         ld_d    26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
 604         ld_d    27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
 605         ld_d    28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
 606         ld_d    29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
 607         ld_d    30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
 608         ld_d    31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
 609         .set pop
 610         .endm
 611
 612 #undef FPR_BASE_OFFS
 613 #undef FPR_BASE
 614
 615         .macro  msa_init_upper wd
 616 #ifdef CONFIG_64BIT
 617         insert_d \wd, 1
 618 #else
 619         insert_w \wd, 2
 620         insert_w \wd, 3
 621 #endif
 622         .endm
 623
 624         .macro  msa_init_all_upper
 625         .set    push
 626         .set    noat
 627         .set    hardfloat
 628         not     $1, zero
 629         msa_init_upper  0
 630         msa_init_upper  1
 631         msa_init_upper  2
 632         msa_init_upper  3
 633         msa_init_upper  4
 634         msa_init_upper  5
 635         msa_init_upper  6
 636         msa_init_upper  7
 637         msa_init_upper  8
 638         msa_init_upper  9
 639         msa_init_upper  10
 640         msa_init_upper  11
 641         msa_init_upper  12
 642         msa_init_upper  13
 643         msa_init_upper  14
 644         msa_init_upper  15
 645         msa_init_upper  16
 646         msa_init_upper  17
 647         msa_init_upper  18
 648         msa_init_upper  19
 649         msa_init_upper  20
 650         msa_init_upper  21
 651         msa_init_upper  22
 652         msa_init_upper  23
 653         msa_init_upper  24
 654         msa_init_upper  25
 655         msa_init_upper  26
 656         msa_init_upper  27
 657         msa_init_upper  28
 658         msa_init_upper  29
 659         msa_init_upper  30
 660         msa_init_upper  31
 661         .set    pop
 662         .endm
 663
 664 #endif /* _ASM_ASMMACRO_H */