arch/mips/include/asm/dec/kn05.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *      include/asm-mips/dec/kn05.h
   4  *
   5  *      DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
   6  *      or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
   7  *      KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
   8  *      definitions.
   9  *
  10  *      Copyright (C) 2002, 2003, 2005, 2008  Maciej W. Rozycki
  11  *
  12  *      WARNING!  All this information is pure guesswork based on the
  13  *      ROM.  It is provided here in hope it will give someone some
  14  *      food for thought.  No documentation for the KN05 nor the KN04
  15  *      module has been located so far.
  16  */
  17 #ifndef __ASM_MIPS_DEC_KN05_H
  18 #define __ASM_MIPS_DEC_KN05_H
  19
  20 #include <asm/dec/ioasic_addrs.h>
  21
  22 /*
  23  * The oncard MB (Memory Buffer) ASIC provides an additional address
  24  * decoder.  Certain address ranges within the "high" 16 slots are
  25  * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
  26  * Others are handled locally.  "Low" slots are always passed.
  27  */
  28 #define KN4K_SLOT_BASE  0x1fc00000
  29
  30 #define KN4K_MB_ROM     (0*IOASIC_SLOT_SIZE)    /* KN05/KN04 card ROM */
  31 #define KN4K_IOCTL      (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
  32 #define KN4K_ESAR       (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
  33 #define KN4K_LANCE      (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
  34 #define KN4K_MB_INT     (4*IOASIC_SLOT_SIZE)    /* MB interrupt register */
  35 #define KN4K_MB_EA      (5*IOASIC_SLOT_SIZE)    /* MB error address? */
  36 #define KN4K_MB_EC      (6*IOASIC_SLOT_SIZE)    /* MB error ??? */
  37 #define KN4K_MB_CSR     (7*IOASIC_SLOT_SIZE)    /* MB control & status */
  38 #define KN4K_RES_08     (8*IOASIC_SLOT_SIZE)    /* unused? */
  39 #define KN4K_RES_09     (9*IOASIC_SLOT_SIZE)    /* unused? */
  40 #define KN4K_RES_10     (10*IOASIC_SLOT_SIZE)   /* unused? */
  41 #define KN4K_RES_11     (11*IOASIC_SLOT_SIZE)   /* unused? */
  42 #define KN4K_SCSI       (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
  43 #define KN4K_RES_13     (13*IOASIC_SLOT_SIZE)   /* unused? */
  44 #define KN4K_RES_14     (14*IOASIC_SLOT_SIZE)   /* unused? */
  45 #define KN4K_RES_15     (15*IOASIC_SLOT_SIZE)   /* unused? */
  46
  47 /*
  48  * MB ASIC interrupt bits.
  49  */
  50 #define KN4K_MB_INR_MB          4       /* ??? */
  51 #define KN4K_MB_INR_MT          3       /* memory, I/O bus read/write errors */
  52 #define KN4K_MB_INR_RES_2       2       /* unused */
  53 #define KN4K_MB_INR_RTC         1       /* RTC */
  54 #define KN4K_MB_INR_TC          0       /* I/O ASIC cascade */
  55
  56 /*
  57  * Bits for the MB interrupt register.
  58  * The register appears read-only.
  59  */
  60 #define KN4K_MB_INT_IRQ         (0x1f<<0)       /* CPU Int[4:0] status. */
  61 #define KN4K_MB_INT_IRQ_N(n)    (1<<(n))        /* Individual status bits. */
  62
  63 /*
  64  * Bits for the MB control & status register.
  65  * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
  66  */
  67 #define KN4K_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
  68 #define KN4K_MB_CSR_F           (1<<1)          /* ??? */
  69 #define KN4K_MB_CSR_ECC         (0xff<<2)       /* ??? */
  70 #define KN4K_MB_CSR_OD          (1<<10)         /* ??? */
  71 #define KN4K_MB_CSR_CP          (1<<11)         /* ??? */
  72 #define KN4K_MB_CSR_UNC         (1<<12)         /* ??? */
  73 #define KN4K_MB_CSR_IM          (1<<13)         /* ??? */
  74 #define KN4K_MB_CSR_NC          (1<<14)         /* ??? */
  75 #define KN4K_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
  76 #define KN4K_MB_CSR_MSK         (0x1f<<16)      /* CPU Int[4:0] mask */
  77 #define KN4K_MB_CSR_MSK_N(n)    (1<<((n)+16))   /* Individual mask bits. */
  78 #define KN4K_MB_CSR_FW          (1<<21)         /* ??? */
  79 #define KN4K_MB_CSR_W           (1<<31)         /* ??? */
  80
  81 #endif /* __ASM_MIPS_DEC_KN05_H */