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drm/rockchip: vop2: Fix the windows switch between different layers
[drm/drm-misc.git] / arch / mips / include / asm / io.h
blob0bddb568af7c1cce9761bcb0face5de993cebc57
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
11 */
12 #ifndef _ASM_IO_H
13 #define _ASM_IO_H
14
15 #include <linux/compiler.h>
16 #include <linux/types.h>
17 #include <linux/irqflags.h>
18
19 #include <asm/addrspace.h>
20 #include <asm/barrier.h>
21 #include <asm/bug.h>
22 #include <asm/byteorder.h>
23 #include <asm/cpu.h>
24 #include <asm/cpu-features.h>
25 #include <asm/page.h>
26 #include <asm/pgtable-bits.h>
27 #include <asm/string.h>
28 #include <mangle-port.h>
29
30 /*
31 * Raw operations are never swapped in software. OTOH values that raw
32 * operations are working on may or may not have been swapped by the bus
33 * hardware. An example use would be for flash memory that's used for
34 * execute in place.
35 */
36 # define __raw_ioswabb(a, x) (x)
37 # define __raw_ioswabw(a, x) (x)
38 # define __raw_ioswabl(a, x) (x)
39 # define __raw_ioswabq(a, x) (x)
40 # define ____raw_ioswabq(a, x) (x)
41
42 # define _ioswabb ioswabb
43 # define _ioswabw ioswabw
44 # define _ioswabl ioswabl
45 # define _ioswabq ioswabq
46
47 # define __relaxed_ioswabb ioswabb
48 # define __relaxed_ioswabw ioswabw
49 # define __relaxed_ioswabl ioswabl
50 # define __relaxed_ioswabq ioswabq
51
52 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
53
54 /*
55 * On MIPS I/O ports are memory mapped, so we access them using normal
56 * load/store instructions. mips_io_port_base is the virtual address to
57 * which all ports are being mapped. For sake of efficiency some code
58 * assumes that this is an address that can be loaded with a single lui
59 * instruction, so the lower 16 bits must be zero. Should be true on
60 * any sane architecture; generic code does not use this assumption.
61 */
62 extern unsigned long mips_io_port_base;
63
64 static inline void set_io_port_base(unsigned long base)
65 {
66 mips_io_port_base = base;
67 }
68
69 /*
70 * Provide the necessary definitions for generic iomap. We make use of
71 * mips_io_port_base for iomap(), but we don't reserve any low addresses for
72 * use with I/O ports.
73 */
74
75 #define HAVE_ARCH_PIO_SIZE
76 #define PIO_OFFSET mips_io_port_base
77 #define PIO_MASK IO_SPACE_LIMIT
78 #define PIO_RESERVED 0x0UL
79
80 /*
81 * Enforce in-order execution of data I/O. In the MIPS architecture
82 * these are equivalent to corresponding platform-specific memory
83 * barriers defined in <asm/barrier.h>. API pinched from PowerPC,
84 * with sync additionally defined.
85 */
86 #define iobarrier_rw() mb()
87 #define iobarrier_r() rmb()
88 #define iobarrier_w() wmb()
89 #define iobarrier_sync() iob()
90
91 /*
92 * virt_to_phys - map virtual addresses to physical
93 * @address: address to remap
94 *
95 * The returned physical address is the physical (CPU) mapping for
96 * the memory address given. It is only valid to use this function on
97 * addresses directly mapped or allocated via kmalloc.
98 *
99 * This function does not give bus mappings for DMA transfers. In
100 * almost all conceivable cases a device driver should not be using
101 * this function
102 */
103 static inline unsigned long __virt_to_phys_nodebug(volatile const void *address)
104 {
105 return __pa(address);
106 }
107
108 #ifdef CONFIG_DEBUG_VIRTUAL
109 extern phys_addr_t __virt_to_phys(volatile const void *x);
110 #else
111 #define __virt_to_phys(x) __virt_to_phys_nodebug(x)
112 #endif
113
114 #define virt_to_phys virt_to_phys
115 static inline phys_addr_t virt_to_phys(const volatile void *x)
116 {
117 return __virt_to_phys(x);
118 }
119
120 /*
121 * ISA I/O bus memory addresses are 1:1 with the physical address.
122 */
123 static inline unsigned long isa_virt_to_bus(volatile void *address)
124 {
125 return virt_to_phys(address);
126 }
127
128 void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
129 unsigned long prot_val);
130 void iounmap(const volatile void __iomem *addr);
131
132 /*
133 * ioremap - map bus memory into CPU space
134 * @offset: bus address of the memory
135 * @size: size of the resource to map
136 *
137 * ioremap performs a platform specific sequence of operations to
138 * make bus memory CPU accessible via the readb/readw/readl/writeb/
139 * writew/writel functions and the other mmio helpers. The returned
140 * address is not guaranteed to be usable directly as a virtual
141 * address.
142 */
143 #define ioremap(offset, size) \
144 ioremap_prot((offset), (size), _CACHE_UNCACHED)
145
146 /*
147 * ioremap_cache - map bus memory into CPU space
148 * @offset: bus address of the memory
149 * @size: size of the resource to map
150 *
151 * ioremap_cache performs a platform specific sequence of operations to
152 * make bus memory CPU accessible via the readb/readw/readl/writeb/
153 * writew/writel functions and the other mmio helpers. The returned
154 * address is not guaranteed to be usable directly as a virtual
155 * address.
156 *
157 * This version of ioremap ensures that the memory is marked cacheable by
158 * the CPU. Also enables full write-combining. Useful for some
159 * memory-like regions on I/O busses.
160 */
161 #define ioremap_cache(offset, size) \
162 ioremap_prot((offset), (size), _page_cachable_default)
163
164 /*
165 * ioremap_wc - map bus memory into CPU space
166 * @offset: bus address of the memory
167 * @size: size of the resource to map
168 *
169 * ioremap_wc performs a platform specific sequence of operations to
170 * make bus memory CPU accessible via the readb/readw/readl/writeb/
171 * writew/writel functions and the other mmio helpers. The returned
172 * address is not guaranteed to be usable directly as a virtual
173 * address.
174 *
175 * This version of ioremap ensures that the memory is marked uncacheable
176 * but accelerated by means of write-combining feature. It is specifically
177 * useful for PCIe prefetchable windows, which may vastly improve a
178 * communications performance. If it was determined on boot stage, what
179 * CPU CCA doesn't support UCA, the method shall fall-back to the
180 * _CACHE_UNCACHED option (see cpu_probe() method).
181 */
182 #define ioremap_wc(offset, size) \
183 ioremap_prot((offset), (size), boot_cpu_data.writecombine)
184
185 #if defined(CONFIG_CPU_CAVIUM_OCTEON)
186 #define war_io_reorder_wmb() wmb()
187 #else
188 #define war_io_reorder_wmb() barrier()
189 #endif
190
191 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
192 \
193 static inline void pfx##write##bwlq(type val, \
194 volatile void __iomem *mem) \
195 { \
196 volatile type *__mem; \
197 type __val; \
198 \
199 if (barrier) \
200 iobarrier_rw(); \
201 else \
202 war_io_reorder_wmb(); \
203 \
204 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
205 \
206 __val = pfx##ioswab##bwlq(__mem, val); \
207 \
208 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
209 *__mem = __val; \
210 else if (cpu_has_64bits) { \
211 unsigned long __flags; \
212 type __tmp; \
213 \
214 if (irq) \
215 local_irq_save(__flags); \
216 __asm__ __volatile__( \
217 ".set push" "\t\t# __writeq""\n\t" \
218 ".set arch=r4000" "\n\t" \
219 "dsll32 %L0, %L0, 0" "\n\t" \
220 "dsrl32 %L0, %L0, 0" "\n\t" \
221 "dsll32 %M0, %M0, 0" "\n\t" \
222 "or %L0, %L0, %M0" "\n\t" \
223 "sd %L0, %2" "\n\t" \
224 ".set pop" "\n" \
225 : "=r" (__tmp) \
226 : "0" (__val), "m" (*__mem)); \
227 if (irq) \
228 local_irq_restore(__flags); \
229 } else \
230 BUG(); \
231 } \
232 \
233 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
234 { \
235 volatile type *__mem; \
236 type __val; \
237 \
238 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
239 \
240 if (barrier) \
241 iobarrier_rw(); \
242 \
243 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
244 __val = *__mem; \
245 else if (cpu_has_64bits) { \
246 unsigned long __flags; \
247 \
248 if (irq) \
249 local_irq_save(__flags); \
250 __asm__ __volatile__( \
251 ".set push" "\t\t# __readq" "\n\t" \
252 ".set arch=r4000" "\n\t" \
253 "ld %L0, %1" "\n\t" \
254 "dsra32 %M0, %L0, 0" "\n\t" \
255 "sll %L0, %L0, 0" "\n\t" \
256 ".set pop" "\n" \
257 : "=r" (__val) \
258 : "m" (*__mem)); \
259 if (irq) \
260 local_irq_restore(__flags); \
261 } else { \
262 __val = 0; \
263 BUG(); \
264 } \
265 \
266 /* prevent prefetching of coherent DMA data prematurely */ \
267 if (!relax) \
268 rmb(); \
269 return pfx##ioswab##bwlq(__mem, __val); \
270 }
271
272 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax) \
273 \
274 static inline void pfx##out##bwlq(type val, unsigned long port) \
275 { \
276 volatile type *__addr; \
277 type __val; \
278 \
279 if (barrier) \
280 iobarrier_rw(); \
281 else \
282 war_io_reorder_wmb(); \
283 \
284 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
285 \
286 __val = pfx##ioswab##bwlq(__addr, val); \
287 \
288 /* Really, we want this to be atomic */ \
289 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
290 \
291 *__addr = __val; \
292 } \
293 \
294 static inline type pfx##in##bwlq(unsigned long port) \
295 { \
296 volatile type *__addr; \
297 type __val; \
298 \
299 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
300 \
301 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
302 \
303 if (barrier) \
304 iobarrier_rw(); \
305 \
306 __val = *__addr; \
307 \
308 /* prevent prefetching of coherent DMA data prematurely */ \
309 if (!relax) \
310 rmb(); \
311 return pfx##ioswab##bwlq(__addr, __val); \
312 }
313
314 #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \
315 \
316 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
317
318 #define BUILDIO_MEM(bwlq, type) \
319 \
320 __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \
321 __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \
322 __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \
323 __BUILD_MEMORY_PFX(, bwlq, type, 0)
324
325 BUILDIO_MEM(b, u8)
326 BUILDIO_MEM(w, u16)
327 BUILDIO_MEM(l, u32)
328 #ifdef CONFIG_64BIT
329 BUILDIO_MEM(q, u64)
330 #else
331 __BUILD_MEMORY_PFX(__raw_, q, u64, 0)
332 __BUILD_MEMORY_PFX(__mem_, q, u64, 0)
333 #endif
334
335 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
336 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0)
337
338 #define BUILDIO_IOPORT(bwlq, type) \
339 __BUILD_IOPORT_PFX(_, bwlq, type) \
340 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
341
342 BUILDIO_IOPORT(b, u8)
343 BUILDIO_IOPORT(w, u16)
344 BUILDIO_IOPORT(l, u32)
345 #ifdef CONFIG_64BIT
346 BUILDIO_IOPORT(q, u64)
347 #endif
348
349 #define __BUILDIO(bwlq, type) \
350 \
351 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
352
353 __BUILDIO(q, u64)
354
355 #define readb_relaxed __relaxed_readb
356 #define readw_relaxed __relaxed_readw
357 #define readl_relaxed __relaxed_readl
358 #ifdef CONFIG_64BIT
359 #define readq_relaxed __relaxed_readq
360 #endif
361
362 #define writeb_relaxed __relaxed_writeb
363 #define writew_relaxed __relaxed_writew
364 #define writel_relaxed __relaxed_writel
365 #ifdef CONFIG_64BIT
366 #define writeq_relaxed __relaxed_writeq
367 #endif
368
369 #define readb_be(addr) \
370 __raw_readb((__force unsigned *)(addr))
371 #define readw_be(addr) \
372 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
373 #define readl_be(addr) \
374 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
375 #define readq_be(addr) \
376 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
377
378 #define writeb_be(val, addr) \
379 __raw_writeb((val), (__force unsigned *)(addr))
380 #define writew_be(val, addr) \
381 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
382 #define writel_be(val, addr) \
383 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
384 #define writeq_be(val, addr) \
385 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
386
387 #define __BUILD_MEMORY_STRING(bwlq, type) \
388 \
389 static inline void writes##bwlq(volatile void __iomem *mem, \
390 const void *addr, unsigned int count) \
391 { \
392 const volatile type *__addr = addr; \
393 \
394 while (count--) { \
395 __mem_write##bwlq(*__addr, mem); \
396 __addr++; \
397 } \
398 } \
399 \
400 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
401 unsigned int count) \
402 { \
403 volatile type *__addr = addr; \
404 \
405 while (count--) { \
406 *__addr = __mem_read##bwlq(mem); \
407 __addr++; \
408 } \
409 }
410
411 #define __BUILD_IOPORT_STRING(bwlq, type) \
412 \
413 static inline void outs##bwlq(unsigned long port, const void *addr, \
414 unsigned int count) \
415 { \
416 const volatile type *__addr = addr; \
417 \
418 while (count--) { \
419 __mem_out##bwlq(*__addr, port); \
420 __addr++; \
421 } \
422 } \
423 \
424 static inline void ins##bwlq(unsigned long port, void *addr, \
425 unsigned int count) \
426 { \
427 volatile type *__addr = addr; \
428 \
429 while (count--) { \
430 *__addr = __mem_in##bwlq(port); \
431 __addr++; \
432 } \
433 }
434
435 #define BUILDSTRING(bwlq, type) \
436 \
437 __BUILD_MEMORY_STRING(bwlq, type) \
438 __BUILD_IOPORT_STRING(bwlq, type)
439
440 BUILDSTRING(b, u8)
441 BUILDSTRING(w, u16)
442 BUILDSTRING(l, u32)
443 #ifdef CONFIG_64BIT
444 BUILDSTRING(q, u64)
445 #endif
446
447
448 /*
449 * The caches on some architectures aren't dma-coherent and have need to
450 * handle this in software. There are three types of operations that
451 * can be applied to dma buffers.
452 *
453 * - dma_cache_wback_inv(start, size) makes caches and coherent by
454 * writing the content of the caches back to memory, if necessary.
455 * The function also invalidates the affected part of the caches as
456 * necessary before DMA transfers from outside to memory.
457 * - dma_cache_wback(start, size) makes caches and coherent by
458 * writing the content of the caches back to memory, if necessary.
459 * The function also invalidates the affected part of the caches as
460 * necessary before DMA transfers from outside to memory.
461 * - dma_cache_inv(start, size) invalidates the affected parts of the
462 * caches. Dirty lines of the caches may be written back or simply
463 * be discarded. This operation is necessary before dma operations
464 * to the memory.
465 *
466 * This API used to be exported; it now is for arch code internal use only.
467 */
468 #ifdef CONFIG_DMA_NONCOHERENT
469
470 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
471 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
472 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
473
474 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
475 #define dma_cache_wback(start, size) _dma_cache_wback(start, size)
476 #define dma_cache_inv(start, size) _dma_cache_inv(start, size)
477
478 #else /* Sane hardware */
479
480 #define dma_cache_wback_inv(start,size) \
481 do { (void) (start); (void) (size); } while (0)
482 #define dma_cache_wback(start,size) \
483 do { (void) (start); (void) (size); } while (0)
484 #define dma_cache_inv(start,size) \
485 do { (void) (start); (void) (size); } while (0)
486
487 #endif /* CONFIG_DMA_NONCOHERENT */
488
489 /*
490 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
491 * Avoid interrupt mucking, just adjust the address for 4-byte access.
492 * Assume the addresses are 8-byte aligned.
493 */
494 #ifdef __MIPSEB__
495 #define __CSR_32_ADJUST 4
496 #else
497 #define __CSR_32_ADJUST 0
498 #endif
499
500 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
501 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
502
503 #define __raw_readb __raw_readb
504 #define __raw_readw __raw_readw
505 #define __raw_readl __raw_readl
506 #ifdef CONFIG_64BIT
507 #define __raw_readq __raw_readq
508 #endif
509 #define __raw_writeb __raw_writeb
510 #define __raw_writew __raw_writew
511 #define __raw_writel __raw_writel
512 #ifdef CONFIG_64BIT
513 #define __raw_writeq __raw_writeq
514 #endif
515
516 #define readb readb
517 #define readw readw
518 #define readl readl
519 #ifdef CONFIG_64BIT
520 #define readq readq
521 #endif
522 #define writeb writeb
523 #define writew writew
524 #define writel writel
525 #ifdef CONFIG_64BIT
526 #define writeq writeq
527 #endif
528
529 #define readsb readsb
530 #define readsw readsw
531 #define readsl readsl
532 #ifdef CONFIG_64BIT
533 #define readsq readsq
534 #endif
535 #define writesb writesb
536 #define writesw writesw
537 #define writesl writesl
538 #ifdef CONFIG_64BIT
539 #define writesq writesq
540 #endif
541
542 #define _inb _inb
543 #define _inw _inw
544 #define _inl _inl
545 #define insb insb
546 #define insw insw
547 #define insl insl
548
549 #define _outb _outb
550 #define _outw _outw
551 #define _outl _outl
552 #define outsb outsb
553 #define outsw outsw
554 #define outsl outsl
555
556 void __ioread64_copy(void *to, const void __iomem *from, size_t count);
557
558 #include <asm-generic/io.h>
559
560 static inline void *isa_bus_to_virt(unsigned long address)
561 {
562 return phys_to_virt(address);
563 }
564
565 #endif /* _ASM_IO_H */
Kernel DRM miscellaneous fixes and cross-tree changes