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drm/rockchip: vop2: Fix the windows switch between different layers
[drm/drm-misc.git] / arch / mips / include / asm / mach-au1x00 / gpio-au1000.h
blobd820b481ac564198096328176cbb103993392994
1 /*
2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
3 *
4 * Copyright (c) 2009 Manuel Lauss.
5 *
6 * Licensed under the terms outlined in the file COPYING.
7 */
8
9 #ifndef _ALCHEMY_GPIO_AU1000_H_
10 #define _ALCHEMY_GPIO_AU1000_H_
11
12 #include <asm/mach-au1x00/au1000.h>
13
14 /* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
16 */
17 #define ALCHEMY_GPIO1_BASE 0
18 #define ALCHEMY_GPIO2_BASE 200
19
20 #define ALCHEMY_GPIO1_NUM 32
21 #define ALCHEMY_GPIO2_NUM 16
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
24
25 #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
26
27 /* GPIO1 registers within SYS_ area */
28 #define AU1000_SYS_TRIOUTRD 0x100
29 #define AU1000_SYS_TRIOUTCLR 0x100
30 #define AU1000_SYS_OUTPUTRD 0x108
31 #define AU1000_SYS_OUTPUTSET 0x108
32 #define AU1000_SYS_OUTPUTCLR 0x10C
33 #define AU1000_SYS_PINSTATERD 0x110
34 #define AU1000_SYS_PININPUTEN 0x110
35
36 /* register offsets within GPIO2 block */
37 #define AU1000_GPIO2_DIR 0x00
38 #define AU1000_GPIO2_OUTPUT 0x08
39 #define AU1000_GPIO2_PINSTATE 0x0C
40 #define AU1000_GPIO2_INTENABLE 0x10
41 #define AU1000_GPIO2_ENABLE 0x14
42
43 struct gpio;
44
45 static inline int au1000_gpio1_to_irq(int gpio)
46 {
47 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
48 }
49
50 static inline int au1000_gpio2_to_irq(int gpio)
51 {
52 return -ENXIO;
53 }
54
55 static inline int au1000_irq_to_gpio(int irq)
56 {
57 if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
58 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
59
60 return -ENXIO;
61 }
62
63 static inline int au1500_gpio1_to_irq(int gpio)
64 {
65 gpio -= ALCHEMY_GPIO1_BASE;
66
67 switch (gpio) {
68 case 0 ... 15:
69 case 20:
70 case 23 ... 28: return MAKE_IRQ(1, gpio);
71 }
72
73 return -ENXIO;
74 }
75
76 static inline int au1500_gpio2_to_irq(int gpio)
77 {
78 gpio -= ALCHEMY_GPIO2_BASE;
79
80 switch (gpio) {
81 case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
82 case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
83 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
84 }
85
86 return -ENXIO;
87 }
88
89 static inline int au1500_irq_to_gpio(int irq)
90 {
91 switch (irq) {
92 case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
93 case AU1500_GPIO20_INT:
94 case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
95 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
96 case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
97 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
98 case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
99 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
100 case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
101 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
102 case AU1500_GPIO208_215_INT:
103 return ALCHEMY_GPIO2_BASE + 8;
104 }
105
106 return -ENXIO;
107 }
108
109 static inline int au1100_gpio1_to_irq(int gpio)
110 {
111 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
112 }
113
114 static inline int au1100_gpio2_to_irq(int gpio)
115 {
116 gpio -= ALCHEMY_GPIO2_BASE;
117
118 if ((gpio >= 8) && (gpio <= 15))
119 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
120
121 return -ENXIO;
122 }
123
124 static inline int au1100_irq_to_gpio(int irq)
125 {
126 switch (irq) {
127 case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
128 return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
129 case AU1100_GPIO208_215_INT:
130 return ALCHEMY_GPIO2_BASE + 8;
131 }
132
133 return -ENXIO;
134 }
135
136 static inline int au1550_gpio1_to_irq(int gpio)
137 {
138 gpio -= ALCHEMY_GPIO1_BASE;
139
140 switch (gpio) {
141 case 0 ... 15:
142 case 20 ... 28: return MAKE_IRQ(1, gpio);
143 case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
144 }
145
146 return -ENXIO;
147 }
148
149 static inline int au1550_gpio2_to_irq(int gpio)
150 {
151 gpio -= ALCHEMY_GPIO2_BASE;
152
153 switch (gpio) {
154 case 0: return MAKE_IRQ(1, 16);
155 case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
156 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
157 case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
158 }
159
160 return -ENXIO;
161 }
162
163 static inline int au1550_irq_to_gpio(int irq)
164 {
165 switch (irq) {
166 case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
167 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
168 case AU1550_GPIO200_INT:
169 case AU1550_GPIO201_205_INT:
170 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
171 case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
172 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
173 case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
174 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
175 }
176
177 return -ENXIO;
178 }
179
180 static inline int au1200_gpio1_to_irq(int gpio)
181 {
182 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
183 }
184
185 static inline int au1200_gpio2_to_irq(int gpio)
186 {
187 gpio -= ALCHEMY_GPIO2_BASE;
188
189 switch (gpio) {
190 case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
191 case 3: return MAKE_IRQ(0, 22);
192 case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
193 case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
194 }
195
196 return -ENXIO;
197 }
198
199 static inline int au1200_irq_to_gpio(int irq)
200 {
201 switch (irq) {
202 case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
203 return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
204 case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
205 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
206 case AU1200_GPIO203_INT:
207 return ALCHEMY_GPIO2_BASE + 3;
208 case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
209 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
210 }
211
212 return -ENXIO;
213 }
214
215 /*
216 * GPIO1 block macros for common linux gpio functions.
217 */
218 static inline void alchemy_gpio1_set_value(int gpio, int v)
219 {
220 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
221 unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;
222 alchemy_wrsys(mask, r);
223 }
224
225 static inline int alchemy_gpio1_get_value(int gpio)
226 {
227 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
228 return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask;
229 }
230
231 static inline int alchemy_gpio1_direction_input(int gpio)
232 {
233 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
234 alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR);
235 return 0;
236 }
237
238 static inline int alchemy_gpio1_direction_output(int gpio, int v)
239 {
240 /* hardware switches to "output" mode when one of the two
241 * "set_value" registers is accessed.
242 */
243 alchemy_gpio1_set_value(gpio, v);
244 return 0;
245 }
246
247 static inline int alchemy_gpio1_is_valid(int gpio)
248 {
249 return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
250 }
251
252 static inline int alchemy_gpio1_to_irq(int gpio)
253 {
254 switch (alchemy_get_cputype()) {
255 case ALCHEMY_CPU_AU1000:
256 return au1000_gpio1_to_irq(gpio);
257 case ALCHEMY_CPU_AU1100:
258 return au1100_gpio1_to_irq(gpio);
259 case ALCHEMY_CPU_AU1500:
260 return au1500_gpio1_to_irq(gpio);
261 case ALCHEMY_CPU_AU1550:
262 return au1550_gpio1_to_irq(gpio);
263 case ALCHEMY_CPU_AU1200:
264 return au1200_gpio1_to_irq(gpio);
265 }
266 return -ENXIO;
267 }
268
269 /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
270 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
271 * register enables use of GPIOs as wake source.
272 */
273 static inline void alchemy_gpio1_input_enable(void)
274 {
275 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
276 __raw_writel(0, base + 0x110); /* the write op is key */
277 wmb();
278 }
279
280 /*
281 * GPIO2 block macros for common linux GPIO functions. The 'gpio'
282 * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
283 */
284 static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
285 {
286 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
287 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
288 unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR);
289
290 if (to_out)
291 d |= mask;
292 else
293 d &= ~mask;
294 __raw_writel(d, base + AU1000_GPIO2_DIR);
295 wmb();
296 }
297
298 static inline void alchemy_gpio2_set_value(int gpio, int v)
299 {
300 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
301 unsigned long mask;
302 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
303 __raw_writel(mask, base + AU1000_GPIO2_OUTPUT);
304 wmb();
305 }
306
307 static inline int alchemy_gpio2_get_value(int gpio)
308 {
309 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
310 return __raw_readl(base + AU1000_GPIO2_PINSTATE) &
311 (1 << (gpio - ALCHEMY_GPIO2_BASE));
312 }
313
314 static inline int alchemy_gpio2_direction_input(int gpio)
315 {
316 unsigned long flags;
317 local_irq_save(flags);
318 __alchemy_gpio2_mod_dir(gpio, 0);
319 local_irq_restore(flags);
320 return 0;
321 }
322
323 static inline int alchemy_gpio2_direction_output(int gpio, int v)
324 {
325 unsigned long flags;
326 alchemy_gpio2_set_value(gpio, v);
327 local_irq_save(flags);
328 __alchemy_gpio2_mod_dir(gpio, 1);
329 local_irq_restore(flags);
330 return 0;
331 }
332
333 static inline int alchemy_gpio2_is_valid(int gpio)
334 {
335 return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
336 }
337
338 static inline int alchemy_gpio2_to_irq(int gpio)
339 {
340 switch (alchemy_get_cputype()) {
341 case ALCHEMY_CPU_AU1000:
342 return au1000_gpio2_to_irq(gpio);
343 case ALCHEMY_CPU_AU1100:
344 return au1100_gpio2_to_irq(gpio);
345 case ALCHEMY_CPU_AU1500:
346 return au1500_gpio2_to_irq(gpio);
347 case ALCHEMY_CPU_AU1550:
348 return au1550_gpio2_to_irq(gpio);
349 case ALCHEMY_CPU_AU1200:
350 return au1200_gpio2_to_irq(gpio);
351 }
352 return -ENXIO;
353 }
354
355 /**********************************************************************/
356
357 /* GPIO2 shared interrupts and control */
358
359 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
360 {
361 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
362 unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE);
363 if (en)
364 r |= 1 << gpio2;
365 else
366 r &= ~(1 << gpio2);
367 __raw_writel(r, base + AU1000_GPIO2_INTENABLE);
368 wmb();
369 }
370
371 /**
372 * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
373 * @gpio2: The GPIO2 pin to activate (200...215).
374 *
375 * GPIO208-215 have one shared interrupt line to the INTC. They are
376 * and'ed with a per-pin enable bit and finally or'ed together to form
377 * a single irq request (useful for active-high sources).
378 * With this function, a pins' individual contribution to the int request
379 * can be enabled. As with all other GPIO-based interrupts, the INTC
380 * must be programmed to accept the GPIO208_215 interrupt as well.
381 *
382 * NOTE: Calling this macro is only necessary for GPIO208-215; all other
383 * GPIO2-based interrupts have their own request to the INTC. Please
384 * consult your Alchemy databook for more information!
385 *
386 * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
387 * line to the INTC, GPIO201_205. This function can be used for those
388 * as well.
389 *
390 * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
391 * (200-215 by default). No sanity checks are made,
392 */
393 static inline void alchemy_gpio2_enable_int(int gpio2)
394 {
395 unsigned long flags;
396
397 gpio2 -= ALCHEMY_GPIO2_BASE;
398
399 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
400 switch (alchemy_get_cputype()) {
401 case ALCHEMY_CPU_AU1100:
402 case ALCHEMY_CPU_AU1500:
403 gpio2 -= 8;
404 }
405
406 local_irq_save(flags);
407 __alchemy_gpio2_mod_int(gpio2, 1);
408 local_irq_restore(flags);
409 }
410
411 /**
412 * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
413 * @gpio2: The GPIO2 pin to activate (200...215).
414 *
415 * see function alchemy_gpio2_enable_int() for more information.
416 */
417 static inline void alchemy_gpio2_disable_int(int gpio2)
418 {
419 unsigned long flags;
420
421 gpio2 -= ALCHEMY_GPIO2_BASE;
422
423 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
424 switch (alchemy_get_cputype()) {
425 case ALCHEMY_CPU_AU1100:
426 case ALCHEMY_CPU_AU1500:
427 gpio2 -= 8;
428 }
429
430 local_irq_save(flags);
431 __alchemy_gpio2_mod_int(gpio2, 0);
432 local_irq_restore(flags);
433 }
434
435 /**
436 * alchemy_gpio2_enable - Activate GPIO2 block.
437 *
438 * The GPIO2 block must be enabled explicitly to work. On systems
439 * where this isn't done by the bootloader, this macro can be used.
440 */
441 static inline void alchemy_gpio2_enable(void)
442 {
443 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
444 __raw_writel(3, base + AU1000_GPIO2_ENABLE); /* reset, clock enabled */
445 wmb();
446 __raw_writel(1, base + AU1000_GPIO2_ENABLE); /* clock enabled */
447 wmb();
448 }
449
450 /**
451 * alchemy_gpio2_disable - disable GPIO2 block.
452 *
453 * Disable and put GPIO2 block in low-power mode.
454 */
455 static inline void alchemy_gpio2_disable(void)
456 {
457 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
458 __raw_writel(2, base + AU1000_GPIO2_ENABLE); /* reset, clock disabled */
459 wmb();
460 }
461
462 /**********************************************************************/
463
464 /* wrappers for on-chip gpios; can be used before gpio chips have been
465 * registered with gpiolib.
466 */
467 static inline int alchemy_gpio_direction_input(int gpio)
468 {
469 return (gpio >= ALCHEMY_GPIO2_BASE) ?
470 alchemy_gpio2_direction_input(gpio) :
471 alchemy_gpio1_direction_input(gpio);
472 }
473
474 static inline int alchemy_gpio_direction_output(int gpio, int v)
475 {
476 return (gpio >= ALCHEMY_GPIO2_BASE) ?
477 alchemy_gpio2_direction_output(gpio, v) :
478 alchemy_gpio1_direction_output(gpio, v);
479 }
480
481 static inline int alchemy_gpio_get_value(int gpio)
482 {
483 return (gpio >= ALCHEMY_GPIO2_BASE) ?
484 alchemy_gpio2_get_value(gpio) :
485 alchemy_gpio1_get_value(gpio);
486 }
487
488 static inline void alchemy_gpio_set_value(int gpio, int v)
489 {
490 if (gpio >= ALCHEMY_GPIO2_BASE)
491 alchemy_gpio2_set_value(gpio, v);
492 else
493 alchemy_gpio1_set_value(gpio, v);
494 }
495
496 static inline int alchemy_gpio_is_valid(int gpio)
497 {
498 return (gpio >= ALCHEMY_GPIO2_BASE) ?
499 alchemy_gpio2_is_valid(gpio) :
500 alchemy_gpio1_is_valid(gpio);
501 }
502
503 static inline int alchemy_gpio_to_irq(int gpio)
504 {
505 return (gpio >= ALCHEMY_GPIO2_BASE) ?
506 alchemy_gpio2_to_irq(gpio) :
507 alchemy_gpio1_to_irq(gpio);
508 }
509
510 static inline int alchemy_irq_to_gpio(int irq)
511 {
512 switch (alchemy_get_cputype()) {
513 case ALCHEMY_CPU_AU1000:
514 return au1000_irq_to_gpio(irq);
515 case ALCHEMY_CPU_AU1100:
516 return au1100_irq_to_gpio(irq);
517 case ALCHEMY_CPU_AU1500:
518 return au1500_irq_to_gpio(irq);
519 case ALCHEMY_CPU_AU1550:
520 return au1550_irq_to_gpio(irq);
521 case ALCHEMY_CPU_AU1200:
522 return au1200_irq_to_gpio(irq);
523 }
524 return -ENXIO;
525 }
526
527 #endif /* _ALCHEMY_GPIO_AU1000_H_ */
Kernel DRM miscellaneous fixes and cross-tree changes