arch/mips/include/asm/mach-ralink/rt3883.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Ralink RT3662/RT3883 SoC register definitions
   4  *
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  */
   7
   8 #ifndef _RT3883_REGS_H_
   9 #define _RT3883_REGS_H_
  10
  11 #include <linux/bitops.h>
  12
  13 #define IOMEM(x)                ((void __iomem *)(KSEG1ADDR(x)))
  14
  15 #define RT3883_SDRAM_BASE       0x00000000
  16 #define RT3883_SYSC_BASE        IOMEM(0x10000000)
  17 #define RT3883_TIMER_BASE       0x10000100
  18 #define RT3883_INTC_BASE        0x10000200
  19 #define RT3883_MEMC_BASE        0x10000300
  20 #define RT3883_UART0_BASE       0x10000500
  21 #define RT3883_PIO_BASE         0x10000600
  22 #define RT3883_FSCC_BASE        0x10000700
  23 #define RT3883_NANDC_BASE       0x10000810
  24 #define RT3883_I2C_BASE         0x10000900
  25 #define RT3883_I2S_BASE         0x10000a00
  26 #define RT3883_SPI_BASE         0x10000b00
  27 #define RT3883_UART1_BASE       0x10000c00
  28 #define RT3883_PCM_BASE         0x10002000
  29 #define RT3883_GDMA_BASE        0x10002800
  30 #define RT3883_CODEC1_BASE      0x10003000
  31 #define RT3883_CODEC2_BASE      0x10003800
  32 #define RT3883_FE_BASE          0x10100000
  33 #define RT3883_ROM_BASE         0x10118000
  34 #define RT3883_USBDEV_BASE      0x10112000
  35 #define RT3883_PCI_BASE         0x10140000
  36 #define RT3883_WLAN_BASE        0x10180000
  37 #define RT3883_USBHOST_BASE     0x101c0000
  38 #define RT3883_BOOT_BASE        0x1c000000
  39 #define RT3883_SRAM_BASE        0x1e000000
  40 #define RT3883_PCIMEM_BASE      0x20000000
  41
  42 #define RT3883_EHCI_BASE        (RT3883_USBHOST_BASE)
  43 #define RT3883_OHCI_BASE        (RT3883_USBHOST_BASE + 0x1000)
  44
  45 #define RT3883_SYSC_SIZE        0x100
  46 #define RT3883_TIMER_SIZE       0x100
  47 #define RT3883_INTC_SIZE        0x100
  48 #define RT3883_MEMC_SIZE        0x100
  49 #define RT3883_UART0_SIZE       0x100
  50 #define RT3883_UART1_SIZE       0x100
  51 #define RT3883_PIO_SIZE         0x100
  52 #define RT3883_FSCC_SIZE        0x100
  53 #define RT3883_NANDC_SIZE       0x0f0
  54 #define RT3883_I2C_SIZE         0x100
  55 #define RT3883_I2S_SIZE         0x100
  56 #define RT3883_SPI_SIZE         0x100
  57 #define RT3883_PCM_SIZE         0x800
  58 #define RT3883_GDMA_SIZE        0x800
  59 #define RT3883_CODEC1_SIZE      0x800
  60 #define RT3883_CODEC2_SIZE      0x800
  61 #define RT3883_FE_SIZE          0x10000
  62 #define RT3883_ROM_SIZE         0x4000
  63 #define RT3883_USBDEV_SIZE      0x4000
  64 #define RT3883_PCI_SIZE         0x40000
  65 #define RT3883_WLAN_SIZE        0x40000
  66 #define RT3883_USBHOST_SIZE     0x40000
  67 #define RT3883_BOOT_SIZE        (32 * 1024 * 1024)
  68 #define RT3883_SRAM_SIZE        (32 * 1024 * 1024)
  69
  70 /* SYSC registers */
  71 #define RT3883_SYSC_REG_CHIPID0_3       0x00    /* Chip ID 0 */
  72 #define RT3883_SYSC_REG_CHIPID4_7       0x04    /* Chip ID 1 */
  73 #define RT3883_SYSC_REG_REVID           0x0c    /* Chip Revision Identification */
  74 #define RT3883_SYSC_REG_SYSCFG0         0x10    /* System Configuration 0 */
  75 #define RT3883_SYSC_REG_SYSCFG1         0x14    /* System Configuration 1 */
  76 #define RT3883_SYSC_REG_CLKCFG0         0x2c    /* Clock Configuration 0 */
  77 #define RT3883_SYSC_REG_CLKCFG1         0x30    /* Clock Configuration 1 */
  78 #define RT3883_SYSC_REG_RSTCTRL         0x34    /* Reset Control*/
  79 #define RT3883_SYSC_REG_RSTSTAT         0x38    /* Reset Status*/
  80 #define RT3883_SYSC_REG_USB_PS          0x5c    /* USB Power saving control */
  81 #define RT3883_SYSC_REG_GPIO_MODE       0x60    /* GPIO Purpose Select */
  82 #define RT3883_SYSC_REG_PCIE_CLK_GEN0   0x7c
  83 #define RT3883_SYSC_REG_PCIE_CLK_GEN1   0x80
  84 #define RT3883_SYSC_REG_PCIE_CLK_GEN2   0x84
  85 #define RT3883_SYSC_REG_PMU             0x88
  86 #define RT3883_SYSC_REG_PMU1            0x8c
  87
  88 #define RT3883_CHIP_NAME0               0x38335452
  89 #define RT3883_CHIP_NAME1               0x20203338
  90
  91 #define RT3883_REVID_VER_ID_MASK        0x0f
  92 #define RT3883_REVID_VER_ID_SHIFT       8
  93 #define RT3883_REVID_ECO_ID_MASK        0x0f
  94
  95 #define RT3883_SYSCFG1_USB0_HOST_MODE   BIT(10)
  96 #define RT3883_SYSCFG1_PCIE_RC_MODE     BIT(8)
  97 #define RT3883_SYSCFG1_PCI_HOST_MODE    BIT(7)
  98 #define RT3883_SYSCFG1_PCI_66M_MODE     BIT(6)
  99 #define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
 100
 101 #define RT3883_CLKCFG1_PCIE_CLK_EN      BIT(21)
 102 #define RT3883_CLKCFG1_UPHY1_CLK_EN     BIT(20)
 103 #define RT3883_CLKCFG1_PCI_CLK_EN       BIT(19)
 104 #define RT3883_CLKCFG1_UPHY0_CLK_EN     BIT(18)
 105
 106 #define RT3883_GPIO_I2C_SD              1
 107 #define RT3883_GPIO_I2C_SCLK            2
 108 #define RT3883_GPIO_SPI_CS0             3
 109 #define RT3883_GPIO_SPI_CLK             4
 110 #define RT3883_GPIO_SPI_MOSI            5
 111 #define RT3883_GPIO_SPI_MISO            6
 112 #define RT3883_GPIO_7                   7
 113 #define RT3883_GPIO_10                  10
 114 #define RT3883_GPIO_11                  11
 115 #define RT3883_GPIO_14                  14
 116 #define RT3883_GPIO_UART1_TXD           15
 117 #define RT3883_GPIO_UART1_RXD           16
 118 #define RT3883_GPIO_JTAG_TDO            17
 119 #define RT3883_GPIO_JTAG_TDI            18
 120 #define RT3883_GPIO_JTAG_TMS            19
 121 #define RT3883_GPIO_JTAG_TCLK           20
 122 #define RT3883_GPIO_JTAG_TRST_N         21
 123 #define RT3883_GPIO_MDIO_MDC            22
 124 #define RT3883_GPIO_MDIO_MDIO           23
 125 #define RT3883_GPIO_LNA_PE_A0           32
 126 #define RT3883_GPIO_LNA_PE_A1           33
 127 #define RT3883_GPIO_LNA_PE_A2           34
 128 #define RT3883_GPIO_LNA_PE_G0           35
 129 #define RT3883_GPIO_LNA_PE_G1           36
 130 #define RT3883_GPIO_LNA_PE_G2           37
 131 #define RT3883_GPIO_PCI_AD0             40
 132 #define RT3883_GPIO_PCI_AD31            71
 133 #define RT3883_GPIO_GE2_TXD0            72
 134 #define RT3883_GPIO_GE2_TXD1            73
 135 #define RT3883_GPIO_GE2_TXD2            74
 136 #define RT3883_GPIO_GE2_TXD3            75
 137 #define RT3883_GPIO_GE2_TXEN            76
 138 #define RT3883_GPIO_GE2_TXCLK           77
 139 #define RT3883_GPIO_GE2_RXD0            78
 140 #define RT3883_GPIO_GE2_RXD1            79
 141 #define RT3883_GPIO_GE2_RXD2            80
 142 #define RT3883_GPIO_GE2_RXD3            81
 143 #define RT3883_GPIO_GE2_RXDV            82
 144 #define RT3883_GPIO_GE2_RXCLK           83
 145 #define RT3883_GPIO_GE1_TXD0            84
 146 #define RT3883_GPIO_GE1_TXD1            85
 147 #define RT3883_GPIO_GE1_TXD2            86
 148 #define RT3883_GPIO_GE1_TXD3            87
 149 #define RT3883_GPIO_GE1_TXEN            88
 150 #define RT3883_GPIO_GE1_TXCLK           89
 151 #define RT3883_GPIO_GE1_RXD0            90
 152 #define RT3883_GPIO_GE1_RXD1            91
 153 #define RT3883_GPIO_GE1_RXD2            92
 154 #define RT3883_GPIO_GE1_RXD3            93
 155 #define RT3883_GPIO_GE1_RXDV            94
 156 #define RT3883_GPIO_GE1_RXCLK   95
 157
 158 #define RT3883_RSTCTRL_PCIE_PCI_PDM     BIT(27)
 159 #define RT3883_RSTCTRL_FLASH            BIT(26)
 160 #define RT3883_RSTCTRL_UDEV             BIT(25)
 161 #define RT3883_RSTCTRL_PCI              BIT(24)
 162 #define RT3883_RSTCTRL_PCIE             BIT(23)
 163 #define RT3883_RSTCTRL_UHST             BIT(22)
 164 #define RT3883_RSTCTRL_FE               BIT(21)
 165 #define RT3883_RSTCTRL_WLAN             BIT(20)
 166 #define RT3883_RSTCTRL_UART1            BIT(29)
 167 #define RT3883_RSTCTRL_SPI              BIT(18)
 168 #define RT3883_RSTCTRL_I2S              BIT(17)
 169 #define RT3883_RSTCTRL_I2C              BIT(16)
 170 #define RT3883_RSTCTRL_NAND             BIT(15)
 171 #define RT3883_RSTCTRL_DMA              BIT(14)
 172 #define RT3883_RSTCTRL_PIO              BIT(13)
 173 #define RT3883_RSTCTRL_UART             BIT(12)
 174 #define RT3883_RSTCTRL_PCM              BIT(11)
 175 #define RT3883_RSTCTRL_MC               BIT(10)
 176 #define RT3883_RSTCTRL_INTC             BIT(9)
 177 #define RT3883_RSTCTRL_TIMER            BIT(8)
 178 #define RT3883_RSTCTRL_SYS              BIT(0)
 179
 180 #define RT3883_INTC_INT_SYSCTL  BIT(0)
 181 #define RT3883_INTC_INT_TIMER0  BIT(1)
 182 #define RT3883_INTC_INT_TIMER1  BIT(2)
 183 #define RT3883_INTC_INT_IA      BIT(3)
 184 #define RT3883_INTC_INT_PCM     BIT(4)
 185 #define RT3883_INTC_INT_UART0   BIT(5)
 186 #define RT3883_INTC_INT_PIO     BIT(6)
 187 #define RT3883_INTC_INT_DMA     BIT(7)
 188 #define RT3883_INTC_INT_NAND    BIT(8)
 189 #define RT3883_INTC_INT_PERFC   BIT(9)
 190 #define RT3883_INTC_INT_I2S     BIT(10)
 191 #define RT3883_INTC_INT_UART1   BIT(12)
 192 #define RT3883_INTC_INT_UHST    BIT(18)
 193 #define RT3883_INTC_INT_UDEV    BIT(19)
 194
 195 /* FLASH/SRAM/Codec Controller registers */
 196 #define RT3883_FSCC_REG_FLASH_CFG0      0x00
 197 #define RT3883_FSCC_REG_FLASH_CFG1      0x04
 198 #define RT3883_FSCC_REG_CODEC_CFG0      0x40
 199 #define RT3883_FSCC_REG_CODEC_CFG1      0x44
 200
 201 #define RT3883_FLASH_CFG_WIDTH_SHIFT    26
 202 #define RT3883_FLASH_CFG_WIDTH_MASK     0x3
 203 #define RT3883_FLASH_CFG_WIDTH_8BIT     0x0
 204 #define RT3883_FLASH_CFG_WIDTH_16BIT    0x1
 205 #define RT3883_FLASH_CFG_WIDTH_32BIT    0x2
 206
 207 #define RT3883_SDRAM_BASE               0x00000000
 208 #define RT3883_MEM_SIZE_MIN             2
 209 #define RT3883_MEM_SIZE_MAX             256
 210
 211 #endif /* _RT3883_REGS_H_ */