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drm/rockchip: vop2: Fix the windows switch between different layers
[drm/drm-misc.git] / arch / mips / include / asm / octeon / cvmx-gmxx-defs.h
blobbdba676f1f2cdf0d5cae56fee2bc32b24a4829c7
1 /***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (C) 2003-2018 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28 #ifndef __CVMX_GMXX_DEFS_H__
29 #define __CVMX_GMXX_DEFS_H__
30
31 static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
32 {
33 switch (cvmx_get_octeon_family()) {
34 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
35 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull;
36 }
37 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
38 }
39
40 static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
41 {
42 switch (cvmx_get_octeon_family()) {
43 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
44 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull;
45 }
46 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
47 }
48
49 static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
50 {
51 switch (cvmx_get_octeon_family()) {
52 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
53 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048;
54 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
55 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
56 }
57 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
58 }
59
60 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
61 {
62 switch (cvmx_get_octeon_family()) {
63 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
64 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048;
65 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
66 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
67 }
68 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
69 }
70
71 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
72 {
73 switch (cvmx_get_octeon_family()) {
74 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
75 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048;
76 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
77 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
78 }
79 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
80 }
81
82 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
83 {
84 switch (cvmx_get_octeon_family()) {
85 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
86 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048;
87 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
88 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
89 }
90 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
91 }
92
93 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
94 {
95 switch (cvmx_get_octeon_family()) {
96 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
97 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048;
98 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
99 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
100 }
101 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
102 }
103
104 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
105 {
106 switch (cvmx_get_octeon_family()) {
107 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
108 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
109 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
110 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
111 }
112 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
113 }
114
115 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
116 {
117 switch (cvmx_get_octeon_family()) {
118 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
119 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
120 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
121 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
122 }
123 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
124 }
125
126 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
127 {
128 switch (cvmx_get_octeon_family()) {
129 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
130 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048;
131 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
132 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
133 }
134 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
135 }
136
137 static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
138 {
139 switch (cvmx_get_octeon_family()) {
140 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
141 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048;
142 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
143 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
144 }
145 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
146 }
147
148 static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
149 {
150 switch (cvmx_get_octeon_family()) {
151 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
152 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048;
153 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
154 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
155 }
156 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
157 }
158
159 #define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
160 #define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
161
162 static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
163 {
164 switch (cvmx_get_octeon_family()) {
165 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
166 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048;
167 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
168 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
169 }
170 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
171 }
172
173 static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
174 {
175 switch (cvmx_get_octeon_family()) {
176 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
177 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048;
178 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
179 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
180 }
181 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
182 }
183
184 static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
185 {
186 switch (cvmx_get_octeon_family()) {
187 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
188 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048;
189 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
190 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
191 }
192 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
193 }
194
195 #define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
196
197 static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
198 {
199 switch (cvmx_get_octeon_family()) {
200 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
201 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull;
202 }
203 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
204 }
205
206 static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
207 {
208 switch (cvmx_get_octeon_family()) {
209 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
210 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull;
211 }
212 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
213 }
214
215 static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
216 {
217 switch (cvmx_get_octeon_family()) {
218 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
219 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048;
220 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
221 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
222 }
223 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
224 }
225
226 static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
227 {
228 switch (cvmx_get_octeon_family()) {
229 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
230 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048;
231 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
232 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
233 }
234 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
235 }
236
237 #define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
238 static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
239 {
240 switch (cvmx_get_octeon_family()) {
241 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
242 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048;
243 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
244 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
245 }
246 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
247 }
248
249 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
250 {
251 switch (cvmx_get_octeon_family()) {
252 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
253 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048;
254 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
255 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
256 }
257 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
258 }
259
260 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
261 {
262 switch (cvmx_get_octeon_family()) {
263 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
264 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048;
265 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
266 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
267 }
268 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
269 }
270
271 static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
272 {
273 switch (cvmx_get_octeon_family()) {
274 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
275 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048;
276 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
277 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
278 }
279 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
280 }
281
282 static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
283 {
284 switch (cvmx_get_octeon_family()) {
285 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
286 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048;
287 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
288 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
289 }
290 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
291 }
292
293 static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
294 {
295 switch (cvmx_get_octeon_family()) {
296 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
297 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull;
298 }
299 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
300 }
301
302 static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
303 {
304 switch (cvmx_get_octeon_family()) {
305 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
306 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull;
307 }
308 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
309 }
310
311 static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
312 {
313 switch (cvmx_get_octeon_family()) {
314 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
315 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull;
316 }
317 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
318 }
319
320 static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
321 {
322 switch (cvmx_get_octeon_family()) {
323 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
324 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull;
325 }
326 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
327 }
328
329 #define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull)
330 #define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull)
331 #define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
332 static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
333 {
334 switch (cvmx_get_octeon_family()) {
335 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
336 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull;
337 }
338 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
339 }
340
341 void __cvmx_interrupt_gmxx_enable(int interface);
342
343 union cvmx_gmxx_hg2_control {
344 uint64_t u64;
345 struct cvmx_gmxx_hg2_control_s {
346 #ifdef __BIG_ENDIAN_BITFIELD
347 uint64_t reserved_19_63:45;
348 uint64_t hg2tx_en:1;
349 uint64_t hg2rx_en:1;
350 uint64_t phys_en:1;
351 uint64_t logl_en:16;
352 #else
353 uint64_t logl_en:16;
354 uint64_t phys_en:1;
355 uint64_t hg2rx_en:1;
356 uint64_t hg2tx_en:1;
357 uint64_t reserved_19_63:45;
358 #endif
359 } s;
360 };
361
362 union cvmx_gmxx_inf_mode {
363 uint64_t u64;
364 struct cvmx_gmxx_inf_mode_s {
365 #ifdef __BIG_ENDIAN_BITFIELD
366 uint64_t reserved_20_63:44;
367 uint64_t rate:4;
368 uint64_t reserved_12_15:4;
369 uint64_t speed:4;
370 uint64_t reserved_7_7:1;
371 uint64_t mode:3;
372 uint64_t reserved_3_3:1;
373 uint64_t p0mii:1;
374 uint64_t en:1;
375 uint64_t type:1;
376 #else
377 uint64_t type:1;
378 uint64_t en:1;
379 uint64_t p0mii:1;
380 uint64_t reserved_3_3:1;
381 uint64_t mode:3;
382 uint64_t reserved_7_7:1;
383 uint64_t speed:4;
384 uint64_t reserved_12_15:4;
385 uint64_t rate:4;
386 uint64_t reserved_20_63:44;
387 #endif
388 } s;
389 struct cvmx_gmxx_inf_mode_cn30xx {
390 #ifdef __BIG_ENDIAN_BITFIELD
391 uint64_t reserved_3_63:61;
392 uint64_t p0mii:1;
393 uint64_t en:1;
394 uint64_t type:1;
395 #else
396 uint64_t type:1;
397 uint64_t en:1;
398 uint64_t p0mii:1;
399 uint64_t reserved_3_63:61;
400 #endif
401 } cn30xx;
402 struct cvmx_gmxx_inf_mode_cn31xx {
403 #ifdef __BIG_ENDIAN_BITFIELD
404 uint64_t reserved_2_63:62;
405 uint64_t en:1;
406 uint64_t type:1;
407 #else
408 uint64_t type:1;
409 uint64_t en:1;
410 uint64_t reserved_2_63:62;
411 #endif
412 } cn31xx;
413 struct cvmx_gmxx_inf_mode_cn52xx {
414 #ifdef __BIG_ENDIAN_BITFIELD
415 uint64_t reserved_10_63:54;
416 uint64_t speed:2;
417 uint64_t reserved_6_7:2;
418 uint64_t mode:2;
419 uint64_t reserved_2_3:2;
420 uint64_t en:1;
421 uint64_t type:1;
422 #else
423 uint64_t type:1;
424 uint64_t en:1;
425 uint64_t reserved_2_3:2;
426 uint64_t mode:2;
427 uint64_t reserved_6_7:2;
428 uint64_t speed:2;
429 uint64_t reserved_10_63:54;
430 #endif
431 } cn52xx;
432 struct cvmx_gmxx_inf_mode_cn61xx {
433 #ifdef __BIG_ENDIAN_BITFIELD
434 uint64_t reserved_12_63:52;
435 uint64_t speed:4;
436 uint64_t reserved_5_7:3;
437 uint64_t mode:1;
438 uint64_t reserved_2_3:2;
439 uint64_t en:1;
440 uint64_t type:1;
441 #else
442 uint64_t type:1;
443 uint64_t en:1;
444 uint64_t reserved_2_3:2;
445 uint64_t mode:1;
446 uint64_t reserved_5_7:3;
447 uint64_t speed:4;
448 uint64_t reserved_12_63:52;
449 #endif
450 } cn61xx;
451 struct cvmx_gmxx_inf_mode_cn66xx {
452 #ifdef __BIG_ENDIAN_BITFIELD
453 uint64_t reserved_20_63:44;
454 uint64_t rate:4;
455 uint64_t reserved_12_15:4;
456 uint64_t speed:4;
457 uint64_t reserved_5_7:3;
458 uint64_t mode:1;
459 uint64_t reserved_2_3:2;
460 uint64_t en:1;
461 uint64_t type:1;
462 #else
463 uint64_t type:1;
464 uint64_t en:1;
465 uint64_t reserved_2_3:2;
466 uint64_t mode:1;
467 uint64_t reserved_5_7:3;
468 uint64_t speed:4;
469 uint64_t reserved_12_15:4;
470 uint64_t rate:4;
471 uint64_t reserved_20_63:44;
472 #endif
473 } cn66xx;
474 struct cvmx_gmxx_inf_mode_cn68xx {
475 #ifdef __BIG_ENDIAN_BITFIELD
476 uint64_t reserved_12_63:52;
477 uint64_t speed:4;
478 uint64_t reserved_7_7:1;
479 uint64_t mode:3;
480 uint64_t reserved_2_3:2;
481 uint64_t en:1;
482 uint64_t type:1;
483 #else
484 uint64_t type:1;
485 uint64_t en:1;
486 uint64_t reserved_2_3:2;
487 uint64_t mode:3;
488 uint64_t reserved_7_7:1;
489 uint64_t speed:4;
490 uint64_t reserved_12_63:52;
491 #endif
492 } cn68xx;
493 };
494
495 union cvmx_gmxx_prtx_cfg {
496 uint64_t u64;
497 struct cvmx_gmxx_prtx_cfg_s {
498 #ifdef __BIG_ENDIAN_BITFIELD
499 uint64_t reserved_22_63:42;
500 uint64_t pknd:6;
501 uint64_t reserved_14_15:2;
502 uint64_t tx_idle:1;
503 uint64_t rx_idle:1;
504 uint64_t reserved_9_11:3;
505 uint64_t speed_msb:1;
506 uint64_t reserved_4_7:4;
507 uint64_t slottime:1;
508 uint64_t duplex:1;
509 uint64_t speed:1;
510 uint64_t en:1;
511 #else
512 uint64_t en:1;
513 uint64_t speed:1;
514 uint64_t duplex:1;
515 uint64_t slottime:1;
516 uint64_t reserved_4_7:4;
517 uint64_t speed_msb:1;
518 uint64_t reserved_9_11:3;
519 uint64_t rx_idle:1;
520 uint64_t tx_idle:1;
521 uint64_t reserved_14_15:2;
522 uint64_t pknd:6;
523 uint64_t reserved_22_63:42;
524 #endif
525 } s;
526 struct cvmx_gmxx_prtx_cfg_cn30xx {
527 #ifdef __BIG_ENDIAN_BITFIELD
528 uint64_t reserved_4_63:60;
529 uint64_t slottime:1;
530 uint64_t duplex:1;
531 uint64_t speed:1;
532 uint64_t en:1;
533 #else
534 uint64_t en:1;
535 uint64_t speed:1;
536 uint64_t duplex:1;
537 uint64_t slottime:1;
538 uint64_t reserved_4_63:60;
539 #endif
540 } cn30xx;
541 struct cvmx_gmxx_prtx_cfg_cn52xx {
542 #ifdef __BIG_ENDIAN_BITFIELD
543 uint64_t reserved_14_63:50;
544 uint64_t tx_idle:1;
545 uint64_t rx_idle:1;
546 uint64_t reserved_9_11:3;
547 uint64_t speed_msb:1;
548 uint64_t reserved_4_7:4;
549 uint64_t slottime:1;
550 uint64_t duplex:1;
551 uint64_t speed:1;
552 uint64_t en:1;
553 #else
554 uint64_t en:1;
555 uint64_t speed:1;
556 uint64_t duplex:1;
557 uint64_t slottime:1;
558 uint64_t reserved_4_7:4;
559 uint64_t speed_msb:1;
560 uint64_t reserved_9_11:3;
561 uint64_t rx_idle:1;
562 uint64_t tx_idle:1;
563 uint64_t reserved_14_63:50;
564 #endif
565 } cn52xx;
566 };
567
568 union cvmx_gmxx_rxx_adr_ctl {
569 uint64_t u64;
570 struct cvmx_gmxx_rxx_adr_ctl_s {
571 #ifdef __BIG_ENDIAN_BITFIELD
572 uint64_t reserved_4_63:60;
573 uint64_t cam_mode:1;
574 uint64_t mcst:2;
575 uint64_t bcst:1;
576 #else
577 uint64_t bcst:1;
578 uint64_t mcst:2;
579 uint64_t cam_mode:1;
580 uint64_t reserved_4_63:60;
581 #endif
582 } s;
583 };
584
585 union cvmx_gmxx_rxx_frm_ctl {
586 uint64_t u64;
587 struct cvmx_gmxx_rxx_frm_ctl_s {
588 #ifdef __BIG_ENDIAN_BITFIELD
589 uint64_t reserved_13_63:51;
590 uint64_t ptp_mode:1;
591 uint64_t reserved_11_11:1;
592 uint64_t null_dis:1;
593 uint64_t pre_align:1;
594 uint64_t pad_len:1;
595 uint64_t vlan_len:1;
596 uint64_t pre_free:1;
597 uint64_t ctl_smac:1;
598 uint64_t ctl_mcst:1;
599 uint64_t ctl_bck:1;
600 uint64_t ctl_drp:1;
601 uint64_t pre_strp:1;
602 uint64_t pre_chk:1;
603 #else
604 uint64_t pre_chk:1;
605 uint64_t pre_strp:1;
606 uint64_t ctl_drp:1;
607 uint64_t ctl_bck:1;
608 uint64_t ctl_mcst:1;
609 uint64_t ctl_smac:1;
610 uint64_t pre_free:1;
611 uint64_t vlan_len:1;
612 uint64_t pad_len:1;
613 uint64_t pre_align:1;
614 uint64_t null_dis:1;
615 uint64_t reserved_11_11:1;
616 uint64_t ptp_mode:1;
617 uint64_t reserved_13_63:51;
618 #endif
619 } s;
620 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
621 #ifdef __BIG_ENDIAN_BITFIELD
622 uint64_t reserved_9_63:55;
623 uint64_t pad_len:1;
624 uint64_t vlan_len:1;
625 uint64_t pre_free:1;
626 uint64_t ctl_smac:1;
627 uint64_t ctl_mcst:1;
628 uint64_t ctl_bck:1;
629 uint64_t ctl_drp:1;
630 uint64_t pre_strp:1;
631 uint64_t pre_chk:1;
632 #else
633 uint64_t pre_chk:1;
634 uint64_t pre_strp:1;
635 uint64_t ctl_drp:1;
636 uint64_t ctl_bck:1;
637 uint64_t ctl_mcst:1;
638 uint64_t ctl_smac:1;
639 uint64_t pre_free:1;
640 uint64_t vlan_len:1;
641 uint64_t pad_len:1;
642 uint64_t reserved_9_63:55;
643 #endif
644 } cn30xx;
645 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
646 #ifdef __BIG_ENDIAN_BITFIELD
647 uint64_t reserved_8_63:56;
648 uint64_t vlan_len:1;
649 uint64_t pre_free:1;
650 uint64_t ctl_smac:1;
651 uint64_t ctl_mcst:1;
652 uint64_t ctl_bck:1;
653 uint64_t ctl_drp:1;
654 uint64_t pre_strp:1;
655 uint64_t pre_chk:1;
656 #else
657 uint64_t pre_chk:1;
658 uint64_t pre_strp:1;
659 uint64_t ctl_drp:1;
660 uint64_t ctl_bck:1;
661 uint64_t ctl_mcst:1;
662 uint64_t ctl_smac:1;
663 uint64_t pre_free:1;
664 uint64_t vlan_len:1;
665 uint64_t reserved_8_63:56;
666 #endif
667 } cn31xx;
668 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
669 #ifdef __BIG_ENDIAN_BITFIELD
670 uint64_t reserved_11_63:53;
671 uint64_t null_dis:1;
672 uint64_t pre_align:1;
673 uint64_t reserved_7_8:2;
674 uint64_t pre_free:1;
675 uint64_t ctl_smac:1;
676 uint64_t ctl_mcst:1;
677 uint64_t ctl_bck:1;
678 uint64_t ctl_drp:1;
679 uint64_t pre_strp:1;
680 uint64_t pre_chk:1;
681 #else
682 uint64_t pre_chk:1;
683 uint64_t pre_strp:1;
684 uint64_t ctl_drp:1;
685 uint64_t ctl_bck:1;
686 uint64_t ctl_mcst:1;
687 uint64_t ctl_smac:1;
688 uint64_t pre_free:1;
689 uint64_t reserved_7_8:2;
690 uint64_t pre_align:1;
691 uint64_t null_dis:1;
692 uint64_t reserved_11_63:53;
693 #endif
694 } cn50xx;
695 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
696 #ifdef __BIG_ENDIAN_BITFIELD
697 uint64_t reserved_10_63:54;
698 uint64_t pre_align:1;
699 uint64_t reserved_7_8:2;
700 uint64_t pre_free:1;
701 uint64_t ctl_smac:1;
702 uint64_t ctl_mcst:1;
703 uint64_t ctl_bck:1;
704 uint64_t ctl_drp:1;
705 uint64_t pre_strp:1;
706 uint64_t pre_chk:1;
707 #else
708 uint64_t pre_chk:1;
709 uint64_t pre_strp:1;
710 uint64_t ctl_drp:1;
711 uint64_t ctl_bck:1;
712 uint64_t ctl_mcst:1;
713 uint64_t ctl_smac:1;
714 uint64_t pre_free:1;
715 uint64_t reserved_7_8:2;
716 uint64_t pre_align:1;
717 uint64_t reserved_10_63:54;
718 #endif
719 } cn56xxp1;
720 struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
721 #ifdef __BIG_ENDIAN_BITFIELD
722 uint64_t reserved_11_63:53;
723 uint64_t null_dis:1;
724 uint64_t pre_align:1;
725 uint64_t pad_len:1;
726 uint64_t vlan_len:1;
727 uint64_t pre_free:1;
728 uint64_t ctl_smac:1;
729 uint64_t ctl_mcst:1;
730 uint64_t ctl_bck:1;
731 uint64_t ctl_drp:1;
732 uint64_t pre_strp:1;
733 uint64_t pre_chk:1;
734 #else
735 uint64_t pre_chk:1;
736 uint64_t pre_strp:1;
737 uint64_t ctl_drp:1;
738 uint64_t ctl_bck:1;
739 uint64_t ctl_mcst:1;
740 uint64_t ctl_smac:1;
741 uint64_t pre_free:1;
742 uint64_t vlan_len:1;
743 uint64_t pad_len:1;
744 uint64_t pre_align:1;
745 uint64_t null_dis:1;
746 uint64_t reserved_11_63:53;
747 #endif
748 } cn58xx;
749 struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
750 #ifdef __BIG_ENDIAN_BITFIELD
751 uint64_t reserved_13_63:51;
752 uint64_t ptp_mode:1;
753 uint64_t reserved_11_11:1;
754 uint64_t null_dis:1;
755 uint64_t pre_align:1;
756 uint64_t reserved_7_8:2;
757 uint64_t pre_free:1;
758 uint64_t ctl_smac:1;
759 uint64_t ctl_mcst:1;
760 uint64_t ctl_bck:1;
761 uint64_t ctl_drp:1;
762 uint64_t pre_strp:1;
763 uint64_t pre_chk:1;
764 #else
765 uint64_t pre_chk:1;
766 uint64_t pre_strp:1;
767 uint64_t ctl_drp:1;
768 uint64_t ctl_bck:1;
769 uint64_t ctl_mcst:1;
770 uint64_t ctl_smac:1;
771 uint64_t pre_free:1;
772 uint64_t reserved_7_8:2;
773 uint64_t pre_align:1;
774 uint64_t null_dis:1;
775 uint64_t reserved_11_11:1;
776 uint64_t ptp_mode:1;
777 uint64_t reserved_13_63:51;
778 #endif
779 } cn61xx;
780 };
781
782 union cvmx_gmxx_rxx_frm_max {
783 uint64_t u64;
784 struct cvmx_gmxx_rxx_frm_max_s {
785 #ifdef __BIG_ENDIAN_BITFIELD
786 uint64_t reserved_16_63:48;
787 uint64_t len:16;
788 #else
789 uint64_t len:16;
790 uint64_t reserved_16_63:48;
791 #endif
792 } s;
793 };
794
795 union cvmx_gmxx_rxx_frm_min {
796 uint64_t u64;
797 struct cvmx_gmxx_rxx_frm_min_s {
798 #ifdef __BIG_ENDIAN_BITFIELD
799 uint64_t reserved_16_63:48;
800 uint64_t len:16;
801 #else
802 uint64_t len:16;
803 uint64_t reserved_16_63:48;
804 #endif
805 } s;
806 };
807
808 union cvmx_gmxx_rxx_int_en {
809 uint64_t u64;
810 struct cvmx_gmxx_rxx_int_en_s {
811 #ifdef __BIG_ENDIAN_BITFIELD
812 uint64_t reserved_29_63:35;
813 uint64_t hg2cc:1;
814 uint64_t hg2fld:1;
815 uint64_t undat:1;
816 uint64_t uneop:1;
817 uint64_t unsop:1;
818 uint64_t bad_term:1;
819 uint64_t bad_seq:1;
820 uint64_t rem_fault:1;
821 uint64_t loc_fault:1;
822 uint64_t pause_drp:1;
823 uint64_t phy_dupx:1;
824 uint64_t phy_spd:1;
825 uint64_t phy_link:1;
826 uint64_t ifgerr:1;
827 uint64_t coldet:1;
828 uint64_t falerr:1;
829 uint64_t rsverr:1;
830 uint64_t pcterr:1;
831 uint64_t ovrerr:1;
832 uint64_t niberr:1;
833 uint64_t skperr:1;
834 uint64_t rcverr:1;
835 uint64_t lenerr:1;
836 uint64_t alnerr:1;
837 uint64_t fcserr:1;
838 uint64_t jabber:1;
839 uint64_t maxerr:1;
840 uint64_t carext:1;
841 uint64_t minerr:1;
842 #else
843 uint64_t minerr:1;
844 uint64_t carext:1;
845 uint64_t maxerr:1;
846 uint64_t jabber:1;
847 uint64_t fcserr:1;
848 uint64_t alnerr:1;
849 uint64_t lenerr:1;
850 uint64_t rcverr:1;
851 uint64_t skperr:1;
852 uint64_t niberr:1;
853 uint64_t ovrerr:1;
854 uint64_t pcterr:1;
855 uint64_t rsverr:1;
856 uint64_t falerr:1;
857 uint64_t coldet:1;
858 uint64_t ifgerr:1;
859 uint64_t phy_link:1;
860 uint64_t phy_spd:1;
861 uint64_t phy_dupx:1;
862 uint64_t pause_drp:1;
863 uint64_t loc_fault:1;
864 uint64_t rem_fault:1;
865 uint64_t bad_seq:1;
866 uint64_t bad_term:1;
867 uint64_t unsop:1;
868 uint64_t uneop:1;
869 uint64_t undat:1;
870 uint64_t hg2fld:1;
871 uint64_t hg2cc:1;
872 uint64_t reserved_29_63:35;
873 #endif
874 } s;
875 struct cvmx_gmxx_rxx_int_en_cn30xx {
876 #ifdef __BIG_ENDIAN_BITFIELD
877 uint64_t reserved_19_63:45;
878 uint64_t phy_dupx:1;
879 uint64_t phy_spd:1;
880 uint64_t phy_link:1;
881 uint64_t ifgerr:1;
882 uint64_t coldet:1;
883 uint64_t falerr:1;
884 uint64_t rsverr:1;
885 uint64_t pcterr:1;
886 uint64_t ovrerr:1;
887 uint64_t niberr:1;
888 uint64_t skperr:1;
889 uint64_t rcverr:1;
890 uint64_t lenerr:1;
891 uint64_t alnerr:1;
892 uint64_t fcserr:1;
893 uint64_t jabber:1;
894 uint64_t maxerr:1;
895 uint64_t carext:1;
896 uint64_t minerr:1;
897 #else
898 uint64_t minerr:1;
899 uint64_t carext:1;
900 uint64_t maxerr:1;
901 uint64_t jabber:1;
902 uint64_t fcserr:1;
903 uint64_t alnerr:1;
904 uint64_t lenerr:1;
905 uint64_t rcverr:1;
906 uint64_t skperr:1;
907 uint64_t niberr:1;
908 uint64_t ovrerr:1;
909 uint64_t pcterr:1;
910 uint64_t rsverr:1;
911 uint64_t falerr:1;
912 uint64_t coldet:1;
913 uint64_t ifgerr:1;
914 uint64_t phy_link:1;
915 uint64_t phy_spd:1;
916 uint64_t phy_dupx:1;
917 uint64_t reserved_19_63:45;
918 #endif
919 } cn30xx;
920 struct cvmx_gmxx_rxx_int_en_cn50xx {
921 #ifdef __BIG_ENDIAN_BITFIELD
922 uint64_t reserved_20_63:44;
923 uint64_t pause_drp:1;
924 uint64_t phy_dupx:1;
925 uint64_t phy_spd:1;
926 uint64_t phy_link:1;
927 uint64_t ifgerr:1;
928 uint64_t coldet:1;
929 uint64_t falerr:1;
930 uint64_t rsverr:1;
931 uint64_t pcterr:1;
932 uint64_t ovrerr:1;
933 uint64_t niberr:1;
934 uint64_t skperr:1;
935 uint64_t rcverr:1;
936 uint64_t reserved_6_6:1;
937 uint64_t alnerr:1;
938 uint64_t fcserr:1;
939 uint64_t jabber:1;
940 uint64_t reserved_2_2:1;
941 uint64_t carext:1;
942 uint64_t reserved_0_0:1;
943 #else
944 uint64_t reserved_0_0:1;
945 uint64_t carext:1;
946 uint64_t reserved_2_2:1;
947 uint64_t jabber:1;
948 uint64_t fcserr:1;
949 uint64_t alnerr:1;
950 uint64_t reserved_6_6:1;
951 uint64_t rcverr:1;
952 uint64_t skperr:1;
953 uint64_t niberr:1;
954 uint64_t ovrerr:1;
955 uint64_t pcterr:1;
956 uint64_t rsverr:1;
957 uint64_t falerr:1;
958 uint64_t coldet:1;
959 uint64_t ifgerr:1;
960 uint64_t phy_link:1;
961 uint64_t phy_spd:1;
962 uint64_t phy_dupx:1;
963 uint64_t pause_drp:1;
964 uint64_t reserved_20_63:44;
965 #endif
966 } cn50xx;
967 struct cvmx_gmxx_rxx_int_en_cn52xx {
968 #ifdef __BIG_ENDIAN_BITFIELD
969 uint64_t reserved_29_63:35;
970 uint64_t hg2cc:1;
971 uint64_t hg2fld:1;
972 uint64_t undat:1;
973 uint64_t uneop:1;
974 uint64_t unsop:1;
975 uint64_t bad_term:1;
976 uint64_t bad_seq:1;
977 uint64_t rem_fault:1;
978 uint64_t loc_fault:1;
979 uint64_t pause_drp:1;
980 uint64_t reserved_16_18:3;
981 uint64_t ifgerr:1;
982 uint64_t coldet:1;
983 uint64_t falerr:1;
984 uint64_t rsverr:1;
985 uint64_t pcterr:1;
986 uint64_t ovrerr:1;
987 uint64_t reserved_9_9:1;
988 uint64_t skperr:1;
989 uint64_t rcverr:1;
990 uint64_t reserved_5_6:2;
991 uint64_t fcserr:1;
992 uint64_t jabber:1;
993 uint64_t reserved_2_2:1;
994 uint64_t carext:1;
995 uint64_t reserved_0_0:1;
996 #else
997 uint64_t reserved_0_0:1;
998 uint64_t carext:1;
999 uint64_t reserved_2_2:1;
1000 uint64_t jabber:1;
1001 uint64_t fcserr:1;
1002 uint64_t reserved_5_6:2;
1003 uint64_t rcverr:1;
1004 uint64_t skperr:1;
1005 uint64_t reserved_9_9:1;
1006 uint64_t ovrerr:1;
1007 uint64_t pcterr:1;
1008 uint64_t rsverr:1;
1009 uint64_t falerr:1;
1010 uint64_t coldet:1;
1011 uint64_t ifgerr:1;
1012 uint64_t reserved_16_18:3;
1013 uint64_t pause_drp:1;
1014 uint64_t loc_fault:1;
1015 uint64_t rem_fault:1;
1016 uint64_t bad_seq:1;
1017 uint64_t bad_term:1;
1018 uint64_t unsop:1;
1019 uint64_t uneop:1;
1020 uint64_t undat:1;
1021 uint64_t hg2fld:1;
1022 uint64_t hg2cc:1;
1023 uint64_t reserved_29_63:35;
1024 #endif
1025 } cn52xx;
1026 struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
1027 #ifdef __BIG_ENDIAN_BITFIELD
1028 uint64_t reserved_27_63:37;
1029 uint64_t undat:1;
1030 uint64_t uneop:1;
1031 uint64_t unsop:1;
1032 uint64_t bad_term:1;
1033 uint64_t bad_seq:1;
1034 uint64_t rem_fault:1;
1035 uint64_t loc_fault:1;
1036 uint64_t pause_drp:1;
1037 uint64_t reserved_16_18:3;
1038 uint64_t ifgerr:1;
1039 uint64_t coldet:1;
1040 uint64_t falerr:1;
1041 uint64_t rsverr:1;
1042 uint64_t pcterr:1;
1043 uint64_t ovrerr:1;
1044 uint64_t reserved_9_9:1;
1045 uint64_t skperr:1;
1046 uint64_t rcverr:1;
1047 uint64_t reserved_5_6:2;
1048 uint64_t fcserr:1;
1049 uint64_t jabber:1;
1050 uint64_t reserved_2_2:1;
1051 uint64_t carext:1;
1052 uint64_t reserved_0_0:1;
1053 #else
1054 uint64_t reserved_0_0:1;
1055 uint64_t carext:1;
1056 uint64_t reserved_2_2:1;
1057 uint64_t jabber:1;
1058 uint64_t fcserr:1;
1059 uint64_t reserved_5_6:2;
1060 uint64_t rcverr:1;
1061 uint64_t skperr:1;
1062 uint64_t reserved_9_9:1;
1063 uint64_t ovrerr:1;
1064 uint64_t pcterr:1;
1065 uint64_t rsverr:1;
1066 uint64_t falerr:1;
1067 uint64_t coldet:1;
1068 uint64_t ifgerr:1;
1069 uint64_t reserved_16_18:3;
1070 uint64_t pause_drp:1;
1071 uint64_t loc_fault:1;
1072 uint64_t rem_fault:1;
1073 uint64_t bad_seq:1;
1074 uint64_t bad_term:1;
1075 uint64_t unsop:1;
1076 uint64_t uneop:1;
1077 uint64_t undat:1;
1078 uint64_t reserved_27_63:37;
1079 #endif
1080 } cn56xxp1;
1081 struct cvmx_gmxx_rxx_int_en_cn58xx {
1082 #ifdef __BIG_ENDIAN_BITFIELD
1083 uint64_t reserved_20_63:44;
1084 uint64_t pause_drp:1;
1085 uint64_t phy_dupx:1;
1086 uint64_t phy_spd:1;
1087 uint64_t phy_link:1;
1088 uint64_t ifgerr:1;
1089 uint64_t coldet:1;
1090 uint64_t falerr:1;
1091 uint64_t rsverr:1;
1092 uint64_t pcterr:1;
1093 uint64_t ovrerr:1;
1094 uint64_t niberr:1;
1095 uint64_t skperr:1;
1096 uint64_t rcverr:1;
1097 uint64_t lenerr:1;
1098 uint64_t alnerr:1;
1099 uint64_t fcserr:1;
1100 uint64_t jabber:1;
1101 uint64_t maxerr:1;
1102 uint64_t carext:1;
1103 uint64_t minerr:1;
1104 #else
1105 uint64_t minerr:1;
1106 uint64_t carext:1;
1107 uint64_t maxerr:1;
1108 uint64_t jabber:1;
1109 uint64_t fcserr:1;
1110 uint64_t alnerr:1;
1111 uint64_t lenerr:1;
1112 uint64_t rcverr:1;
1113 uint64_t skperr:1;
1114 uint64_t niberr:1;
1115 uint64_t ovrerr:1;
1116 uint64_t pcterr:1;
1117 uint64_t rsverr:1;
1118 uint64_t falerr:1;
1119 uint64_t coldet:1;
1120 uint64_t ifgerr:1;
1121 uint64_t phy_link:1;
1122 uint64_t phy_spd:1;
1123 uint64_t phy_dupx:1;
1124 uint64_t pause_drp:1;
1125 uint64_t reserved_20_63:44;
1126 #endif
1127 } cn58xx;
1128 struct cvmx_gmxx_rxx_int_en_cn61xx {
1129 #ifdef __BIG_ENDIAN_BITFIELD
1130 uint64_t reserved_29_63:35;
1131 uint64_t hg2cc:1;
1132 uint64_t hg2fld:1;
1133 uint64_t undat:1;
1134 uint64_t uneop:1;
1135 uint64_t unsop:1;
1136 uint64_t bad_term:1;
1137 uint64_t bad_seq:1;
1138 uint64_t rem_fault:1;
1139 uint64_t loc_fault:1;
1140 uint64_t pause_drp:1;
1141 uint64_t reserved_16_18:3;
1142 uint64_t ifgerr:1;
1143 uint64_t coldet:1;
1144 uint64_t falerr:1;
1145 uint64_t rsverr:1;
1146 uint64_t pcterr:1;
1147 uint64_t ovrerr:1;
1148 uint64_t reserved_9_9:1;
1149 uint64_t skperr:1;
1150 uint64_t rcverr:1;
1151 uint64_t reserved_5_6:2;
1152 uint64_t fcserr:1;
1153 uint64_t jabber:1;
1154 uint64_t reserved_2_2:1;
1155 uint64_t carext:1;
1156 uint64_t minerr:1;
1157 #else
1158 uint64_t minerr:1;
1159 uint64_t carext:1;
1160 uint64_t reserved_2_2:1;
1161 uint64_t jabber:1;
1162 uint64_t fcserr:1;
1163 uint64_t reserved_5_6:2;
1164 uint64_t rcverr:1;
1165 uint64_t skperr:1;
1166 uint64_t reserved_9_9:1;
1167 uint64_t ovrerr:1;
1168 uint64_t pcterr:1;
1169 uint64_t rsverr:1;
1170 uint64_t falerr:1;
1171 uint64_t coldet:1;
1172 uint64_t ifgerr:1;
1173 uint64_t reserved_16_18:3;
1174 uint64_t pause_drp:1;
1175 uint64_t loc_fault:1;
1176 uint64_t rem_fault:1;
1177 uint64_t bad_seq:1;
1178 uint64_t bad_term:1;
1179 uint64_t unsop:1;
1180 uint64_t uneop:1;
1181 uint64_t undat:1;
1182 uint64_t hg2fld:1;
1183 uint64_t hg2cc:1;
1184 uint64_t reserved_29_63:35;
1185 #endif
1186 } cn61xx;
1187 };
1188
1189 union cvmx_gmxx_rxx_int_reg {
1190 uint64_t u64;
1191 struct cvmx_gmxx_rxx_int_reg_s {
1192 #ifdef __BIG_ENDIAN_BITFIELD
1193 uint64_t reserved_29_63:35;
1194 uint64_t hg2cc:1;
1195 uint64_t hg2fld:1;
1196 uint64_t undat:1;
1197 uint64_t uneop:1;
1198 uint64_t unsop:1;
1199 uint64_t bad_term:1;
1200 uint64_t bad_seq:1;
1201 uint64_t rem_fault:1;
1202 uint64_t loc_fault:1;
1203 uint64_t pause_drp:1;
1204 uint64_t phy_dupx:1;
1205 uint64_t phy_spd:1;
1206 uint64_t phy_link:1;
1207 uint64_t ifgerr:1;
1208 uint64_t coldet:1;
1209 uint64_t falerr:1;
1210 uint64_t rsverr:1;
1211 uint64_t pcterr:1;
1212 uint64_t ovrerr:1;
1213 uint64_t niberr:1;
1214 uint64_t skperr:1;
1215 uint64_t rcverr:1;
1216 uint64_t lenerr:1;
1217 uint64_t alnerr:1;
1218 uint64_t fcserr:1;
1219 uint64_t jabber:1;
1220 uint64_t maxerr:1;
1221 uint64_t carext:1;
1222 uint64_t minerr:1;
1223 #else
1224 uint64_t minerr:1;
1225 uint64_t carext:1;
1226 uint64_t maxerr:1;
1227 uint64_t jabber:1;
1228 uint64_t fcserr:1;
1229 uint64_t alnerr:1;
1230 uint64_t lenerr:1;
1231 uint64_t rcverr:1;
1232 uint64_t skperr:1;
1233 uint64_t niberr:1;
1234 uint64_t ovrerr:1;
1235 uint64_t pcterr:1;
1236 uint64_t rsverr:1;
1237 uint64_t falerr:1;
1238 uint64_t coldet:1;
1239 uint64_t ifgerr:1;
1240 uint64_t phy_link:1;
1241 uint64_t phy_spd:1;
1242 uint64_t phy_dupx:1;
1243 uint64_t pause_drp:1;
1244 uint64_t loc_fault:1;
1245 uint64_t rem_fault:1;
1246 uint64_t bad_seq:1;
1247 uint64_t bad_term:1;
1248 uint64_t unsop:1;
1249 uint64_t uneop:1;
1250 uint64_t undat:1;
1251 uint64_t hg2fld:1;
1252 uint64_t hg2cc:1;
1253 uint64_t reserved_29_63:35;
1254 #endif
1255 } s;
1256 struct cvmx_gmxx_rxx_int_reg_cn30xx {
1257 #ifdef __BIG_ENDIAN_BITFIELD
1258 uint64_t reserved_19_63:45;
1259 uint64_t phy_dupx:1;
1260 uint64_t phy_spd:1;
1261 uint64_t phy_link:1;
1262 uint64_t ifgerr:1;
1263 uint64_t coldet:1;
1264 uint64_t falerr:1;
1265 uint64_t rsverr:1;
1266 uint64_t pcterr:1;
1267 uint64_t ovrerr:1;
1268 uint64_t niberr:1;
1269 uint64_t skperr:1;
1270 uint64_t rcverr:1;
1271 uint64_t lenerr:1;
1272 uint64_t alnerr:1;
1273 uint64_t fcserr:1;
1274 uint64_t jabber:1;
1275 uint64_t maxerr:1;
1276 uint64_t carext:1;
1277 uint64_t minerr:1;
1278 #else
1279 uint64_t minerr:1;
1280 uint64_t carext:1;
1281 uint64_t maxerr:1;
1282 uint64_t jabber:1;
1283 uint64_t fcserr:1;
1284 uint64_t alnerr:1;
1285 uint64_t lenerr:1;
1286 uint64_t rcverr:1;
1287 uint64_t skperr:1;
1288 uint64_t niberr:1;
1289 uint64_t ovrerr:1;
1290 uint64_t pcterr:1;
1291 uint64_t rsverr:1;
1292 uint64_t falerr:1;
1293 uint64_t coldet:1;
1294 uint64_t ifgerr:1;
1295 uint64_t phy_link:1;
1296 uint64_t phy_spd:1;
1297 uint64_t phy_dupx:1;
1298 uint64_t reserved_19_63:45;
1299 #endif
1300 } cn30xx;
1301 struct cvmx_gmxx_rxx_int_reg_cn50xx {
1302 #ifdef __BIG_ENDIAN_BITFIELD
1303 uint64_t reserved_20_63:44;
1304 uint64_t pause_drp:1;
1305 uint64_t phy_dupx:1;
1306 uint64_t phy_spd:1;
1307 uint64_t phy_link:1;
1308 uint64_t ifgerr:1;
1309 uint64_t coldet:1;
1310 uint64_t falerr:1;
1311 uint64_t rsverr:1;
1312 uint64_t pcterr:1;
1313 uint64_t ovrerr:1;
1314 uint64_t niberr:1;
1315 uint64_t skperr:1;
1316 uint64_t rcverr:1;
1317 uint64_t reserved_6_6:1;
1318 uint64_t alnerr:1;
1319 uint64_t fcserr:1;
1320 uint64_t jabber:1;
1321 uint64_t reserved_2_2:1;
1322 uint64_t carext:1;
1323 uint64_t reserved_0_0:1;
1324 #else
1325 uint64_t reserved_0_0:1;
1326 uint64_t carext:1;
1327 uint64_t reserved_2_2:1;
1328 uint64_t jabber:1;
1329 uint64_t fcserr:1;
1330 uint64_t alnerr:1;
1331 uint64_t reserved_6_6:1;
1332 uint64_t rcverr:1;
1333 uint64_t skperr:1;
1334 uint64_t niberr:1;
1335 uint64_t ovrerr:1;
1336 uint64_t pcterr:1;
1337 uint64_t rsverr:1;
1338 uint64_t falerr:1;
1339 uint64_t coldet:1;
1340 uint64_t ifgerr:1;
1341 uint64_t phy_link:1;
1342 uint64_t phy_spd:1;
1343 uint64_t phy_dupx:1;
1344 uint64_t pause_drp:1;
1345 uint64_t reserved_20_63:44;
1346 #endif
1347 } cn50xx;
1348 struct cvmx_gmxx_rxx_int_reg_cn52xx {
1349 #ifdef __BIG_ENDIAN_BITFIELD
1350 uint64_t reserved_29_63:35;
1351 uint64_t hg2cc:1;
1352 uint64_t hg2fld:1;
1353 uint64_t undat:1;
1354 uint64_t uneop:1;
1355 uint64_t unsop:1;
1356 uint64_t bad_term:1;
1357 uint64_t bad_seq:1;
1358 uint64_t rem_fault:1;
1359 uint64_t loc_fault:1;
1360 uint64_t pause_drp:1;
1361 uint64_t reserved_16_18:3;
1362 uint64_t ifgerr:1;
1363 uint64_t coldet:1;
1364 uint64_t falerr:1;
1365 uint64_t rsverr:1;
1366 uint64_t pcterr:1;
1367 uint64_t ovrerr:1;
1368 uint64_t reserved_9_9:1;
1369 uint64_t skperr:1;
1370 uint64_t rcverr:1;
1371 uint64_t reserved_5_6:2;
1372 uint64_t fcserr:1;
1373 uint64_t jabber:1;
1374 uint64_t reserved_2_2:1;
1375 uint64_t carext:1;
1376 uint64_t reserved_0_0:1;
1377 #else
1378 uint64_t reserved_0_0:1;
1379 uint64_t carext:1;
1380 uint64_t reserved_2_2:1;
1381 uint64_t jabber:1;
1382 uint64_t fcserr:1;
1383 uint64_t reserved_5_6:2;
1384 uint64_t rcverr:1;
1385 uint64_t skperr:1;
1386 uint64_t reserved_9_9:1;
1387 uint64_t ovrerr:1;
1388 uint64_t pcterr:1;
1389 uint64_t rsverr:1;
1390 uint64_t falerr:1;
1391 uint64_t coldet:1;
1392 uint64_t ifgerr:1;
1393 uint64_t reserved_16_18:3;
1394 uint64_t pause_drp:1;
1395 uint64_t loc_fault:1;
1396 uint64_t rem_fault:1;
1397 uint64_t bad_seq:1;
1398 uint64_t bad_term:1;
1399 uint64_t unsop:1;
1400 uint64_t uneop:1;
1401 uint64_t undat:1;
1402 uint64_t hg2fld:1;
1403 uint64_t hg2cc:1;
1404 uint64_t reserved_29_63:35;
1405 #endif
1406 } cn52xx;
1407 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
1408 #ifdef __BIG_ENDIAN_BITFIELD
1409 uint64_t reserved_27_63:37;
1410 uint64_t undat:1;
1411 uint64_t uneop:1;
1412 uint64_t unsop:1;
1413 uint64_t bad_term:1;
1414 uint64_t bad_seq:1;
1415 uint64_t rem_fault:1;
1416 uint64_t loc_fault:1;
1417 uint64_t pause_drp:1;
1418 uint64_t reserved_16_18:3;
1419 uint64_t ifgerr:1;
1420 uint64_t coldet:1;
1421 uint64_t falerr:1;
1422 uint64_t rsverr:1;
1423 uint64_t pcterr:1;
1424 uint64_t ovrerr:1;
1425 uint64_t reserved_9_9:1;
1426 uint64_t skperr:1;
1427 uint64_t rcverr:1;
1428 uint64_t reserved_5_6:2;
1429 uint64_t fcserr:1;
1430 uint64_t jabber:1;
1431 uint64_t reserved_2_2:1;
1432 uint64_t carext:1;
1433 uint64_t reserved_0_0:1;
1434 #else
1435 uint64_t reserved_0_0:1;
1436 uint64_t carext:1;
1437 uint64_t reserved_2_2:1;
1438 uint64_t jabber:1;
1439 uint64_t fcserr:1;
1440 uint64_t reserved_5_6:2;
1441 uint64_t rcverr:1;
1442 uint64_t skperr:1;
1443 uint64_t reserved_9_9:1;
1444 uint64_t ovrerr:1;
1445 uint64_t pcterr:1;
1446 uint64_t rsverr:1;
1447 uint64_t falerr:1;
1448 uint64_t coldet:1;
1449 uint64_t ifgerr:1;
1450 uint64_t reserved_16_18:3;
1451 uint64_t pause_drp:1;
1452 uint64_t loc_fault:1;
1453 uint64_t rem_fault:1;
1454 uint64_t bad_seq:1;
1455 uint64_t bad_term:1;
1456 uint64_t unsop:1;
1457 uint64_t uneop:1;
1458 uint64_t undat:1;
1459 uint64_t reserved_27_63:37;
1460 #endif
1461 } cn56xxp1;
1462 struct cvmx_gmxx_rxx_int_reg_cn58xx {
1463 #ifdef __BIG_ENDIAN_BITFIELD
1464 uint64_t reserved_20_63:44;
1465 uint64_t pause_drp:1;
1466 uint64_t phy_dupx:1;
1467 uint64_t phy_spd:1;
1468 uint64_t phy_link:1;
1469 uint64_t ifgerr:1;
1470 uint64_t coldet:1;
1471 uint64_t falerr:1;
1472 uint64_t rsverr:1;
1473 uint64_t pcterr:1;
1474 uint64_t ovrerr:1;
1475 uint64_t niberr:1;
1476 uint64_t skperr:1;
1477 uint64_t rcverr:1;
1478 uint64_t lenerr:1;
1479 uint64_t alnerr:1;
1480 uint64_t fcserr:1;
1481 uint64_t jabber:1;
1482 uint64_t maxerr:1;
1483 uint64_t carext:1;
1484 uint64_t minerr:1;
1485 #else
1486 uint64_t minerr:1;
1487 uint64_t carext:1;
1488 uint64_t maxerr:1;
1489 uint64_t jabber:1;
1490 uint64_t fcserr:1;
1491 uint64_t alnerr:1;
1492 uint64_t lenerr:1;
1493 uint64_t rcverr:1;
1494 uint64_t skperr:1;
1495 uint64_t niberr:1;
1496 uint64_t ovrerr:1;
1497 uint64_t pcterr:1;
1498 uint64_t rsverr:1;
1499 uint64_t falerr:1;
1500 uint64_t coldet:1;
1501 uint64_t ifgerr:1;
1502 uint64_t phy_link:1;
1503 uint64_t phy_spd:1;
1504 uint64_t phy_dupx:1;
1505 uint64_t pause_drp:1;
1506 uint64_t reserved_20_63:44;
1507 #endif
1508 } cn58xx;
1509 struct cvmx_gmxx_rxx_int_reg_cn61xx {
1510 #ifdef __BIG_ENDIAN_BITFIELD
1511 uint64_t reserved_29_63:35;
1512 uint64_t hg2cc:1;
1513 uint64_t hg2fld:1;
1514 uint64_t undat:1;
1515 uint64_t uneop:1;
1516 uint64_t unsop:1;
1517 uint64_t bad_term:1;
1518 uint64_t bad_seq:1;
1519 uint64_t rem_fault:1;
1520 uint64_t loc_fault:1;
1521 uint64_t pause_drp:1;
1522 uint64_t reserved_16_18:3;
1523 uint64_t ifgerr:1;
1524 uint64_t coldet:1;
1525 uint64_t falerr:1;
1526 uint64_t rsverr:1;
1527 uint64_t pcterr:1;
1528 uint64_t ovrerr:1;
1529 uint64_t reserved_9_9:1;
1530 uint64_t skperr:1;
1531 uint64_t rcverr:1;
1532 uint64_t reserved_5_6:2;
1533 uint64_t fcserr:1;
1534 uint64_t jabber:1;
1535 uint64_t reserved_2_2:1;
1536 uint64_t carext:1;
1537 uint64_t minerr:1;
1538 #else
1539 uint64_t minerr:1;
1540 uint64_t carext:1;
1541 uint64_t reserved_2_2:1;
1542 uint64_t jabber:1;
1543 uint64_t fcserr:1;
1544 uint64_t reserved_5_6:2;
1545 uint64_t rcverr:1;
1546 uint64_t skperr:1;
1547 uint64_t reserved_9_9:1;
1548 uint64_t ovrerr:1;
1549 uint64_t pcterr:1;
1550 uint64_t rsverr:1;
1551 uint64_t falerr:1;
1552 uint64_t coldet:1;
1553 uint64_t ifgerr:1;
1554 uint64_t reserved_16_18:3;
1555 uint64_t pause_drp:1;
1556 uint64_t loc_fault:1;
1557 uint64_t rem_fault:1;
1558 uint64_t bad_seq:1;
1559 uint64_t bad_term:1;
1560 uint64_t unsop:1;
1561 uint64_t uneop:1;
1562 uint64_t undat:1;
1563 uint64_t hg2fld:1;
1564 uint64_t hg2cc:1;
1565 uint64_t reserved_29_63:35;
1566 #endif
1567 } cn61xx;
1568 };
1569
1570 union cvmx_gmxx_rxx_jabber {
1571 uint64_t u64;
1572 struct cvmx_gmxx_rxx_jabber_s {
1573 #ifdef __BIG_ENDIAN_BITFIELD
1574 uint64_t reserved_16_63:48;
1575 uint64_t cnt:16;
1576 #else
1577 uint64_t cnt:16;
1578 uint64_t reserved_16_63:48;
1579 #endif
1580 } s;
1581 };
1582
1583 union cvmx_gmxx_rxx_rx_inbnd {
1584 uint64_t u64;
1585 struct cvmx_gmxx_rxx_rx_inbnd_s {
1586 #ifdef __BIG_ENDIAN_BITFIELD
1587 uint64_t reserved_4_63:60;
1588 uint64_t duplex:1;
1589 uint64_t speed:2;
1590 uint64_t status:1;
1591 #else
1592 uint64_t status:1;
1593 uint64_t speed:2;
1594 uint64_t duplex:1;
1595 uint64_t reserved_4_63:60;
1596 #endif
1597 } s;
1598 };
1599
1600 union cvmx_gmxx_rx_prts {
1601 uint64_t u64;
1602 struct cvmx_gmxx_rx_prts_s {
1603 #ifdef __BIG_ENDIAN_BITFIELD
1604 uint64_t reserved_3_63:61;
1605 uint64_t prts:3;
1606 #else
1607 uint64_t prts:3;
1608 uint64_t reserved_3_63:61;
1609 #endif
1610 } s;
1611 };
1612
1613 union cvmx_gmxx_rx_xaui_ctl {
1614 uint64_t u64;
1615 struct cvmx_gmxx_rx_xaui_ctl_s {
1616 #ifdef __BIG_ENDIAN_BITFIELD
1617 uint64_t reserved_2_63:62;
1618 uint64_t status:2;
1619 #else
1620 uint64_t status:2;
1621 uint64_t reserved_2_63:62;
1622 #endif
1623 } s;
1624 };
1625
1626 union cvmx_gmxx_txx_thresh {
1627 uint64_t u64;
1628 struct cvmx_gmxx_txx_thresh_s {
1629 #ifdef __BIG_ENDIAN_BITFIELD
1630 uint64_t reserved_10_63:54;
1631 uint64_t cnt:10;
1632 #else
1633 uint64_t cnt:10;
1634 uint64_t reserved_10_63:54;
1635 #endif
1636 } s;
1637 struct cvmx_gmxx_txx_thresh_cn30xx {
1638 #ifdef __BIG_ENDIAN_BITFIELD
1639 uint64_t reserved_7_63:57;
1640 uint64_t cnt:7;
1641 #else
1642 uint64_t cnt:7;
1643 uint64_t reserved_7_63:57;
1644 #endif
1645 } cn30xx;
1646 struct cvmx_gmxx_txx_thresh_cn38xx {
1647 #ifdef __BIG_ENDIAN_BITFIELD
1648 uint64_t reserved_9_63:55;
1649 uint64_t cnt:9;
1650 #else
1651 uint64_t cnt:9;
1652 uint64_t reserved_9_63:55;
1653 #endif
1654 } cn38xx;
1655 };
1656
1657 union cvmx_gmxx_tx_int_en {
1658 uint64_t u64;
1659 struct cvmx_gmxx_tx_int_en_s {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661 uint64_t reserved_25_63:39;
1662 uint64_t xchange:1;
1663 uint64_t ptp_lost:4;
1664 uint64_t late_col:4;
1665 uint64_t xsdef:4;
1666 uint64_t xscol:4;
1667 uint64_t reserved_6_7:2;
1668 uint64_t undflw:4;
1669 uint64_t reserved_1_1:1;
1670 uint64_t pko_nxa:1;
1671 #else
1672 uint64_t pko_nxa:1;
1673 uint64_t reserved_1_1:1;
1674 uint64_t undflw:4;
1675 uint64_t reserved_6_7:2;
1676 uint64_t xscol:4;
1677 uint64_t xsdef:4;
1678 uint64_t late_col:4;
1679 uint64_t ptp_lost:4;
1680 uint64_t xchange:1;
1681 uint64_t reserved_25_63:39;
1682 #endif
1683 } s;
1684 struct cvmx_gmxx_tx_int_en_cn30xx {
1685 #ifdef __BIG_ENDIAN_BITFIELD
1686 uint64_t reserved_19_63:45;
1687 uint64_t late_col:3;
1688 uint64_t reserved_15_15:1;
1689 uint64_t xsdef:3;
1690 uint64_t reserved_11_11:1;
1691 uint64_t xscol:3;
1692 uint64_t reserved_5_7:3;
1693 uint64_t undflw:3;
1694 uint64_t reserved_1_1:1;
1695 uint64_t pko_nxa:1;
1696 #else
1697 uint64_t pko_nxa:1;
1698 uint64_t reserved_1_1:1;
1699 uint64_t undflw:3;
1700 uint64_t reserved_5_7:3;
1701 uint64_t xscol:3;
1702 uint64_t reserved_11_11:1;
1703 uint64_t xsdef:3;
1704 uint64_t reserved_15_15:1;
1705 uint64_t late_col:3;
1706 uint64_t reserved_19_63:45;
1707 #endif
1708 } cn30xx;
1709 struct cvmx_gmxx_tx_int_en_cn31xx {
1710 #ifdef __BIG_ENDIAN_BITFIELD
1711 uint64_t reserved_15_63:49;
1712 uint64_t xsdef:3;
1713 uint64_t reserved_11_11:1;
1714 uint64_t xscol:3;
1715 uint64_t reserved_5_7:3;
1716 uint64_t undflw:3;
1717 uint64_t reserved_1_1:1;
1718 uint64_t pko_nxa:1;
1719 #else
1720 uint64_t pko_nxa:1;
1721 uint64_t reserved_1_1:1;
1722 uint64_t undflw:3;
1723 uint64_t reserved_5_7:3;
1724 uint64_t xscol:3;
1725 uint64_t reserved_11_11:1;
1726 uint64_t xsdef:3;
1727 uint64_t reserved_15_63:49;
1728 #endif
1729 } cn31xx;
1730 struct cvmx_gmxx_tx_int_en_cn38xx {
1731 #ifdef __BIG_ENDIAN_BITFIELD
1732 uint64_t reserved_20_63:44;
1733 uint64_t late_col:4;
1734 uint64_t xsdef:4;
1735 uint64_t xscol:4;
1736 uint64_t reserved_6_7:2;
1737 uint64_t undflw:4;
1738 uint64_t ncb_nxa:1;
1739 uint64_t pko_nxa:1;
1740 #else
1741 uint64_t pko_nxa:1;
1742 uint64_t ncb_nxa:1;
1743 uint64_t undflw:4;
1744 uint64_t reserved_6_7:2;
1745 uint64_t xscol:4;
1746 uint64_t xsdef:4;
1747 uint64_t late_col:4;
1748 uint64_t reserved_20_63:44;
1749 #endif
1750 } cn38xx;
1751 struct cvmx_gmxx_tx_int_en_cn38xxp2 {
1752 #ifdef __BIG_ENDIAN_BITFIELD
1753 uint64_t reserved_16_63:48;
1754 uint64_t xsdef:4;
1755 uint64_t xscol:4;
1756 uint64_t reserved_6_7:2;
1757 uint64_t undflw:4;
1758 uint64_t ncb_nxa:1;
1759 uint64_t pko_nxa:1;
1760 #else
1761 uint64_t pko_nxa:1;
1762 uint64_t ncb_nxa:1;
1763 uint64_t undflw:4;
1764 uint64_t reserved_6_7:2;
1765 uint64_t xscol:4;
1766 uint64_t xsdef:4;
1767 uint64_t reserved_16_63:48;
1768 #endif
1769 } cn38xxp2;
1770 struct cvmx_gmxx_tx_int_en_cn52xx {
1771 #ifdef __BIG_ENDIAN_BITFIELD
1772 uint64_t reserved_20_63:44;
1773 uint64_t late_col:4;
1774 uint64_t xsdef:4;
1775 uint64_t xscol:4;
1776 uint64_t reserved_6_7:2;
1777 uint64_t undflw:4;
1778 uint64_t reserved_1_1:1;
1779 uint64_t pko_nxa:1;
1780 #else
1781 uint64_t pko_nxa:1;
1782 uint64_t reserved_1_1:1;
1783 uint64_t undflw:4;
1784 uint64_t reserved_6_7:2;
1785 uint64_t xscol:4;
1786 uint64_t xsdef:4;
1787 uint64_t late_col:4;
1788 uint64_t reserved_20_63:44;
1789 #endif
1790 } cn52xx;
1791 struct cvmx_gmxx_tx_int_en_cn63xx {
1792 #ifdef __BIG_ENDIAN_BITFIELD
1793 uint64_t reserved_24_63:40;
1794 uint64_t ptp_lost:4;
1795 uint64_t late_col:4;
1796 uint64_t xsdef:4;
1797 uint64_t xscol:4;
1798 uint64_t reserved_6_7:2;
1799 uint64_t undflw:4;
1800 uint64_t reserved_1_1:1;
1801 uint64_t pko_nxa:1;
1802 #else
1803 uint64_t pko_nxa:1;
1804 uint64_t reserved_1_1:1;
1805 uint64_t undflw:4;
1806 uint64_t reserved_6_7:2;
1807 uint64_t xscol:4;
1808 uint64_t xsdef:4;
1809 uint64_t late_col:4;
1810 uint64_t ptp_lost:4;
1811 uint64_t reserved_24_63:40;
1812 #endif
1813 } cn63xx;
1814 struct cvmx_gmxx_tx_int_en_cn68xx {
1815 #ifdef __BIG_ENDIAN_BITFIELD
1816 uint64_t reserved_25_63:39;
1817 uint64_t xchange:1;
1818 uint64_t ptp_lost:4;
1819 uint64_t late_col:4;
1820 uint64_t xsdef:4;
1821 uint64_t xscol:4;
1822 uint64_t reserved_6_7:2;
1823 uint64_t undflw:4;
1824 uint64_t pko_nxp:1;
1825 uint64_t pko_nxa:1;
1826 #else
1827 uint64_t pko_nxa:1;
1828 uint64_t pko_nxp:1;
1829 uint64_t undflw:4;
1830 uint64_t reserved_6_7:2;
1831 uint64_t xscol:4;
1832 uint64_t xsdef:4;
1833 uint64_t late_col:4;
1834 uint64_t ptp_lost:4;
1835 uint64_t xchange:1;
1836 uint64_t reserved_25_63:39;
1837 #endif
1838 } cn68xx;
1839 struct cvmx_gmxx_tx_int_en_cnf71xx {
1840 #ifdef __BIG_ENDIAN_BITFIELD
1841 uint64_t reserved_25_63:39;
1842 uint64_t xchange:1;
1843 uint64_t reserved_22_23:2;
1844 uint64_t ptp_lost:2;
1845 uint64_t reserved_18_19:2;
1846 uint64_t late_col:2;
1847 uint64_t reserved_14_15:2;
1848 uint64_t xsdef:2;
1849 uint64_t reserved_10_11:2;
1850 uint64_t xscol:2;
1851 uint64_t reserved_4_7:4;
1852 uint64_t undflw:2;
1853 uint64_t reserved_1_1:1;
1854 uint64_t pko_nxa:1;
1855 #else
1856 uint64_t pko_nxa:1;
1857 uint64_t reserved_1_1:1;
1858 uint64_t undflw:2;
1859 uint64_t reserved_4_7:4;
1860 uint64_t xscol:2;
1861 uint64_t reserved_10_11:2;
1862 uint64_t xsdef:2;
1863 uint64_t reserved_14_15:2;
1864 uint64_t late_col:2;
1865 uint64_t reserved_18_19:2;
1866 uint64_t ptp_lost:2;
1867 uint64_t reserved_22_23:2;
1868 uint64_t xchange:1;
1869 uint64_t reserved_25_63:39;
1870 #endif
1871 } cnf71xx;
1872 };
1873
1874 union cvmx_gmxx_tx_int_reg {
1875 uint64_t u64;
1876 struct cvmx_gmxx_tx_int_reg_s {
1877 #ifdef __BIG_ENDIAN_BITFIELD
1878 uint64_t reserved_25_63:39;
1879 uint64_t xchange:1;
1880 uint64_t ptp_lost:4;
1881 uint64_t late_col:4;
1882 uint64_t xsdef:4;
1883 uint64_t xscol:4;
1884 uint64_t reserved_6_7:2;
1885 uint64_t undflw:4;
1886 uint64_t reserved_1_1:1;
1887 uint64_t pko_nxa:1;
1888 #else
1889 uint64_t pko_nxa:1;
1890 uint64_t reserved_1_1:1;
1891 uint64_t undflw:4;
1892 uint64_t reserved_6_7:2;
1893 uint64_t xscol:4;
1894 uint64_t xsdef:4;
1895 uint64_t late_col:4;
1896 uint64_t ptp_lost:4;
1897 uint64_t xchange:1;
1898 uint64_t reserved_25_63:39;
1899 #endif
1900 } s;
1901 struct cvmx_gmxx_tx_int_reg_cn30xx {
1902 #ifdef __BIG_ENDIAN_BITFIELD
1903 uint64_t reserved_19_63:45;
1904 uint64_t late_col:3;
1905 uint64_t reserved_15_15:1;
1906 uint64_t xsdef:3;
1907 uint64_t reserved_11_11:1;
1908 uint64_t xscol:3;
1909 uint64_t reserved_5_7:3;
1910 uint64_t undflw:3;
1911 uint64_t reserved_1_1:1;
1912 uint64_t pko_nxa:1;
1913 #else
1914 uint64_t pko_nxa:1;
1915 uint64_t reserved_1_1:1;
1916 uint64_t undflw:3;
1917 uint64_t reserved_5_7:3;
1918 uint64_t xscol:3;
1919 uint64_t reserved_11_11:1;
1920 uint64_t xsdef:3;
1921 uint64_t reserved_15_15:1;
1922 uint64_t late_col:3;
1923 uint64_t reserved_19_63:45;
1924 #endif
1925 } cn30xx;
1926 struct cvmx_gmxx_tx_int_reg_cn31xx {
1927 #ifdef __BIG_ENDIAN_BITFIELD
1928 uint64_t reserved_15_63:49;
1929 uint64_t xsdef:3;
1930 uint64_t reserved_11_11:1;
1931 uint64_t xscol:3;
1932 uint64_t reserved_5_7:3;
1933 uint64_t undflw:3;
1934 uint64_t reserved_1_1:1;
1935 uint64_t pko_nxa:1;
1936 #else
1937 uint64_t pko_nxa:1;
1938 uint64_t reserved_1_1:1;
1939 uint64_t undflw:3;
1940 uint64_t reserved_5_7:3;
1941 uint64_t xscol:3;
1942 uint64_t reserved_11_11:1;
1943 uint64_t xsdef:3;
1944 uint64_t reserved_15_63:49;
1945 #endif
1946 } cn31xx;
1947 struct cvmx_gmxx_tx_int_reg_cn38xx {
1948 #ifdef __BIG_ENDIAN_BITFIELD
1949 uint64_t reserved_20_63:44;
1950 uint64_t late_col:4;
1951 uint64_t xsdef:4;
1952 uint64_t xscol:4;
1953 uint64_t reserved_6_7:2;
1954 uint64_t undflw:4;
1955 uint64_t ncb_nxa:1;
1956 uint64_t pko_nxa:1;
1957 #else
1958 uint64_t pko_nxa:1;
1959 uint64_t ncb_nxa:1;
1960 uint64_t undflw:4;
1961 uint64_t reserved_6_7:2;
1962 uint64_t xscol:4;
1963 uint64_t xsdef:4;
1964 uint64_t late_col:4;
1965 uint64_t reserved_20_63:44;
1966 #endif
1967 } cn38xx;
1968 struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
1969 #ifdef __BIG_ENDIAN_BITFIELD
1970 uint64_t reserved_16_63:48;
1971 uint64_t xsdef:4;
1972 uint64_t xscol:4;
1973 uint64_t reserved_6_7:2;
1974 uint64_t undflw:4;
1975 uint64_t ncb_nxa:1;
1976 uint64_t pko_nxa:1;
1977 #else
1978 uint64_t pko_nxa:1;
1979 uint64_t ncb_nxa:1;
1980 uint64_t undflw:4;
1981 uint64_t reserved_6_7:2;
1982 uint64_t xscol:4;
1983 uint64_t xsdef:4;
1984 uint64_t reserved_16_63:48;
1985 #endif
1986 } cn38xxp2;
1987 struct cvmx_gmxx_tx_int_reg_cn52xx {
1988 #ifdef __BIG_ENDIAN_BITFIELD
1989 uint64_t reserved_20_63:44;
1990 uint64_t late_col:4;
1991 uint64_t xsdef:4;
1992 uint64_t xscol:4;
1993 uint64_t reserved_6_7:2;
1994 uint64_t undflw:4;
1995 uint64_t reserved_1_1:1;
1996 uint64_t pko_nxa:1;
1997 #else
1998 uint64_t pko_nxa:1;
1999 uint64_t reserved_1_1:1;
2000 uint64_t undflw:4;
2001 uint64_t reserved_6_7:2;
2002 uint64_t xscol:4;
2003 uint64_t xsdef:4;
2004 uint64_t late_col:4;
2005 uint64_t reserved_20_63:44;
2006 #endif
2007 } cn52xx;
2008 struct cvmx_gmxx_tx_int_reg_cn63xx {
2009 #ifdef __BIG_ENDIAN_BITFIELD
2010 uint64_t reserved_24_63:40;
2011 uint64_t ptp_lost:4;
2012 uint64_t late_col:4;
2013 uint64_t xsdef:4;
2014 uint64_t xscol:4;
2015 uint64_t reserved_6_7:2;
2016 uint64_t undflw:4;
2017 uint64_t reserved_1_1:1;
2018 uint64_t pko_nxa:1;
2019 #else
2020 uint64_t pko_nxa:1;
2021 uint64_t reserved_1_1:1;
2022 uint64_t undflw:4;
2023 uint64_t reserved_6_7:2;
2024 uint64_t xscol:4;
2025 uint64_t xsdef:4;
2026 uint64_t late_col:4;
2027 uint64_t ptp_lost:4;
2028 uint64_t reserved_24_63:40;
2029 #endif
2030 } cn63xx;
2031 struct cvmx_gmxx_tx_int_reg_cn68xx {
2032 #ifdef __BIG_ENDIAN_BITFIELD
2033 uint64_t reserved_25_63:39;
2034 uint64_t xchange:1;
2035 uint64_t ptp_lost:4;
2036 uint64_t late_col:4;
2037 uint64_t xsdef:4;
2038 uint64_t xscol:4;
2039 uint64_t reserved_6_7:2;
2040 uint64_t undflw:4;
2041 uint64_t pko_nxp:1;
2042 uint64_t pko_nxa:1;
2043 #else
2044 uint64_t pko_nxa:1;
2045 uint64_t pko_nxp:1;
2046 uint64_t undflw:4;
2047 uint64_t reserved_6_7:2;
2048 uint64_t xscol:4;
2049 uint64_t xsdef:4;
2050 uint64_t late_col:4;
2051 uint64_t ptp_lost:4;
2052 uint64_t xchange:1;
2053 uint64_t reserved_25_63:39;
2054 #endif
2055 } cn68xx;
2056 struct cvmx_gmxx_tx_int_reg_cnf71xx {
2057 #ifdef __BIG_ENDIAN_BITFIELD
2058 uint64_t reserved_25_63:39;
2059 uint64_t xchange:1;
2060 uint64_t reserved_22_23:2;
2061 uint64_t ptp_lost:2;
2062 uint64_t reserved_18_19:2;
2063 uint64_t late_col:2;
2064 uint64_t reserved_14_15:2;
2065 uint64_t xsdef:2;
2066 uint64_t reserved_10_11:2;
2067 uint64_t xscol:2;
2068 uint64_t reserved_4_7:4;
2069 uint64_t undflw:2;
2070 uint64_t reserved_1_1:1;
2071 uint64_t pko_nxa:1;
2072 #else
2073 uint64_t pko_nxa:1;
2074 uint64_t reserved_1_1:1;
2075 uint64_t undflw:2;
2076 uint64_t reserved_4_7:4;
2077 uint64_t xscol:2;
2078 uint64_t reserved_10_11:2;
2079 uint64_t xsdef:2;
2080 uint64_t reserved_14_15:2;
2081 uint64_t late_col:2;
2082 uint64_t reserved_18_19:2;
2083 uint64_t ptp_lost:2;
2084 uint64_t reserved_22_23:2;
2085 uint64_t xchange:1;
2086 uint64_t reserved_25_63:39;
2087 #endif
2088 } cnf71xx;
2089 };
2090
2091 union cvmx_gmxx_tx_ovr_bp {
2092 uint64_t u64;
2093 struct cvmx_gmxx_tx_ovr_bp_s {
2094 #ifdef __BIG_ENDIAN_BITFIELD
2095 uint64_t reserved_48_63:16;
2096 uint64_t tx_prt_bp:16;
2097 uint64_t reserved_12_31:20;
2098 uint64_t en:4;
2099 uint64_t bp:4;
2100 uint64_t ign_full:4;
2101 #else
2102 uint64_t ign_full:4;
2103 uint64_t bp:4;
2104 uint64_t en:4;
2105 uint64_t reserved_12_31:20;
2106 uint64_t tx_prt_bp:16;
2107 uint64_t reserved_48_63:16;
2108 #endif
2109 } s;
2110 struct cvmx_gmxx_tx_ovr_bp_cn30xx {
2111 #ifdef __BIG_ENDIAN_BITFIELD
2112 uint64_t reserved_11_63:53;
2113 uint64_t en:3;
2114 uint64_t reserved_7_7:1;
2115 uint64_t bp:3;
2116 uint64_t reserved_3_3:1;
2117 uint64_t ign_full:3;
2118 #else
2119 uint64_t ign_full:3;
2120 uint64_t reserved_3_3:1;
2121 uint64_t bp:3;
2122 uint64_t reserved_7_7:1;
2123 uint64_t en:3;
2124 uint64_t reserved_11_63:53;
2125 #endif
2126 } cn30xx;
2127 struct cvmx_gmxx_tx_ovr_bp_cn38xx {
2128 #ifdef __BIG_ENDIAN_BITFIELD
2129 uint64_t reserved_12_63:52;
2130 uint64_t en:4;
2131 uint64_t bp:4;
2132 uint64_t ign_full:4;
2133 #else
2134 uint64_t ign_full:4;
2135 uint64_t bp:4;
2136 uint64_t en:4;
2137 uint64_t reserved_12_63:52;
2138 #endif
2139 } cn38xx;
2140 struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
2141 #ifdef __BIG_ENDIAN_BITFIELD
2142 uint64_t reserved_48_63:16;
2143 uint64_t tx_prt_bp:16;
2144 uint64_t reserved_10_31:22;
2145 uint64_t en:2;
2146 uint64_t reserved_6_7:2;
2147 uint64_t bp:2;
2148 uint64_t reserved_2_3:2;
2149 uint64_t ign_full:2;
2150 #else
2151 uint64_t ign_full:2;
2152 uint64_t reserved_2_3:2;
2153 uint64_t bp:2;
2154 uint64_t reserved_6_7:2;
2155 uint64_t en:2;
2156 uint64_t reserved_10_31:22;
2157 uint64_t tx_prt_bp:16;
2158 uint64_t reserved_48_63:16;
2159 #endif
2160 } cnf71xx;
2161 };
2162
2163 union cvmx_gmxx_tx_prts {
2164 uint64_t u64;
2165 struct cvmx_gmxx_tx_prts_s {
2166 #ifdef __BIG_ENDIAN_BITFIELD
2167 uint64_t reserved_5_63:59;
2168 uint64_t prts:5;
2169 #else
2170 uint64_t prts:5;
2171 uint64_t reserved_5_63:59;
2172 #endif
2173 } s;
2174 };
2175
2176 union cvmx_gmxx_tx_spi_ctl {
2177 uint64_t u64;
2178 struct cvmx_gmxx_tx_spi_ctl_s {
2179 #ifdef __BIG_ENDIAN_BITFIELD
2180 uint64_t reserved_2_63:62;
2181 uint64_t tpa_clr:1;
2182 uint64_t cont_pkt:1;
2183 #else
2184 uint64_t cont_pkt:1;
2185 uint64_t tpa_clr:1;
2186 uint64_t reserved_2_63:62;
2187 #endif
2188 } s;
2189 };
2190
2191 union cvmx_gmxx_tx_spi_max {
2192 uint64_t u64;
2193 struct cvmx_gmxx_tx_spi_max_s {
2194 #ifdef __BIG_ENDIAN_BITFIELD
2195 uint64_t reserved_23_63:41;
2196 uint64_t slice:7;
2197 uint64_t max2:8;
2198 uint64_t max1:8;
2199 #else
2200 uint64_t max1:8;
2201 uint64_t max2:8;
2202 uint64_t slice:7;
2203 uint64_t reserved_23_63:41;
2204 #endif
2205 } s;
2206 struct cvmx_gmxx_tx_spi_max_cn38xx {
2207 #ifdef __BIG_ENDIAN_BITFIELD
2208 uint64_t reserved_16_63:48;
2209 uint64_t max2:8;
2210 uint64_t max1:8;
2211 #else
2212 uint64_t max1:8;
2213 uint64_t max2:8;
2214 uint64_t reserved_16_63:48;
2215 #endif
2216 } cn38xx;
2217 };
2218
2219 union cvmx_gmxx_tx_spi_thresh {
2220 uint64_t u64;
2221 struct cvmx_gmxx_tx_spi_thresh_s {
2222 #ifdef __BIG_ENDIAN_BITFIELD
2223 uint64_t reserved_6_63:58;
2224 uint64_t thresh:6;
2225 #else
2226 uint64_t thresh:6;
2227 uint64_t reserved_6_63:58;
2228 #endif
2229 } s;
2230 };
2231
2232 union cvmx_gmxx_tx_xaui_ctl {
2233 uint64_t u64;
2234 struct cvmx_gmxx_tx_xaui_ctl_s {
2235 #ifdef __BIG_ENDIAN_BITFIELD
2236 uint64_t reserved_11_63:53;
2237 uint64_t hg_pause_hgi:2;
2238 uint64_t hg_en:1;
2239 uint64_t reserved_7_7:1;
2240 uint64_t ls_byp:1;
2241 uint64_t ls:2;
2242 uint64_t reserved_2_3:2;
2243 uint64_t uni_en:1;
2244 uint64_t dic_en:1;
2245 #else
2246 uint64_t dic_en:1;
2247 uint64_t uni_en:1;
2248 uint64_t reserved_2_3:2;
2249 uint64_t ls:2;
2250 uint64_t ls_byp:1;
2251 uint64_t reserved_7_7:1;
2252 uint64_t hg_en:1;
2253 uint64_t hg_pause_hgi:2;
2254 uint64_t reserved_11_63:53;
2255 #endif
2256 } s;
2257 };
2258
2259 #endif
Kernel DRM miscellaneous fixes and cross-tree changes