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drm/rockchip: vop2: Fix the windows switch between different layers
[drm/drm-misc.git] / arch / mips / include / asm / octeon / cvmx-mio-defs.h
blob4ad95d040bb1109535cc403887c5cbfca11a7a49
1 /***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28 #ifndef __CVMX_MIO_DEFS_H__
29 #define __CVMX_MIO_DEFS_H__
30
31 #define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
32 #define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
33 #define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
34 #define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
35 #define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
36 #define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
37 #define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
38 #define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
39 #define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
40 #define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
41 #define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
42 #define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
43 #define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
44 #define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
45 #define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
46 #define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
47 #define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
48 #define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
49 #define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
50 #define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
51 #define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
52 #define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
53 #define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
54 #define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
55 #define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
56 #define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
57 #define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
58 #define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
59 #define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
60 #define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
61 #define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
62 #define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
63 #define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
64 #define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
65 #define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
66 #define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
67 #define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
68 #define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
69 #define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
70 #define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
71 #define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
72 #define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
73 #define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
74 #define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
75 #define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
76 #define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
77 #define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
78 #define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
79 #define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
80 #define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
81 #define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
82 #define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
83 #define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
84 #define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
85 #define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
86 #define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
87 #define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
88 #define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
89 #define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
90 #define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
91 #define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
92 #define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
93 #define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
94 #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
95 #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
96 #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
97 #define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull))
98 #define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
99 #define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
100 #define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
101 #define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
102 #define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
103 #define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
104 #define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
105 #define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
106 #define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
107 #define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
108 #define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
109 #define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
110 #define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
111 #define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
112 #define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
113 #define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
114 #define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
115 #define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
116 #define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
117 #define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
118 #define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
119 #define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
120 #define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
121 #define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
122 #define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
123 #define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
124 #define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
125 #define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
126 #define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
127 #define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
128 #define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
129 #define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
130 #define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
131 #define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
132 #define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
133 #define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
134 #define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
135 #define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
136 #define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
137 #define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
138 #define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
139 #define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
140 #define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
141 #define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
142 #define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
143 #define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
144 #define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
145 #define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
146 #define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
147 #define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
148 #define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
149 #define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
150 #define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
151 #define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
152 #define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
153 #define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
154 #define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
155 #define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
156 #define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
157 #define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
158 #define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
159 #define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
160 #define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
161 #define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
162 #define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
163 #define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
164 #define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
165 #define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
166
167 union cvmx_mio_boot_bist_stat {
168 uint64_t u64;
169 struct cvmx_mio_boot_bist_stat_s {
170 #ifdef __BIG_ENDIAN_BITFIELD
171 uint64_t reserved_0_63:64;
172 #else
173 uint64_t reserved_0_63:64;
174 #endif
175 } s;
176 struct cvmx_mio_boot_bist_stat_cn30xx {
177 #ifdef __BIG_ENDIAN_BITFIELD
178 uint64_t reserved_4_63:60;
179 uint64_t ncbo_1:1;
180 uint64_t ncbo_0:1;
181 uint64_t loc:1;
182 uint64_t ncbi:1;
183 #else
184 uint64_t ncbi:1;
185 uint64_t loc:1;
186 uint64_t ncbo_0:1;
187 uint64_t ncbo_1:1;
188 uint64_t reserved_4_63:60;
189 #endif
190 } cn30xx;
191 struct cvmx_mio_boot_bist_stat_cn38xx {
192 #ifdef __BIG_ENDIAN_BITFIELD
193 uint64_t reserved_3_63:61;
194 uint64_t ncbo_0:1;
195 uint64_t loc:1;
196 uint64_t ncbi:1;
197 #else
198 uint64_t ncbi:1;
199 uint64_t loc:1;
200 uint64_t ncbo_0:1;
201 uint64_t reserved_3_63:61;
202 #endif
203 } cn38xx;
204 struct cvmx_mio_boot_bist_stat_cn50xx {
205 #ifdef __BIG_ENDIAN_BITFIELD
206 uint64_t reserved_6_63:58;
207 uint64_t pcm_1:1;
208 uint64_t pcm_0:1;
209 uint64_t ncbo_1:1;
210 uint64_t ncbo_0:1;
211 uint64_t loc:1;
212 uint64_t ncbi:1;
213 #else
214 uint64_t ncbi:1;
215 uint64_t loc:1;
216 uint64_t ncbo_0:1;
217 uint64_t ncbo_1:1;
218 uint64_t pcm_0:1;
219 uint64_t pcm_1:1;
220 uint64_t reserved_6_63:58;
221 #endif
222 } cn50xx;
223 struct cvmx_mio_boot_bist_stat_cn52xx {
224 #ifdef __BIG_ENDIAN_BITFIELD
225 uint64_t reserved_6_63:58;
226 uint64_t ndf:2;
227 uint64_t ncbo_0:1;
228 uint64_t dma:1;
229 uint64_t loc:1;
230 uint64_t ncbi:1;
231 #else
232 uint64_t ncbi:1;
233 uint64_t loc:1;
234 uint64_t dma:1;
235 uint64_t ncbo_0:1;
236 uint64_t ndf:2;
237 uint64_t reserved_6_63:58;
238 #endif
239 } cn52xx;
240 struct cvmx_mio_boot_bist_stat_cn52xxp1 {
241 #ifdef __BIG_ENDIAN_BITFIELD
242 uint64_t reserved_4_63:60;
243 uint64_t ncbo_0:1;
244 uint64_t dma:1;
245 uint64_t loc:1;
246 uint64_t ncbi:1;
247 #else
248 uint64_t ncbi:1;
249 uint64_t loc:1;
250 uint64_t dma:1;
251 uint64_t ncbo_0:1;
252 uint64_t reserved_4_63:60;
253 #endif
254 } cn52xxp1;
255 struct cvmx_mio_boot_bist_stat_cn61xx {
256 #ifdef __BIG_ENDIAN_BITFIELD
257 uint64_t reserved_12_63:52;
258 uint64_t stat:12;
259 #else
260 uint64_t stat:12;
261 uint64_t reserved_12_63:52;
262 #endif
263 } cn61xx;
264 struct cvmx_mio_boot_bist_stat_cn63xx {
265 #ifdef __BIG_ENDIAN_BITFIELD
266 uint64_t reserved_9_63:55;
267 uint64_t stat:9;
268 #else
269 uint64_t stat:9;
270 uint64_t reserved_9_63:55;
271 #endif
272 } cn63xx;
273 struct cvmx_mio_boot_bist_stat_cn66xx {
274 #ifdef __BIG_ENDIAN_BITFIELD
275 uint64_t reserved_10_63:54;
276 uint64_t stat:10;
277 #else
278 uint64_t stat:10;
279 uint64_t reserved_10_63:54;
280 #endif
281 } cn66xx;
282 };
283
284 union cvmx_mio_boot_comp {
285 uint64_t u64;
286 struct cvmx_mio_boot_comp_s {
287 #ifdef __BIG_ENDIAN_BITFIELD
288 uint64_t reserved_0_63:64;
289 #else
290 uint64_t reserved_0_63:64;
291 #endif
292 } s;
293 struct cvmx_mio_boot_comp_cn50xx {
294 #ifdef __BIG_ENDIAN_BITFIELD
295 uint64_t reserved_10_63:54;
296 uint64_t pctl:5;
297 uint64_t nctl:5;
298 #else
299 uint64_t nctl:5;
300 uint64_t pctl:5;
301 uint64_t reserved_10_63:54;
302 #endif
303 } cn50xx;
304 struct cvmx_mio_boot_comp_cn61xx {
305 #ifdef __BIG_ENDIAN_BITFIELD
306 uint64_t reserved_12_63:52;
307 uint64_t pctl:6;
308 uint64_t nctl:6;
309 #else
310 uint64_t nctl:6;
311 uint64_t pctl:6;
312 uint64_t reserved_12_63:52;
313 #endif
314 } cn61xx;
315 };
316
317 union cvmx_mio_boot_dma_cfgx {
318 uint64_t u64;
319 struct cvmx_mio_boot_dma_cfgx_s {
320 #ifdef __BIG_ENDIAN_BITFIELD
321 uint64_t en:1;
322 uint64_t rw:1;
323 uint64_t clr:1;
324 uint64_t reserved_60_60:1;
325 uint64_t swap32:1;
326 uint64_t swap16:1;
327 uint64_t swap8:1;
328 uint64_t endian:1;
329 uint64_t size:20;
330 uint64_t adr:36;
331 #else
332 uint64_t adr:36;
333 uint64_t size:20;
334 uint64_t endian:1;
335 uint64_t swap8:1;
336 uint64_t swap16:1;
337 uint64_t swap32:1;
338 uint64_t reserved_60_60:1;
339 uint64_t clr:1;
340 uint64_t rw:1;
341 uint64_t en:1;
342 #endif
343 } s;
344 };
345
346 union cvmx_mio_boot_dma_intx {
347 uint64_t u64;
348 struct cvmx_mio_boot_dma_intx_s {
349 #ifdef __BIG_ENDIAN_BITFIELD
350 uint64_t reserved_2_63:62;
351 uint64_t dmarq:1;
352 uint64_t done:1;
353 #else
354 uint64_t done:1;
355 uint64_t dmarq:1;
356 uint64_t reserved_2_63:62;
357 #endif
358 } s;
359 };
360
361 union cvmx_mio_boot_dma_int_enx {
362 uint64_t u64;
363 struct cvmx_mio_boot_dma_int_enx_s {
364 #ifdef __BIG_ENDIAN_BITFIELD
365 uint64_t reserved_2_63:62;
366 uint64_t dmarq:1;
367 uint64_t done:1;
368 #else
369 uint64_t done:1;
370 uint64_t dmarq:1;
371 uint64_t reserved_2_63:62;
372 #endif
373 } s;
374 };
375
376 union cvmx_mio_boot_dma_timx {
377 uint64_t u64;
378 struct cvmx_mio_boot_dma_timx_s {
379 #ifdef __BIG_ENDIAN_BITFIELD
380 uint64_t dmack_pi:1;
381 uint64_t dmarq_pi:1;
382 uint64_t tim_mult:2;
383 uint64_t rd_dly:3;
384 uint64_t ddr:1;
385 uint64_t width:1;
386 uint64_t reserved_48_54:7;
387 uint64_t pause:6;
388 uint64_t dmack_h:6;
389 uint64_t we_n:6;
390 uint64_t we_a:6;
391 uint64_t oe_n:6;
392 uint64_t oe_a:6;
393 uint64_t dmack_s:6;
394 uint64_t dmarq:6;
395 #else
396 uint64_t dmarq:6;
397 uint64_t dmack_s:6;
398 uint64_t oe_a:6;
399 uint64_t oe_n:6;
400 uint64_t we_a:6;
401 uint64_t we_n:6;
402 uint64_t dmack_h:6;
403 uint64_t pause:6;
404 uint64_t reserved_48_54:7;
405 uint64_t width:1;
406 uint64_t ddr:1;
407 uint64_t rd_dly:3;
408 uint64_t tim_mult:2;
409 uint64_t dmarq_pi:1;
410 uint64_t dmack_pi:1;
411 #endif
412 } s;
413 };
414
415 union cvmx_mio_boot_err {
416 uint64_t u64;
417 struct cvmx_mio_boot_err_s {
418 #ifdef __BIG_ENDIAN_BITFIELD
419 uint64_t reserved_2_63:62;
420 uint64_t wait_err:1;
421 uint64_t adr_err:1;
422 #else
423 uint64_t adr_err:1;
424 uint64_t wait_err:1;
425 uint64_t reserved_2_63:62;
426 #endif
427 } s;
428 };
429
430 union cvmx_mio_boot_int {
431 uint64_t u64;
432 struct cvmx_mio_boot_int_s {
433 #ifdef __BIG_ENDIAN_BITFIELD
434 uint64_t reserved_2_63:62;
435 uint64_t wait_int:1;
436 uint64_t adr_int:1;
437 #else
438 uint64_t adr_int:1;
439 uint64_t wait_int:1;
440 uint64_t reserved_2_63:62;
441 #endif
442 } s;
443 };
444
445 union cvmx_mio_boot_loc_adr {
446 uint64_t u64;
447 struct cvmx_mio_boot_loc_adr_s {
448 #ifdef __BIG_ENDIAN_BITFIELD
449 uint64_t reserved_8_63:56;
450 uint64_t adr:5;
451 uint64_t reserved_0_2:3;
452 #else
453 uint64_t reserved_0_2:3;
454 uint64_t adr:5;
455 uint64_t reserved_8_63:56;
456 #endif
457 } s;
458 };
459
460 union cvmx_mio_boot_loc_cfgx {
461 uint64_t u64;
462 struct cvmx_mio_boot_loc_cfgx_s {
463 #ifdef __BIG_ENDIAN_BITFIELD
464 uint64_t reserved_32_63:32;
465 uint64_t en:1;
466 uint64_t reserved_28_30:3;
467 uint64_t base:25;
468 uint64_t reserved_0_2:3;
469 #else
470 uint64_t reserved_0_2:3;
471 uint64_t base:25;
472 uint64_t reserved_28_30:3;
473 uint64_t en:1;
474 uint64_t reserved_32_63:32;
475 #endif
476 } s;
477 };
478
479 union cvmx_mio_boot_loc_dat {
480 uint64_t u64;
481 struct cvmx_mio_boot_loc_dat_s {
482 #ifdef __BIG_ENDIAN_BITFIELD
483 uint64_t data:64;
484 #else
485 uint64_t data:64;
486 #endif
487 } s;
488 };
489
490 union cvmx_mio_boot_pin_defs {
491 uint64_t u64;
492 struct cvmx_mio_boot_pin_defs_s {
493 #ifdef __BIG_ENDIAN_BITFIELD
494 uint64_t reserved_32_63:32;
495 uint64_t user1:16;
496 uint64_t ale:1;
497 uint64_t width:1;
498 uint64_t dmack_p2:1;
499 uint64_t dmack_p1:1;
500 uint64_t dmack_p0:1;
501 uint64_t term:2;
502 uint64_t nand:1;
503 uint64_t user0:8;
504 #else
505 uint64_t user0:8;
506 uint64_t nand:1;
507 uint64_t term:2;
508 uint64_t dmack_p0:1;
509 uint64_t dmack_p1:1;
510 uint64_t dmack_p2:1;
511 uint64_t width:1;
512 uint64_t ale:1;
513 uint64_t user1:16;
514 uint64_t reserved_32_63:32;
515 #endif
516 } s;
517 struct cvmx_mio_boot_pin_defs_cn52xx {
518 #ifdef __BIG_ENDIAN_BITFIELD
519 uint64_t reserved_16_63:48;
520 uint64_t ale:1;
521 uint64_t width:1;
522 uint64_t reserved_13_13:1;
523 uint64_t dmack_p1:1;
524 uint64_t dmack_p0:1;
525 uint64_t term:2;
526 uint64_t nand:1;
527 uint64_t reserved_0_7:8;
528 #else
529 uint64_t reserved_0_7:8;
530 uint64_t nand:1;
531 uint64_t term:2;
532 uint64_t dmack_p0:1;
533 uint64_t dmack_p1:1;
534 uint64_t reserved_13_13:1;
535 uint64_t width:1;
536 uint64_t ale:1;
537 uint64_t reserved_16_63:48;
538 #endif
539 } cn52xx;
540 struct cvmx_mio_boot_pin_defs_cn56xx {
541 #ifdef __BIG_ENDIAN_BITFIELD
542 uint64_t reserved_16_63:48;
543 uint64_t ale:1;
544 uint64_t width:1;
545 uint64_t dmack_p2:1;
546 uint64_t dmack_p1:1;
547 uint64_t dmack_p0:1;
548 uint64_t term:2;
549 uint64_t reserved_0_8:9;
550 #else
551 uint64_t reserved_0_8:9;
552 uint64_t term:2;
553 uint64_t dmack_p0:1;
554 uint64_t dmack_p1:1;
555 uint64_t dmack_p2:1;
556 uint64_t width:1;
557 uint64_t ale:1;
558 uint64_t reserved_16_63:48;
559 #endif
560 } cn56xx;
561 struct cvmx_mio_boot_pin_defs_cn61xx {
562 #ifdef __BIG_ENDIAN_BITFIELD
563 uint64_t reserved_32_63:32;
564 uint64_t user1:16;
565 uint64_t ale:1;
566 uint64_t width:1;
567 uint64_t reserved_13_13:1;
568 uint64_t dmack_p1:1;
569 uint64_t dmack_p0:1;
570 uint64_t term:2;
571 uint64_t nand:1;
572 uint64_t user0:8;
573 #else
574 uint64_t user0:8;
575 uint64_t nand:1;
576 uint64_t term:2;
577 uint64_t dmack_p0:1;
578 uint64_t dmack_p1:1;
579 uint64_t reserved_13_13:1;
580 uint64_t width:1;
581 uint64_t ale:1;
582 uint64_t user1:16;
583 uint64_t reserved_32_63:32;
584 #endif
585 } cn61xx;
586 };
587
588 union cvmx_mio_boot_reg_cfgx {
589 uint64_t u64;
590 struct cvmx_mio_boot_reg_cfgx_s {
591 #ifdef __BIG_ENDIAN_BITFIELD
592 uint64_t reserved_44_63:20;
593 uint64_t dmack:2;
594 uint64_t tim_mult:2;
595 uint64_t rd_dly:3;
596 uint64_t sam:1;
597 uint64_t we_ext:2;
598 uint64_t oe_ext:2;
599 uint64_t en:1;
600 uint64_t orbit:1;
601 uint64_t ale:1;
602 uint64_t width:1;
603 uint64_t size:12;
604 uint64_t base:16;
605 #else
606 uint64_t base:16;
607 uint64_t size:12;
608 uint64_t width:1;
609 uint64_t ale:1;
610 uint64_t orbit:1;
611 uint64_t en:1;
612 uint64_t oe_ext:2;
613 uint64_t we_ext:2;
614 uint64_t sam:1;
615 uint64_t rd_dly:3;
616 uint64_t tim_mult:2;
617 uint64_t dmack:2;
618 uint64_t reserved_44_63:20;
619 #endif
620 } s;
621 struct cvmx_mio_boot_reg_cfgx_cn30xx {
622 #ifdef __BIG_ENDIAN_BITFIELD
623 uint64_t reserved_37_63:27;
624 uint64_t sam:1;
625 uint64_t we_ext:2;
626 uint64_t oe_ext:2;
627 uint64_t en:1;
628 uint64_t orbit:1;
629 uint64_t ale:1;
630 uint64_t width:1;
631 uint64_t size:12;
632 uint64_t base:16;
633 #else
634 uint64_t base:16;
635 uint64_t size:12;
636 uint64_t width:1;
637 uint64_t ale:1;
638 uint64_t orbit:1;
639 uint64_t en:1;
640 uint64_t oe_ext:2;
641 uint64_t we_ext:2;
642 uint64_t sam:1;
643 uint64_t reserved_37_63:27;
644 #endif
645 } cn30xx;
646 struct cvmx_mio_boot_reg_cfgx_cn38xx {
647 #ifdef __BIG_ENDIAN_BITFIELD
648 uint64_t reserved_32_63:32;
649 uint64_t en:1;
650 uint64_t orbit:1;
651 uint64_t reserved_28_29:2;
652 uint64_t size:12;
653 uint64_t base:16;
654 #else
655 uint64_t base:16;
656 uint64_t size:12;
657 uint64_t reserved_28_29:2;
658 uint64_t orbit:1;
659 uint64_t en:1;
660 uint64_t reserved_32_63:32;
661 #endif
662 } cn38xx;
663 struct cvmx_mio_boot_reg_cfgx_cn50xx {
664 #ifdef __BIG_ENDIAN_BITFIELD
665 uint64_t reserved_42_63:22;
666 uint64_t tim_mult:2;
667 uint64_t rd_dly:3;
668 uint64_t sam:1;
669 uint64_t we_ext:2;
670 uint64_t oe_ext:2;
671 uint64_t en:1;
672 uint64_t orbit:1;
673 uint64_t ale:1;
674 uint64_t width:1;
675 uint64_t size:12;
676 uint64_t base:16;
677 #else
678 uint64_t base:16;
679 uint64_t size:12;
680 uint64_t width:1;
681 uint64_t ale:1;
682 uint64_t orbit:1;
683 uint64_t en:1;
684 uint64_t oe_ext:2;
685 uint64_t we_ext:2;
686 uint64_t sam:1;
687 uint64_t rd_dly:3;
688 uint64_t tim_mult:2;
689 uint64_t reserved_42_63:22;
690 #endif
691 } cn50xx;
692 };
693
694 union cvmx_mio_boot_reg_timx {
695 uint64_t u64;
696 struct cvmx_mio_boot_reg_timx_s {
697 #ifdef __BIG_ENDIAN_BITFIELD
698 uint64_t pagem:1;
699 uint64_t waitm:1;
700 uint64_t pages:2;
701 uint64_t ale:6;
702 uint64_t page:6;
703 uint64_t wait:6;
704 uint64_t pause:6;
705 uint64_t wr_hld:6;
706 uint64_t rd_hld:6;
707 uint64_t we:6;
708 uint64_t oe:6;
709 uint64_t ce:6;
710 uint64_t adr:6;
711 #else
712 uint64_t adr:6;
713 uint64_t ce:6;
714 uint64_t oe:6;
715 uint64_t we:6;
716 uint64_t rd_hld:6;
717 uint64_t wr_hld:6;
718 uint64_t pause:6;
719 uint64_t wait:6;
720 uint64_t page:6;
721 uint64_t ale:6;
722 uint64_t pages:2;
723 uint64_t waitm:1;
724 uint64_t pagem:1;
725 #endif
726 } s;
727 struct cvmx_mio_boot_reg_timx_cn38xx {
728 #ifdef __BIG_ENDIAN_BITFIELD
729 uint64_t pagem:1;
730 uint64_t waitm:1;
731 uint64_t pages:2;
732 uint64_t reserved_54_59:6;
733 uint64_t page:6;
734 uint64_t wait:6;
735 uint64_t pause:6;
736 uint64_t wr_hld:6;
737 uint64_t rd_hld:6;
738 uint64_t we:6;
739 uint64_t oe:6;
740 uint64_t ce:6;
741 uint64_t adr:6;
742 #else
743 uint64_t adr:6;
744 uint64_t ce:6;
745 uint64_t oe:6;
746 uint64_t we:6;
747 uint64_t rd_hld:6;
748 uint64_t wr_hld:6;
749 uint64_t pause:6;
750 uint64_t wait:6;
751 uint64_t page:6;
752 uint64_t reserved_54_59:6;
753 uint64_t pages:2;
754 uint64_t waitm:1;
755 uint64_t pagem:1;
756 #endif
757 } cn38xx;
758 };
759
760 union cvmx_mio_boot_thr {
761 uint64_t u64;
762 struct cvmx_mio_boot_thr_s {
763 #ifdef __BIG_ENDIAN_BITFIELD
764 uint64_t reserved_22_63:42;
765 uint64_t dma_thr:6;
766 uint64_t reserved_14_15:2;
767 uint64_t fif_cnt:6;
768 uint64_t reserved_6_7:2;
769 uint64_t fif_thr:6;
770 #else
771 uint64_t fif_thr:6;
772 uint64_t reserved_6_7:2;
773 uint64_t fif_cnt:6;
774 uint64_t reserved_14_15:2;
775 uint64_t dma_thr:6;
776 uint64_t reserved_22_63:42;
777 #endif
778 } s;
779 struct cvmx_mio_boot_thr_cn30xx {
780 #ifdef __BIG_ENDIAN_BITFIELD
781 uint64_t reserved_14_63:50;
782 uint64_t fif_cnt:6;
783 uint64_t reserved_6_7:2;
784 uint64_t fif_thr:6;
785 #else
786 uint64_t fif_thr:6;
787 uint64_t reserved_6_7:2;
788 uint64_t fif_cnt:6;
789 uint64_t reserved_14_63:50;
790 #endif
791 } cn30xx;
792 };
793
794 union cvmx_mio_emm_buf_dat {
795 uint64_t u64;
796 struct cvmx_mio_emm_buf_dat_s {
797 #ifdef __BIG_ENDIAN_BITFIELD
798 uint64_t dat:64;
799 #else
800 uint64_t dat:64;
801 #endif
802 } s;
803 };
804
805 union cvmx_mio_emm_buf_idx {
806 uint64_t u64;
807 struct cvmx_mio_emm_buf_idx_s {
808 #ifdef __BIG_ENDIAN_BITFIELD
809 uint64_t reserved_17_63:47;
810 uint64_t inc:1;
811 uint64_t reserved_7_15:9;
812 uint64_t buf_num:1;
813 uint64_t offset:6;
814 #else
815 uint64_t offset:6;
816 uint64_t buf_num:1;
817 uint64_t reserved_7_15:9;
818 uint64_t inc:1;
819 uint64_t reserved_17_63:47;
820 #endif
821 } s;
822 };
823
824 union cvmx_mio_emm_cfg {
825 uint64_t u64;
826 struct cvmx_mio_emm_cfg_s {
827 #ifdef __BIG_ENDIAN_BITFIELD
828 uint64_t reserved_17_63:47;
829 uint64_t boot_fail:1;
830 uint64_t reserved_4_15:12;
831 uint64_t bus_ena:4;
832 #else
833 uint64_t bus_ena:4;
834 uint64_t reserved_4_15:12;
835 uint64_t boot_fail:1;
836 uint64_t reserved_17_63:47;
837 #endif
838 } s;
839 };
840
841 union cvmx_mio_emm_cmd {
842 uint64_t u64;
843 struct cvmx_mio_emm_cmd_s {
844 #ifdef __BIG_ENDIAN_BITFIELD
845 uint64_t reserved_62_63:2;
846 uint64_t bus_id:2;
847 uint64_t cmd_val:1;
848 uint64_t reserved_56_58:3;
849 uint64_t dbuf:1;
850 uint64_t offset:6;
851 uint64_t reserved_43_48:6;
852 uint64_t ctype_xor:2;
853 uint64_t rtype_xor:3;
854 uint64_t cmd_idx:6;
855 uint64_t arg:32;
856 #else
857 uint64_t arg:32;
858 uint64_t cmd_idx:6;
859 uint64_t rtype_xor:3;
860 uint64_t ctype_xor:2;
861 uint64_t reserved_43_48:6;
862 uint64_t offset:6;
863 uint64_t dbuf:1;
864 uint64_t reserved_56_58:3;
865 uint64_t cmd_val:1;
866 uint64_t bus_id:2;
867 uint64_t reserved_62_63:2;
868 #endif
869 } s;
870 };
871
872 union cvmx_mio_emm_dma {
873 uint64_t u64;
874 struct cvmx_mio_emm_dma_s {
875 #ifdef __BIG_ENDIAN_BITFIELD
876 uint64_t reserved_62_63:2;
877 uint64_t bus_id:2;
878 uint64_t dma_val:1;
879 uint64_t sector:1;
880 uint64_t dat_null:1;
881 uint64_t thres:6;
882 uint64_t rel_wr:1;
883 uint64_t rw:1;
884 uint64_t multi:1;
885 uint64_t block_cnt:16;
886 uint64_t card_addr:32;
887 #else
888 uint64_t card_addr:32;
889 uint64_t block_cnt:16;
890 uint64_t multi:1;
891 uint64_t rw:1;
892 uint64_t rel_wr:1;
893 uint64_t thres:6;
894 uint64_t dat_null:1;
895 uint64_t sector:1;
896 uint64_t dma_val:1;
897 uint64_t bus_id:2;
898 uint64_t reserved_62_63:2;
899 #endif
900 } s;
901 };
902
903 union cvmx_mio_emm_int {
904 uint64_t u64;
905 struct cvmx_mio_emm_int_s {
906 #ifdef __BIG_ENDIAN_BITFIELD
907 uint64_t reserved_7_63:57;
908 uint64_t switch_err:1;
909 uint64_t switch_done:1;
910 uint64_t dma_err:1;
911 uint64_t cmd_err:1;
912 uint64_t dma_done:1;
913 uint64_t cmd_done:1;
914 uint64_t buf_done:1;
915 #else
916 uint64_t buf_done:1;
917 uint64_t cmd_done:1;
918 uint64_t dma_done:1;
919 uint64_t cmd_err:1;
920 uint64_t dma_err:1;
921 uint64_t switch_done:1;
922 uint64_t switch_err:1;
923 uint64_t reserved_7_63:57;
924 #endif
925 } s;
926 };
927
928 union cvmx_mio_emm_int_en {
929 uint64_t u64;
930 struct cvmx_mio_emm_int_en_s {
931 #ifdef __BIG_ENDIAN_BITFIELD
932 uint64_t reserved_7_63:57;
933 uint64_t switch_err:1;
934 uint64_t switch_done:1;
935 uint64_t dma_err:1;
936 uint64_t cmd_err:1;
937 uint64_t dma_done:1;
938 uint64_t cmd_done:1;
939 uint64_t buf_done:1;
940 #else
941 uint64_t buf_done:1;
942 uint64_t cmd_done:1;
943 uint64_t dma_done:1;
944 uint64_t cmd_err:1;
945 uint64_t dma_err:1;
946 uint64_t switch_done:1;
947 uint64_t switch_err:1;
948 uint64_t reserved_7_63:57;
949 #endif
950 } s;
951 };
952
953 union cvmx_mio_emm_modex {
954 uint64_t u64;
955 struct cvmx_mio_emm_modex_s {
956 #ifdef __BIG_ENDIAN_BITFIELD
957 uint64_t reserved_49_63:15;
958 uint64_t hs_timing:1;
959 uint64_t reserved_43_47:5;
960 uint64_t bus_width:3;
961 uint64_t reserved_36_39:4;
962 uint64_t power_class:4;
963 uint64_t clk_hi:16;
964 uint64_t clk_lo:16;
965 #else
966 uint64_t clk_lo:16;
967 uint64_t clk_hi:16;
968 uint64_t power_class:4;
969 uint64_t reserved_36_39:4;
970 uint64_t bus_width:3;
971 uint64_t reserved_43_47:5;
972 uint64_t hs_timing:1;
973 uint64_t reserved_49_63:15;
974 #endif
975 } s;
976 };
977
978 union cvmx_mio_emm_rca {
979 uint64_t u64;
980 struct cvmx_mio_emm_rca_s {
981 #ifdef __BIG_ENDIAN_BITFIELD
982 uint64_t reserved_16_63:48;
983 uint64_t card_rca:16;
984 #else
985 uint64_t card_rca:16;
986 uint64_t reserved_16_63:48;
987 #endif
988 } s;
989 };
990
991 union cvmx_mio_emm_rsp_hi {
992 uint64_t u64;
993 struct cvmx_mio_emm_rsp_hi_s {
994 #ifdef __BIG_ENDIAN_BITFIELD
995 uint64_t dat:64;
996 #else
997 uint64_t dat:64;
998 #endif
999 } s;
1000 };
1001
1002 union cvmx_mio_emm_rsp_lo {
1003 uint64_t u64;
1004 struct cvmx_mio_emm_rsp_lo_s {
1005 #ifdef __BIG_ENDIAN_BITFIELD
1006 uint64_t dat:64;
1007 #else
1008 uint64_t dat:64;
1009 #endif
1010 } s;
1011 };
1012
1013 union cvmx_mio_emm_rsp_sts {
1014 uint64_t u64;
1015 struct cvmx_mio_emm_rsp_sts_s {
1016 #ifdef __BIG_ENDIAN_BITFIELD
1017 uint64_t reserved_62_63:2;
1018 uint64_t bus_id:2;
1019 uint64_t cmd_val:1;
1020 uint64_t switch_val:1;
1021 uint64_t dma_val:1;
1022 uint64_t dma_pend:1;
1023 uint64_t reserved_29_55:27;
1024 uint64_t dbuf_err:1;
1025 uint64_t reserved_24_27:4;
1026 uint64_t dbuf:1;
1027 uint64_t blk_timeout:1;
1028 uint64_t blk_crc_err:1;
1029 uint64_t rsp_busybit:1;
1030 uint64_t stp_timeout:1;
1031 uint64_t stp_crc_err:1;
1032 uint64_t stp_bad_sts:1;
1033 uint64_t stp_val:1;
1034 uint64_t rsp_timeout:1;
1035 uint64_t rsp_crc_err:1;
1036 uint64_t rsp_bad_sts:1;
1037 uint64_t rsp_val:1;
1038 uint64_t rsp_type:3;
1039 uint64_t cmd_type:2;
1040 uint64_t cmd_idx:6;
1041 uint64_t cmd_done:1;
1042 #else
1043 uint64_t cmd_done:1;
1044 uint64_t cmd_idx:6;
1045 uint64_t cmd_type:2;
1046 uint64_t rsp_type:3;
1047 uint64_t rsp_val:1;
1048 uint64_t rsp_bad_sts:1;
1049 uint64_t rsp_crc_err:1;
1050 uint64_t rsp_timeout:1;
1051 uint64_t stp_val:1;
1052 uint64_t stp_bad_sts:1;
1053 uint64_t stp_crc_err:1;
1054 uint64_t stp_timeout:1;
1055 uint64_t rsp_busybit:1;
1056 uint64_t blk_crc_err:1;
1057 uint64_t blk_timeout:1;
1058 uint64_t dbuf:1;
1059 uint64_t reserved_24_27:4;
1060 uint64_t dbuf_err:1;
1061 uint64_t reserved_29_55:27;
1062 uint64_t dma_pend:1;
1063 uint64_t dma_val:1;
1064 uint64_t switch_val:1;
1065 uint64_t cmd_val:1;
1066 uint64_t bus_id:2;
1067 uint64_t reserved_62_63:2;
1068 #endif
1069 } s;
1070 };
1071
1072 union cvmx_mio_emm_sample {
1073 uint64_t u64;
1074 struct cvmx_mio_emm_sample_s {
1075 #ifdef __BIG_ENDIAN_BITFIELD
1076 uint64_t reserved_26_63:38;
1077 uint64_t cmd_cnt:10;
1078 uint64_t reserved_10_15:6;
1079 uint64_t dat_cnt:10;
1080 #else
1081 uint64_t dat_cnt:10;
1082 uint64_t reserved_10_15:6;
1083 uint64_t cmd_cnt:10;
1084 uint64_t reserved_26_63:38;
1085 #endif
1086 } s;
1087 };
1088
1089 union cvmx_mio_emm_sts_mask {
1090 uint64_t u64;
1091 struct cvmx_mio_emm_sts_mask_s {
1092 #ifdef __BIG_ENDIAN_BITFIELD
1093 uint64_t reserved_32_63:32;
1094 uint64_t sts_msk:32;
1095 #else
1096 uint64_t sts_msk:32;
1097 uint64_t reserved_32_63:32;
1098 #endif
1099 } s;
1100 };
1101
1102 union cvmx_mio_emm_switch {
1103 uint64_t u64;
1104 struct cvmx_mio_emm_switch_s {
1105 #ifdef __BIG_ENDIAN_BITFIELD
1106 uint64_t reserved_62_63:2;
1107 uint64_t bus_id:2;
1108 uint64_t switch_exe:1;
1109 uint64_t switch_err0:1;
1110 uint64_t switch_err1:1;
1111 uint64_t switch_err2:1;
1112 uint64_t reserved_49_55:7;
1113 uint64_t hs_timing:1;
1114 uint64_t reserved_43_47:5;
1115 uint64_t bus_width:3;
1116 uint64_t reserved_36_39:4;
1117 uint64_t power_class:4;
1118 uint64_t clk_hi:16;
1119 uint64_t clk_lo:16;
1120 #else
1121 uint64_t clk_lo:16;
1122 uint64_t clk_hi:16;
1123 uint64_t power_class:4;
1124 uint64_t reserved_36_39:4;
1125 uint64_t bus_width:3;
1126 uint64_t reserved_43_47:5;
1127 uint64_t hs_timing:1;
1128 uint64_t reserved_49_55:7;
1129 uint64_t switch_err2:1;
1130 uint64_t switch_err1:1;
1131 uint64_t switch_err0:1;
1132 uint64_t switch_exe:1;
1133 uint64_t bus_id:2;
1134 uint64_t reserved_62_63:2;
1135 #endif
1136 } s;
1137 };
1138
1139 union cvmx_mio_emm_wdog {
1140 uint64_t u64;
1141 struct cvmx_mio_emm_wdog_s {
1142 #ifdef __BIG_ENDIAN_BITFIELD
1143 uint64_t reserved_26_63:38;
1144 uint64_t clk_cnt:26;
1145 #else
1146 uint64_t clk_cnt:26;
1147 uint64_t reserved_26_63:38;
1148 #endif
1149 } s;
1150 };
1151
1152 union cvmx_mio_fus_bnk_datx {
1153 uint64_t u64;
1154 struct cvmx_mio_fus_bnk_datx_s {
1155 #ifdef __BIG_ENDIAN_BITFIELD
1156 uint64_t dat:64;
1157 #else
1158 uint64_t dat:64;
1159 #endif
1160 } s;
1161 };
1162
1163 union cvmx_mio_fus_dat0 {
1164 uint64_t u64;
1165 struct cvmx_mio_fus_dat0_s {
1166 #ifdef __BIG_ENDIAN_BITFIELD
1167 uint64_t reserved_32_63:32;
1168 uint64_t man_info:32;
1169 #else
1170 uint64_t man_info:32;
1171 uint64_t reserved_32_63:32;
1172 #endif
1173 } s;
1174 };
1175
1176 union cvmx_mio_fus_dat1 {
1177 uint64_t u64;
1178 struct cvmx_mio_fus_dat1_s {
1179 #ifdef __BIG_ENDIAN_BITFIELD
1180 uint64_t reserved_32_63:32;
1181 uint64_t man_info:32;
1182 #else
1183 uint64_t man_info:32;
1184 uint64_t reserved_32_63:32;
1185 #endif
1186 } s;
1187 };
1188
1189 union cvmx_mio_fus_dat2 {
1190 uint64_t u64;
1191 struct cvmx_mio_fus_dat2_s {
1192 #ifdef __BIG_ENDIAN_BITFIELD
1193 uint64_t reserved_59_63:5;
1194 uint64_t run_platform:3;
1195 uint64_t gbl_pwr_throttle:8;
1196 uint64_t fus118:1;
1197 uint64_t rom_info:10;
1198 uint64_t power_limit:2;
1199 uint64_t dorm_crypto:1;
1200 uint64_t fus318:1;
1201 uint64_t raid_en:1;
1202 uint64_t reserved_30_31:2;
1203 uint64_t nokasu:1;
1204 uint64_t nodfa_cp2:1;
1205 uint64_t nomul:1;
1206 uint64_t nocrypto:1;
1207 uint64_t rst_sht:1;
1208 uint64_t bist_dis:1;
1209 uint64_t chip_id:8;
1210 uint64_t reserved_0_15:16;
1211 #else
1212 uint64_t reserved_0_15:16;
1213 uint64_t chip_id:8;
1214 uint64_t bist_dis:1;
1215 uint64_t rst_sht:1;
1216 uint64_t nocrypto:1;
1217 uint64_t nomul:1;
1218 uint64_t nodfa_cp2:1;
1219 uint64_t nokasu:1;
1220 uint64_t reserved_30_31:2;
1221 uint64_t raid_en:1;
1222 uint64_t fus318:1;
1223 uint64_t dorm_crypto:1;
1224 uint64_t power_limit:2;
1225 uint64_t rom_info:10;
1226 uint64_t fus118:1;
1227 uint64_t gbl_pwr_throttle:8;
1228 uint64_t run_platform:3;
1229 uint64_t reserved_59_63:5;
1230 #endif
1231 } s;
1232 struct cvmx_mio_fus_dat2_cn30xx {
1233 #ifdef __BIG_ENDIAN_BITFIELD
1234 uint64_t reserved_29_63:35;
1235 uint64_t nodfa_cp2:1;
1236 uint64_t nomul:1;
1237 uint64_t nocrypto:1;
1238 uint64_t rst_sht:1;
1239 uint64_t bist_dis:1;
1240 uint64_t chip_id:8;
1241 uint64_t pll_off:4;
1242 uint64_t reserved_1_11:11;
1243 uint64_t pp_dis:1;
1244 #else
1245 uint64_t pp_dis:1;
1246 uint64_t reserved_1_11:11;
1247 uint64_t pll_off:4;
1248 uint64_t chip_id:8;
1249 uint64_t bist_dis:1;
1250 uint64_t rst_sht:1;
1251 uint64_t nocrypto:1;
1252 uint64_t nomul:1;
1253 uint64_t nodfa_cp2:1;
1254 uint64_t reserved_29_63:35;
1255 #endif
1256 } cn30xx;
1257 struct cvmx_mio_fus_dat2_cn31xx {
1258 #ifdef __BIG_ENDIAN_BITFIELD
1259 uint64_t reserved_29_63:35;
1260 uint64_t nodfa_cp2:1;
1261 uint64_t nomul:1;
1262 uint64_t nocrypto:1;
1263 uint64_t rst_sht:1;
1264 uint64_t bist_dis:1;
1265 uint64_t chip_id:8;
1266 uint64_t pll_off:4;
1267 uint64_t reserved_2_11:10;
1268 uint64_t pp_dis:2;
1269 #else
1270 uint64_t pp_dis:2;
1271 uint64_t reserved_2_11:10;
1272 uint64_t pll_off:4;
1273 uint64_t chip_id:8;
1274 uint64_t bist_dis:1;
1275 uint64_t rst_sht:1;
1276 uint64_t nocrypto:1;
1277 uint64_t nomul:1;
1278 uint64_t nodfa_cp2:1;
1279 uint64_t reserved_29_63:35;
1280 #endif
1281 } cn31xx;
1282 struct cvmx_mio_fus_dat2_cn38xx {
1283 #ifdef __BIG_ENDIAN_BITFIELD
1284 uint64_t reserved_29_63:35;
1285 uint64_t nodfa_cp2:1;
1286 uint64_t nomul:1;
1287 uint64_t nocrypto:1;
1288 uint64_t rst_sht:1;
1289 uint64_t bist_dis:1;
1290 uint64_t chip_id:8;
1291 uint64_t pp_dis:16;
1292 #else
1293 uint64_t pp_dis:16;
1294 uint64_t chip_id:8;
1295 uint64_t bist_dis:1;
1296 uint64_t rst_sht:1;
1297 uint64_t nocrypto:1;
1298 uint64_t nomul:1;
1299 uint64_t nodfa_cp2:1;
1300 uint64_t reserved_29_63:35;
1301 #endif
1302 } cn38xx;
1303 struct cvmx_mio_fus_dat2_cn50xx {
1304 #ifdef __BIG_ENDIAN_BITFIELD
1305 uint64_t reserved_34_63:30;
1306 uint64_t fus318:1;
1307 uint64_t raid_en:1;
1308 uint64_t reserved_30_31:2;
1309 uint64_t nokasu:1;
1310 uint64_t nodfa_cp2:1;
1311 uint64_t nomul:1;
1312 uint64_t nocrypto:1;
1313 uint64_t rst_sht:1;
1314 uint64_t bist_dis:1;
1315 uint64_t chip_id:8;
1316 uint64_t reserved_2_15:14;
1317 uint64_t pp_dis:2;
1318 #else
1319 uint64_t pp_dis:2;
1320 uint64_t reserved_2_15:14;
1321 uint64_t chip_id:8;
1322 uint64_t bist_dis:1;
1323 uint64_t rst_sht:1;
1324 uint64_t nocrypto:1;
1325 uint64_t nomul:1;
1326 uint64_t nodfa_cp2:1;
1327 uint64_t nokasu:1;
1328 uint64_t reserved_30_31:2;
1329 uint64_t raid_en:1;
1330 uint64_t fus318:1;
1331 uint64_t reserved_34_63:30;
1332 #endif
1333 } cn50xx;
1334 struct cvmx_mio_fus_dat2_cn52xx {
1335 #ifdef __BIG_ENDIAN_BITFIELD
1336 uint64_t reserved_34_63:30;
1337 uint64_t fus318:1;
1338 uint64_t raid_en:1;
1339 uint64_t reserved_30_31:2;
1340 uint64_t nokasu:1;
1341 uint64_t nodfa_cp2:1;
1342 uint64_t nomul:1;
1343 uint64_t nocrypto:1;
1344 uint64_t rst_sht:1;
1345 uint64_t bist_dis:1;
1346 uint64_t chip_id:8;
1347 uint64_t reserved_4_15:12;
1348 uint64_t pp_dis:4;
1349 #else
1350 uint64_t pp_dis:4;
1351 uint64_t reserved_4_15:12;
1352 uint64_t chip_id:8;
1353 uint64_t bist_dis:1;
1354 uint64_t rst_sht:1;
1355 uint64_t nocrypto:1;
1356 uint64_t nomul:1;
1357 uint64_t nodfa_cp2:1;
1358 uint64_t nokasu:1;
1359 uint64_t reserved_30_31:2;
1360 uint64_t raid_en:1;
1361 uint64_t fus318:1;
1362 uint64_t reserved_34_63:30;
1363 #endif
1364 } cn52xx;
1365 struct cvmx_mio_fus_dat2_cn56xx {
1366 #ifdef __BIG_ENDIAN_BITFIELD
1367 uint64_t reserved_34_63:30;
1368 uint64_t fus318:1;
1369 uint64_t raid_en:1;
1370 uint64_t reserved_30_31:2;
1371 uint64_t nokasu:1;
1372 uint64_t nodfa_cp2:1;
1373 uint64_t nomul:1;
1374 uint64_t nocrypto:1;
1375 uint64_t rst_sht:1;
1376 uint64_t bist_dis:1;
1377 uint64_t chip_id:8;
1378 uint64_t reserved_12_15:4;
1379 uint64_t pp_dis:12;
1380 #else
1381 uint64_t pp_dis:12;
1382 uint64_t reserved_12_15:4;
1383 uint64_t chip_id:8;
1384 uint64_t bist_dis:1;
1385 uint64_t rst_sht:1;
1386 uint64_t nocrypto:1;
1387 uint64_t nomul:1;
1388 uint64_t nodfa_cp2:1;
1389 uint64_t nokasu:1;
1390 uint64_t reserved_30_31:2;
1391 uint64_t raid_en:1;
1392 uint64_t fus318:1;
1393 uint64_t reserved_34_63:30;
1394 #endif
1395 } cn56xx;
1396 struct cvmx_mio_fus_dat2_cn58xx {
1397 #ifdef __BIG_ENDIAN_BITFIELD
1398 uint64_t reserved_30_63:34;
1399 uint64_t nokasu:1;
1400 uint64_t nodfa_cp2:1;
1401 uint64_t nomul:1;
1402 uint64_t nocrypto:1;
1403 uint64_t rst_sht:1;
1404 uint64_t bist_dis:1;
1405 uint64_t chip_id:8;
1406 uint64_t pp_dis:16;
1407 #else
1408 uint64_t pp_dis:16;
1409 uint64_t chip_id:8;
1410 uint64_t bist_dis:1;
1411 uint64_t rst_sht:1;
1412 uint64_t nocrypto:1;
1413 uint64_t nomul:1;
1414 uint64_t nodfa_cp2:1;
1415 uint64_t nokasu:1;
1416 uint64_t reserved_30_63:34;
1417 #endif
1418 } cn58xx;
1419 struct cvmx_mio_fus_dat2_cn61xx {
1420 #ifdef __BIG_ENDIAN_BITFIELD
1421 uint64_t reserved_48_63:16;
1422 uint64_t fus118:1;
1423 uint64_t rom_info:10;
1424 uint64_t power_limit:2;
1425 uint64_t dorm_crypto:1;
1426 uint64_t fus318:1;
1427 uint64_t raid_en:1;
1428 uint64_t reserved_29_31:3;
1429 uint64_t nodfa_cp2:1;
1430 uint64_t nomul:1;
1431 uint64_t nocrypto:1;
1432 uint64_t reserved_24_25:2;
1433 uint64_t chip_id:8;
1434 uint64_t reserved_4_15:12;
1435 uint64_t pp_dis:4;
1436 #else
1437 uint64_t pp_dis:4;
1438 uint64_t reserved_4_15:12;
1439 uint64_t chip_id:8;
1440 uint64_t reserved_24_25:2;
1441 uint64_t nocrypto:1;
1442 uint64_t nomul:1;
1443 uint64_t nodfa_cp2:1;
1444 uint64_t reserved_29_31:3;
1445 uint64_t raid_en:1;
1446 uint64_t fus318:1;
1447 uint64_t dorm_crypto:1;
1448 uint64_t power_limit:2;
1449 uint64_t rom_info:10;
1450 uint64_t fus118:1;
1451 uint64_t reserved_48_63:16;
1452 #endif
1453 } cn61xx;
1454 struct cvmx_mio_fus_dat2_cn63xx {
1455 #ifdef __BIG_ENDIAN_BITFIELD
1456 uint64_t reserved_35_63:29;
1457 uint64_t dorm_crypto:1;
1458 uint64_t fus318:1;
1459 uint64_t raid_en:1;
1460 uint64_t reserved_29_31:3;
1461 uint64_t nodfa_cp2:1;
1462 uint64_t nomul:1;
1463 uint64_t nocrypto:1;
1464 uint64_t reserved_24_25:2;
1465 uint64_t chip_id:8;
1466 uint64_t reserved_6_15:10;
1467 uint64_t pp_dis:6;
1468 #else
1469 uint64_t pp_dis:6;
1470 uint64_t reserved_6_15:10;
1471 uint64_t chip_id:8;
1472 uint64_t reserved_24_25:2;
1473 uint64_t nocrypto:1;
1474 uint64_t nomul:1;
1475 uint64_t nodfa_cp2:1;
1476 uint64_t reserved_29_31:3;
1477 uint64_t raid_en:1;
1478 uint64_t fus318:1;
1479 uint64_t dorm_crypto:1;
1480 uint64_t reserved_35_63:29;
1481 #endif
1482 } cn63xx;
1483 struct cvmx_mio_fus_dat2_cn66xx {
1484 #ifdef __BIG_ENDIAN_BITFIELD
1485 uint64_t reserved_48_63:16;
1486 uint64_t fus118:1;
1487 uint64_t rom_info:10;
1488 uint64_t power_limit:2;
1489 uint64_t dorm_crypto:1;
1490 uint64_t fus318:1;
1491 uint64_t raid_en:1;
1492 uint64_t reserved_29_31:3;
1493 uint64_t nodfa_cp2:1;
1494 uint64_t nomul:1;
1495 uint64_t nocrypto:1;
1496 uint64_t reserved_24_25:2;
1497 uint64_t chip_id:8;
1498 uint64_t reserved_10_15:6;
1499 uint64_t pp_dis:10;
1500 #else
1501 uint64_t pp_dis:10;
1502 uint64_t reserved_10_15:6;
1503 uint64_t chip_id:8;
1504 uint64_t reserved_24_25:2;
1505 uint64_t nocrypto:1;
1506 uint64_t nomul:1;
1507 uint64_t nodfa_cp2:1;
1508 uint64_t reserved_29_31:3;
1509 uint64_t raid_en:1;
1510 uint64_t fus318:1;
1511 uint64_t dorm_crypto:1;
1512 uint64_t power_limit:2;
1513 uint64_t rom_info:10;
1514 uint64_t fus118:1;
1515 uint64_t reserved_48_63:16;
1516 #endif
1517 } cn66xx;
1518 struct cvmx_mio_fus_dat2_cn68xx {
1519 #ifdef __BIG_ENDIAN_BITFIELD
1520 uint64_t reserved_37_63:27;
1521 uint64_t power_limit:2;
1522 uint64_t dorm_crypto:1;
1523 uint64_t fus318:1;
1524 uint64_t raid_en:1;
1525 uint64_t reserved_29_31:3;
1526 uint64_t nodfa_cp2:1;
1527 uint64_t nomul:1;
1528 uint64_t nocrypto:1;
1529 uint64_t reserved_24_25:2;
1530 uint64_t chip_id:8;
1531 uint64_t reserved_0_15:16;
1532 #else
1533 uint64_t reserved_0_15:16;
1534 uint64_t chip_id:8;
1535 uint64_t reserved_24_25:2;
1536 uint64_t nocrypto:1;
1537 uint64_t nomul:1;
1538 uint64_t nodfa_cp2:1;
1539 uint64_t reserved_29_31:3;
1540 uint64_t raid_en:1;
1541 uint64_t fus318:1;
1542 uint64_t dorm_crypto:1;
1543 uint64_t power_limit:2;
1544 uint64_t reserved_37_63:27;
1545 #endif
1546 } cn68xx;
1547 struct cvmx_mio_fus_dat2_cn70xx {
1548 #ifdef __BIG_ENDIAN_BITFIELD
1549 uint64_t reserved_48_63:16;
1550 uint64_t fus118:1;
1551 uint64_t rom_info:10;
1552 uint64_t power_limit:2;
1553 uint64_t dorm_crypto:1;
1554 uint64_t fus318:1;
1555 uint64_t raid_en:1;
1556 uint64_t reserved_31_29:3;
1557 uint64_t nodfa_cp2:1;
1558 uint64_t nomul:1;
1559 uint64_t nocrypto:1;
1560 uint64_t reserved_25_24:2;
1561 uint64_t chip_id:8;
1562 uint64_t reserved_15_0:16;
1563 #else
1564 uint64_t reserved_15_0:16;
1565 uint64_t chip_id:8;
1566 uint64_t reserved_25_24:2;
1567 uint64_t nocrypto:1;
1568 uint64_t nomul:1;
1569 uint64_t nodfa_cp2:1;
1570 uint64_t reserved_31_29:3;
1571 uint64_t raid_en:1;
1572 uint64_t fus318:1;
1573 uint64_t dorm_crypto:1;
1574 uint64_t power_limit:2;
1575 uint64_t rom_info:10;
1576 uint64_t fus118:1;
1577 uint64_t reserved_48_63:16;
1578 #endif
1579 } cn70xx;
1580 struct cvmx_mio_fus_dat2_cn73xx {
1581 #ifdef __BIG_ENDIAN_BITFIELD
1582 uint64_t reserved_59_63:5;
1583 uint64_t run_platform:3;
1584 uint64_t gbl_pwr_throttle:8;
1585 uint64_t fus118:1;
1586 uint64_t rom_info:10;
1587 uint64_t power_limit:2;
1588 uint64_t dorm_crypto:1;
1589 uint64_t fus318:1;
1590 uint64_t raid_en:1;
1591 uint64_t reserved_31_29:3;
1592 uint64_t nodfa_cp2:1;
1593 uint64_t nomul:1;
1594 uint64_t nocrypto:1;
1595 uint64_t reserved_25_24:2;
1596 uint64_t chip_id:8;
1597 uint64_t reserved_15_0:16;
1598 #else
1599 uint64_t reserved_15_0:16;
1600 uint64_t chip_id:8;
1601 uint64_t reserved_25_24:2;
1602 uint64_t nocrypto:1;
1603 uint64_t nomul:1;
1604 uint64_t nodfa_cp2:1;
1605 uint64_t reserved_31_29:3;
1606 uint64_t raid_en:1;
1607 uint64_t fus318:1;
1608 uint64_t dorm_crypto:1;
1609 uint64_t power_limit:2;
1610 uint64_t rom_info:10;
1611 uint64_t fus118:1;
1612 uint64_t gbl_pwr_throttle:8;
1613 uint64_t run_platform:3;
1614 uint64_t reserved_59_63:5;
1615 #endif
1616 } cn73xx;
1617 struct cvmx_mio_fus_dat2_cn78xx {
1618 #ifdef __BIG_ENDIAN_BITFIELD
1619 uint64_t reserved_59_63:5;
1620 uint64_t run_platform:3;
1621 uint64_t reserved_48_55:8;
1622 uint64_t fus118:1;
1623 uint64_t rom_info:10;
1624 uint64_t power_limit:2;
1625 uint64_t dorm_crypto:1;
1626 uint64_t fus318:1;
1627 uint64_t raid_en:1;
1628 uint64_t reserved_31_29:3;
1629 uint64_t nodfa_cp2:1;
1630 uint64_t nomul:1;
1631 uint64_t nocrypto:1;
1632 uint64_t reserved_25_24:2;
1633 uint64_t chip_id:8;
1634 uint64_t reserved_0_15:16;
1635 #else
1636 uint64_t reserved_0_15:16;
1637 uint64_t chip_id:8;
1638 uint64_t reserved_25_24:2;
1639 uint64_t nocrypto:1;
1640 uint64_t nomul:1;
1641 uint64_t nodfa_cp2:1;
1642 uint64_t reserved_31_29:3;
1643 uint64_t raid_en:1;
1644 uint64_t fus318:1;
1645 uint64_t dorm_crypto:1;
1646 uint64_t power_limit:2;
1647 uint64_t rom_info:10;
1648 uint64_t fus118:1;
1649 uint64_t reserved_48_55:8;
1650 uint64_t run_platform:3;
1651 uint64_t reserved_59_63:5;
1652 #endif
1653 } cn78xx;
1654 struct cvmx_mio_fus_dat2_cn78xxp2 {
1655 #ifdef __BIG_ENDIAN_BITFIELD
1656 uint64_t reserved_59_63:5;
1657 uint64_t run_platform:3;
1658 uint64_t gbl_pwr_throttle:8;
1659 uint64_t fus118:1;
1660 uint64_t rom_info:10;
1661 uint64_t power_limit:2;
1662 uint64_t dorm_crypto:1;
1663 uint64_t fus318:1;
1664 uint64_t raid_en:1;
1665 uint64_t reserved_31_29:3;
1666 uint64_t nodfa_cp2:1;
1667 uint64_t nomul:1;
1668 uint64_t nocrypto:1;
1669 uint64_t reserved_25_24:2;
1670 uint64_t chip_id:8;
1671 uint64_t reserved_0_15:16;
1672 #else
1673 uint64_t reserved_0_15:16;
1674 uint64_t chip_id:8;
1675 uint64_t reserved_25_24:2;
1676 uint64_t nocrypto:1;
1677 uint64_t nomul:1;
1678 uint64_t nodfa_cp2:1;
1679 uint64_t reserved_31_29:3;
1680 uint64_t raid_en:1;
1681 uint64_t fus318:1;
1682 uint64_t dorm_crypto:1;
1683 uint64_t power_limit:2;
1684 uint64_t rom_info:10;
1685 uint64_t fus118:1;
1686 uint64_t gbl_pwr_throttle:8;
1687 uint64_t run_platform:3;
1688 uint64_t reserved_59_63:5;
1689 #endif
1690 } cn78xxp2;
1691 };
1692
1693 union cvmx_mio_fus_dat3 {
1694 uint64_t u64;
1695 struct cvmx_mio_fus_dat3_s {
1696 #ifdef __BIG_ENDIAN_BITFIELD
1697 uint64_t ema0:6;
1698 uint64_t pll_ctl:10;
1699 uint64_t dfa_info_dte:3;
1700 uint64_t dfa_info_clm:4;
1701 uint64_t pll_alt_matrix:1;
1702 uint64_t reserved_38_39:2;
1703 uint64_t efus_lck_rsv:1;
1704 uint64_t efus_lck_man:1;
1705 uint64_t pll_half_dis:1;
1706 uint64_t l2c_crip:3;
1707 uint64_t reserved_28_31:4;
1708 uint64_t efus_lck:1;
1709 uint64_t efus_ign:1;
1710 uint64_t nozip:1;
1711 uint64_t nodfa_dte:1;
1712 uint64_t reserved_0_23:24;
1713 #else
1714 uint64_t reserved_0_23:24;
1715 uint64_t nodfa_dte:1;
1716 uint64_t nozip:1;
1717 uint64_t efus_ign:1;
1718 uint64_t efus_lck:1;
1719 uint64_t reserved_28_31:4;
1720 uint64_t l2c_crip:3;
1721 uint64_t pll_half_dis:1;
1722 uint64_t efus_lck_man:1;
1723 uint64_t efus_lck_rsv:1;
1724 uint64_t reserved_38_39:2;
1725 uint64_t pll_alt_matrix:1;
1726 uint64_t dfa_info_clm:4;
1727 uint64_t dfa_info_dte:3;
1728 uint64_t pll_ctl:10;
1729 uint64_t ema0:6;
1730 #endif
1731 } s;
1732 struct cvmx_mio_fus_dat3_cn30xx {
1733 #ifdef __BIG_ENDIAN_BITFIELD
1734 uint64_t reserved_32_63:32;
1735 uint64_t pll_div4:1;
1736 uint64_t reserved_29_30:2;
1737 uint64_t bar2_en:1;
1738 uint64_t efus_lck:1;
1739 uint64_t efus_ign:1;
1740 uint64_t nozip:1;
1741 uint64_t nodfa_dte:1;
1742 uint64_t icache:24;
1743 #else
1744 uint64_t icache:24;
1745 uint64_t nodfa_dte:1;
1746 uint64_t nozip:1;
1747 uint64_t efus_ign:1;
1748 uint64_t efus_lck:1;
1749 uint64_t bar2_en:1;
1750 uint64_t reserved_29_30:2;
1751 uint64_t pll_div4:1;
1752 uint64_t reserved_32_63:32;
1753 #endif
1754 } cn30xx;
1755 struct cvmx_mio_fus_dat3_cn31xx {
1756 #ifdef __BIG_ENDIAN_BITFIELD
1757 uint64_t reserved_32_63:32;
1758 uint64_t pll_div4:1;
1759 uint64_t zip_crip:2;
1760 uint64_t bar2_en:1;
1761 uint64_t efus_lck:1;
1762 uint64_t efus_ign:1;
1763 uint64_t nozip:1;
1764 uint64_t nodfa_dte:1;
1765 uint64_t icache:24;
1766 #else
1767 uint64_t icache:24;
1768 uint64_t nodfa_dte:1;
1769 uint64_t nozip:1;
1770 uint64_t efus_ign:1;
1771 uint64_t efus_lck:1;
1772 uint64_t bar2_en:1;
1773 uint64_t zip_crip:2;
1774 uint64_t pll_div4:1;
1775 uint64_t reserved_32_63:32;
1776 #endif
1777 } cn31xx;
1778 struct cvmx_mio_fus_dat3_cn38xx {
1779 #ifdef __BIG_ENDIAN_BITFIELD
1780 uint64_t reserved_31_63:33;
1781 uint64_t zip_crip:2;
1782 uint64_t bar2_en:1;
1783 uint64_t efus_lck:1;
1784 uint64_t efus_ign:1;
1785 uint64_t nozip:1;
1786 uint64_t nodfa_dte:1;
1787 uint64_t icache:24;
1788 #else
1789 uint64_t icache:24;
1790 uint64_t nodfa_dte:1;
1791 uint64_t nozip:1;
1792 uint64_t efus_ign:1;
1793 uint64_t efus_lck:1;
1794 uint64_t bar2_en:1;
1795 uint64_t zip_crip:2;
1796 uint64_t reserved_31_63:33;
1797 #endif
1798 } cn38xx;
1799 struct cvmx_mio_fus_dat3_cn38xxp2 {
1800 #ifdef __BIG_ENDIAN_BITFIELD
1801 uint64_t reserved_29_63:35;
1802 uint64_t bar2_en:1;
1803 uint64_t efus_lck:1;
1804 uint64_t efus_ign:1;
1805 uint64_t nozip:1;
1806 uint64_t nodfa_dte:1;
1807 uint64_t icache:24;
1808 #else
1809 uint64_t icache:24;
1810 uint64_t nodfa_dte:1;
1811 uint64_t nozip:1;
1812 uint64_t efus_ign:1;
1813 uint64_t efus_lck:1;
1814 uint64_t bar2_en:1;
1815 uint64_t reserved_29_63:35;
1816 #endif
1817 } cn38xxp2;
1818 struct cvmx_mio_fus_dat3_cn61xx {
1819 #ifdef __BIG_ENDIAN_BITFIELD
1820 uint64_t reserved_58_63:6;
1821 uint64_t pll_ctl:10;
1822 uint64_t dfa_info_dte:3;
1823 uint64_t dfa_info_clm:4;
1824 uint64_t reserved_40_40:1;
1825 uint64_t ema:2;
1826 uint64_t efus_lck_rsv:1;
1827 uint64_t efus_lck_man:1;
1828 uint64_t pll_half_dis:1;
1829 uint64_t l2c_crip:3;
1830 uint64_t reserved_31_31:1;
1831 uint64_t zip_info:2;
1832 uint64_t bar2_en:1;
1833 uint64_t efus_lck:1;
1834 uint64_t efus_ign:1;
1835 uint64_t nozip:1;
1836 uint64_t nodfa_dte:1;
1837 uint64_t reserved_0_23:24;
1838 #else
1839 uint64_t reserved_0_23:24;
1840 uint64_t nodfa_dte:1;
1841 uint64_t nozip:1;
1842 uint64_t efus_ign:1;
1843 uint64_t efus_lck:1;
1844 uint64_t bar2_en:1;
1845 uint64_t zip_info:2;
1846 uint64_t reserved_31_31:1;
1847 uint64_t l2c_crip:3;
1848 uint64_t pll_half_dis:1;
1849 uint64_t efus_lck_man:1;
1850 uint64_t efus_lck_rsv:1;
1851 uint64_t ema:2;
1852 uint64_t reserved_40_40:1;
1853 uint64_t dfa_info_clm:4;
1854 uint64_t dfa_info_dte:3;
1855 uint64_t pll_ctl:10;
1856 uint64_t reserved_58_63:6;
1857 #endif
1858 } cn61xx;
1859 struct cvmx_mio_fus_dat3_cn70xx {
1860 #ifdef __BIG_ENDIAN_BITFIELD
1861 uint64_t ema0:6;
1862 uint64_t pll_ctl:10;
1863 uint64_t dfa_info_dte:3;
1864 uint64_t dfa_info_clm:4;
1865 uint64_t pll_alt_matrix:1;
1866 uint64_t pll_bwadj_denom:2;
1867 uint64_t efus_lck_rsv:1;
1868 uint64_t efus_lck_man:1;
1869 uint64_t pll_half_dis:1;
1870 uint64_t l2c_crip:3;
1871 uint64_t use_int_refclk:1;
1872 uint64_t zip_info:2;
1873 uint64_t bar2_sz_conf:1;
1874 uint64_t efus_lck:1;
1875 uint64_t efus_ign:1;
1876 uint64_t nozip:1;
1877 uint64_t nodfa_dte:1;
1878 uint64_t ema1:6;
1879 uint64_t reserved_0_17:18;
1880 #else
1881 uint64_t reserved_0_17:18;
1882 uint64_t ema1:6;
1883 uint64_t nodfa_dte:1;
1884 uint64_t nozip:1;
1885 uint64_t efus_ign:1;
1886 uint64_t efus_lck:1;
1887 uint64_t bar2_sz_conf:1;
1888 uint64_t zip_info:2;
1889 uint64_t use_int_refclk:1;
1890 uint64_t l2c_crip:3;
1891 uint64_t pll_half_dis:1;
1892 uint64_t efus_lck_man:1;
1893 uint64_t efus_lck_rsv:1;
1894 uint64_t pll_bwadj_denom:2;
1895 uint64_t pll_alt_matrix:1;
1896 uint64_t dfa_info_clm:4;
1897 uint64_t dfa_info_dte:3;
1898 uint64_t pll_ctl:10;
1899 uint64_t ema0:6;
1900 #endif
1901 } cn70xx;
1902 struct cvmx_mio_fus_dat3_cn70xxp1 {
1903 #ifdef __BIG_ENDIAN_BITFIELD
1904 uint64_t ema0:6;
1905 uint64_t pll_ctl:10;
1906 uint64_t dfa_info_dte:3;
1907 uint64_t dfa_info_clm:4;
1908 uint64_t reserved_38_40:3;
1909 uint64_t efus_lck_rsv:1;
1910 uint64_t efus_lck_man:1;
1911 uint64_t pll_half_dis:1;
1912 uint64_t l2c_crip:3;
1913 uint64_t reserved_31_31:1;
1914 uint64_t zip_info:2;
1915 uint64_t bar2_sz_conf:1;
1916 uint64_t efus_lck:1;
1917 uint64_t efus_ign:1;
1918 uint64_t nozip:1;
1919 uint64_t nodfa_dte:1;
1920 uint64_t ema1:6;
1921 uint64_t reserved_0_17:18;
1922 #else
1923 uint64_t reserved_0_17:18;
1924 uint64_t ema1:6;
1925 uint64_t nodfa_dte:1;
1926 uint64_t nozip:1;
1927 uint64_t efus_ign:1;
1928 uint64_t efus_lck:1;
1929 uint64_t bar2_sz_conf:1;
1930 uint64_t zip_info:2;
1931 uint64_t reserved_31_31:1;
1932 uint64_t l2c_crip:3;
1933 uint64_t pll_half_dis:1;
1934 uint64_t efus_lck_man:1;
1935 uint64_t efus_lck_rsv:1;
1936 uint64_t reserved_38_40:3;
1937 uint64_t dfa_info_clm:4;
1938 uint64_t dfa_info_dte:3;
1939 uint64_t pll_ctl:10;
1940 uint64_t ema0:6;
1941 #endif
1942 } cn70xxp1;
1943 struct cvmx_mio_fus_dat3_cn73xx {
1944 #ifdef __BIG_ENDIAN_BITFIELD
1945 uint64_t ema0:6;
1946 uint64_t pll_ctl:10;
1947 uint64_t dfa_info_dte:3;
1948 uint64_t dfa_info_clm:4;
1949 uint64_t pll_alt_matrix:1;
1950 uint64_t pll_bwadj_denom:2;
1951 uint64_t efus_lck_rsv:1;
1952 uint64_t efus_lck_man:1;
1953 uint64_t pll_half_dis:1;
1954 uint64_t l2c_crip:3;
1955 uint64_t use_int_refclk:1;
1956 uint64_t zip_info:2;
1957 uint64_t bar2_sz_conf:1;
1958 uint64_t efus_lck:1;
1959 uint64_t efus_ign:1;
1960 uint64_t nozip:1;
1961 uint64_t nodfa_dte:1;
1962 uint64_t ema1:6;
1963 uint64_t nohna_dte:1;
1964 uint64_t hna_info_dte:3;
1965 uint64_t hna_info_clm:4;
1966 uint64_t reserved_9_9:1;
1967 uint64_t core_pll_mul:5;
1968 uint64_t pnr_pll_mul:4;
1969 #else
1970 uint64_t pnr_pll_mul:4;
1971 uint64_t core_pll_mul:5;
1972 uint64_t reserved_9_9:1;
1973 uint64_t hna_info_clm:4;
1974 uint64_t hna_info_dte:3;
1975 uint64_t nohna_dte:1;
1976 uint64_t ema1:6;
1977 uint64_t nodfa_dte:1;
1978 uint64_t nozip:1;
1979 uint64_t efus_ign:1;
1980 uint64_t efus_lck:1;
1981 uint64_t bar2_sz_conf:1;
1982 uint64_t zip_info:2;
1983 uint64_t use_int_refclk:1;
1984 uint64_t l2c_crip:3;
1985 uint64_t pll_half_dis:1;
1986 uint64_t efus_lck_man:1;
1987 uint64_t efus_lck_rsv:1;
1988 uint64_t pll_bwadj_denom:2;
1989 uint64_t pll_alt_matrix:1;
1990 uint64_t dfa_info_clm:4;
1991 uint64_t dfa_info_dte:3;
1992 uint64_t pll_ctl:10;
1993 uint64_t ema0:6;
1994 #endif
1995 } cn73xx;
1996 struct cvmx_mio_fus_dat3_cn78xx {
1997 #ifdef __BIG_ENDIAN_BITFIELD
1998 uint64_t ema0:6;
1999 uint64_t pll_ctl:10;
2000 uint64_t dfa_info_dte:3;
2001 uint64_t dfa_info_clm:4;
2002 uint64_t reserved_38_40:3;
2003 uint64_t efus_lck_rsv:1;
2004 uint64_t efus_lck_man:1;
2005 uint64_t pll_half_dis:1;
2006 uint64_t l2c_crip:3;
2007 uint64_t reserved_31_31:1;
2008 uint64_t zip_info:2;
2009 uint64_t bar2_sz_conf:1;
2010 uint64_t efus_lck:1;
2011 uint64_t efus_ign:1;
2012 uint64_t nozip:1;
2013 uint64_t nodfa_dte:1;
2014 uint64_t ema1:6;
2015 uint64_t nohna_dte:1;
2016 uint64_t hna_info_dte:3;
2017 uint64_t hna_info_clm:4;
2018 uint64_t reserved_0_9:10;
2019 #else
2020 uint64_t reserved_0_9:10;
2021 uint64_t hna_info_clm:4;
2022 uint64_t hna_info_dte:3;
2023 uint64_t nohna_dte:1;
2024 uint64_t ema1:6;
2025 uint64_t nodfa_dte:1;
2026 uint64_t nozip:1;
2027 uint64_t efus_ign:1;
2028 uint64_t efus_lck:1;
2029 uint64_t bar2_sz_conf:1;
2030 uint64_t zip_info:2;
2031 uint64_t reserved_31_31:1;
2032 uint64_t l2c_crip:3;
2033 uint64_t pll_half_dis:1;
2034 uint64_t efus_lck_man:1;
2035 uint64_t efus_lck_rsv:1;
2036 uint64_t reserved_38_40:3;
2037 uint64_t dfa_info_clm:4;
2038 uint64_t dfa_info_dte:3;
2039 uint64_t pll_ctl:10;
2040 uint64_t ema0:6;
2041 #endif
2042 } cn78xx;
2043 struct cvmx_mio_fus_dat3_cnf75xx {
2044 #ifdef __BIG_ENDIAN_BITFIELD
2045 uint64_t ema0:6;
2046 uint64_t pll_ctl:10;
2047 uint64_t dfa_info_dte:3;
2048 uint64_t dfa_info_clm:4;
2049 uint64_t pll_alt_matrix:1;
2050 uint64_t pll_bwadj_denom:2;
2051 uint64_t efus_lck_rsv:1;
2052 uint64_t efus_lck_man:1;
2053 uint64_t pll_half_dis:1;
2054 uint64_t l2c_crip:3;
2055 uint64_t use_int_refclk:1;
2056 uint64_t zip_info:2;
2057 uint64_t bar2_sz_conf:1;
2058 uint64_t efus_lck:1;
2059 uint64_t efus_ign:1;
2060 uint64_t nozip:1;
2061 uint64_t nodfa_dte:1;
2062 uint64_t ema1:6;
2063 uint64_t reserved_9_17:9;
2064 uint64_t core_pll_mul:5;
2065 uint64_t pnr_pll_mul:4;
2066 #else
2067 uint64_t pnr_pll_mul:4;
2068 uint64_t core_pll_mul:5;
2069 uint64_t reserved_9_17:9;
2070 uint64_t ema1:6;
2071 uint64_t nodfa_dte:1;
2072 uint64_t nozip:1;
2073 uint64_t efus_ign:1;
2074 uint64_t efus_lck:1;
2075 uint64_t bar2_sz_conf:1;
2076 uint64_t zip_info:2;
2077 uint64_t use_int_refclk:1;
2078 uint64_t l2c_crip:3;
2079 uint64_t pll_half_dis:1;
2080 uint64_t efus_lck_man:1;
2081 uint64_t efus_lck_rsv:1;
2082 uint64_t pll_bwadj_denom:2;
2083 uint64_t pll_alt_matrix:1;
2084 uint64_t dfa_info_clm:4;
2085 uint64_t dfa_info_dte:3;
2086 uint64_t pll_ctl:10;
2087 uint64_t ema0:6;
2088 #endif
2089 } cnf75xx;
2090 };
2091
2092 union cvmx_mio_fus_ema {
2093 uint64_t u64;
2094 struct cvmx_mio_fus_ema_s {
2095 #ifdef __BIG_ENDIAN_BITFIELD
2096 uint64_t reserved_7_63:57;
2097 uint64_t eff_ema:3;
2098 uint64_t reserved_3_3:1;
2099 uint64_t ema:3;
2100 #else
2101 uint64_t ema:3;
2102 uint64_t reserved_3_3:1;
2103 uint64_t eff_ema:3;
2104 uint64_t reserved_7_63:57;
2105 #endif
2106 } s;
2107 struct cvmx_mio_fus_ema_cn58xx {
2108 #ifdef __BIG_ENDIAN_BITFIELD
2109 uint64_t reserved_2_63:62;
2110 uint64_t ema:2;
2111 #else
2112 uint64_t ema:2;
2113 uint64_t reserved_2_63:62;
2114 #endif
2115 } cn58xx;
2116 };
2117
2118 union cvmx_mio_fus_pdf {
2119 uint64_t u64;
2120 struct cvmx_mio_fus_pdf_s {
2121 #ifdef __BIG_ENDIAN_BITFIELD
2122 uint64_t pdf:64;
2123 #else
2124 uint64_t pdf:64;
2125 #endif
2126 } s;
2127 };
2128
2129 union cvmx_mio_fus_pll {
2130 uint64_t u64;
2131 struct cvmx_mio_fus_pll_s {
2132 #ifdef __BIG_ENDIAN_BITFIELD
2133 uint64_t reserved_48_63:16;
2134 uint64_t rclk_align_r:8;
2135 uint64_t rclk_align_l:8;
2136 uint64_t reserved_8_31:24;
2137 uint64_t c_cout_rst:1;
2138 uint64_t c_cout_sel:2;
2139 uint64_t pnr_cout_rst:1;
2140 uint64_t pnr_cout_sel:2;
2141 uint64_t rfslip:1;
2142 uint64_t fbslip:1;
2143 #else
2144 uint64_t fbslip:1;
2145 uint64_t rfslip:1;
2146 uint64_t pnr_cout_sel:2;
2147 uint64_t pnr_cout_rst:1;
2148 uint64_t c_cout_sel:2;
2149 uint64_t c_cout_rst:1;
2150 uint64_t reserved_8_31:24;
2151 uint64_t rclk_align_l:8;
2152 uint64_t rclk_align_r:8;
2153 uint64_t reserved_48_63:16;
2154 #endif
2155 } s;
2156 struct cvmx_mio_fus_pll_cn50xx {
2157 #ifdef __BIG_ENDIAN_BITFIELD
2158 uint64_t reserved_2_63:62;
2159 uint64_t rfslip:1;
2160 uint64_t fbslip:1;
2161 #else
2162 uint64_t fbslip:1;
2163 uint64_t rfslip:1;
2164 uint64_t reserved_2_63:62;
2165 #endif
2166 } cn50xx;
2167 struct cvmx_mio_fus_pll_cn61xx {
2168 #ifdef __BIG_ENDIAN_BITFIELD
2169 uint64_t reserved_8_63:56;
2170 uint64_t c_cout_rst:1;
2171 uint64_t c_cout_sel:2;
2172 uint64_t pnr_cout_rst:1;
2173 uint64_t pnr_cout_sel:2;
2174 uint64_t rfslip:1;
2175 uint64_t fbslip:1;
2176 #else
2177 uint64_t fbslip:1;
2178 uint64_t rfslip:1;
2179 uint64_t pnr_cout_sel:2;
2180 uint64_t pnr_cout_rst:1;
2181 uint64_t c_cout_sel:2;
2182 uint64_t c_cout_rst:1;
2183 uint64_t reserved_8_63:56;
2184 #endif
2185 } cn61xx;
2186 };
2187
2188 union cvmx_mio_fus_prog {
2189 uint64_t u64;
2190 struct cvmx_mio_fus_prog_s {
2191 #ifdef __BIG_ENDIAN_BITFIELD
2192 uint64_t reserved_2_63:62;
2193 uint64_t soft:1;
2194 uint64_t prog:1;
2195 #else
2196 uint64_t prog:1;
2197 uint64_t soft:1;
2198 uint64_t reserved_2_63:62;
2199 #endif
2200 } s;
2201 struct cvmx_mio_fus_prog_cn30xx {
2202 #ifdef __BIG_ENDIAN_BITFIELD
2203 uint64_t reserved_1_63:63;
2204 uint64_t prog:1;
2205 #else
2206 uint64_t prog:1;
2207 uint64_t reserved_1_63:63;
2208 #endif
2209 } cn30xx;
2210 };
2211
2212 union cvmx_mio_fus_prog_times {
2213 uint64_t u64;
2214 struct cvmx_mio_fus_prog_times_s {
2215 #ifdef __BIG_ENDIAN_BITFIELD
2216 uint64_t reserved_35_63:29;
2217 uint64_t vgate_pin:1;
2218 uint64_t fsrc_pin:1;
2219 uint64_t prog_pin:1;
2220 uint64_t reserved_6_31:26;
2221 uint64_t setup:6;
2222 #else
2223 uint64_t setup:6;
2224 uint64_t reserved_6_31:26;
2225 uint64_t prog_pin:1;
2226 uint64_t fsrc_pin:1;
2227 uint64_t vgate_pin:1;
2228 uint64_t reserved_35_63:29;
2229 #endif
2230 } s;
2231 struct cvmx_mio_fus_prog_times_cn50xx {
2232 #ifdef __BIG_ENDIAN_BITFIELD
2233 uint64_t reserved_33_63:31;
2234 uint64_t prog_pin:1;
2235 uint64_t out:8;
2236 uint64_t sclk_lo:4;
2237 uint64_t sclk_hi:12;
2238 uint64_t setup:8;
2239 #else
2240 uint64_t setup:8;
2241 uint64_t sclk_hi:12;
2242 uint64_t sclk_lo:4;
2243 uint64_t out:8;
2244 uint64_t prog_pin:1;
2245 uint64_t reserved_33_63:31;
2246 #endif
2247 } cn50xx;
2248 struct cvmx_mio_fus_prog_times_cn61xx {
2249 #ifdef __BIG_ENDIAN_BITFIELD
2250 uint64_t reserved_35_63:29;
2251 uint64_t vgate_pin:1;
2252 uint64_t fsrc_pin:1;
2253 uint64_t prog_pin:1;
2254 uint64_t out:7;
2255 uint64_t sclk_lo:4;
2256 uint64_t sclk_hi:15;
2257 uint64_t setup:6;
2258 #else
2259 uint64_t setup:6;
2260 uint64_t sclk_hi:15;
2261 uint64_t sclk_lo:4;
2262 uint64_t out:7;
2263 uint64_t prog_pin:1;
2264 uint64_t fsrc_pin:1;
2265 uint64_t vgate_pin:1;
2266 uint64_t reserved_35_63:29;
2267 #endif
2268 } cn61xx;
2269 };
2270
2271 union cvmx_mio_fus_rcmd {
2272 uint64_t u64;
2273 struct cvmx_mio_fus_rcmd_s {
2274 #ifdef __BIG_ENDIAN_BITFIELD
2275 uint64_t reserved_24_63:40;
2276 uint64_t dat:8;
2277 uint64_t reserved_13_15:3;
2278 uint64_t pend:1;
2279 uint64_t reserved_9_11:3;
2280 uint64_t efuse:1;
2281 uint64_t addr:8;
2282 #else
2283 uint64_t addr:8;
2284 uint64_t efuse:1;
2285 uint64_t reserved_9_11:3;
2286 uint64_t pend:1;
2287 uint64_t reserved_13_15:3;
2288 uint64_t dat:8;
2289 uint64_t reserved_24_63:40;
2290 #endif
2291 } s;
2292 struct cvmx_mio_fus_rcmd_cn30xx {
2293 #ifdef __BIG_ENDIAN_BITFIELD
2294 uint64_t reserved_24_63:40;
2295 uint64_t dat:8;
2296 uint64_t reserved_13_15:3;
2297 uint64_t pend:1;
2298 uint64_t reserved_9_11:3;
2299 uint64_t efuse:1;
2300 uint64_t reserved_7_7:1;
2301 uint64_t addr:7;
2302 #else
2303 uint64_t addr:7;
2304 uint64_t reserved_7_7:1;
2305 uint64_t efuse:1;
2306 uint64_t reserved_9_11:3;
2307 uint64_t pend:1;
2308 uint64_t reserved_13_15:3;
2309 uint64_t dat:8;
2310 uint64_t reserved_24_63:40;
2311 #endif
2312 } cn30xx;
2313 };
2314
2315 union cvmx_mio_fus_read_times {
2316 uint64_t u64;
2317 struct cvmx_mio_fus_read_times_s {
2318 #ifdef __BIG_ENDIAN_BITFIELD
2319 uint64_t reserved_26_63:38;
2320 uint64_t sch:4;
2321 uint64_t fsh:4;
2322 uint64_t prh:4;
2323 uint64_t sdh:4;
2324 uint64_t setup:10;
2325 #else
2326 uint64_t setup:10;
2327 uint64_t sdh:4;
2328 uint64_t prh:4;
2329 uint64_t fsh:4;
2330 uint64_t sch:4;
2331 uint64_t reserved_26_63:38;
2332 #endif
2333 } s;
2334 };
2335
2336 union cvmx_mio_fus_repair_res0 {
2337 uint64_t u64;
2338 struct cvmx_mio_fus_repair_res0_s {
2339 #ifdef __BIG_ENDIAN_BITFIELD
2340 uint64_t reserved_55_63:9;
2341 uint64_t too_many:1;
2342 uint64_t repair2:18;
2343 uint64_t repair1:18;
2344 uint64_t repair0:18;
2345 #else
2346 uint64_t repair0:18;
2347 uint64_t repair1:18;
2348 uint64_t repair2:18;
2349 uint64_t too_many:1;
2350 uint64_t reserved_55_63:9;
2351 #endif
2352 } s;
2353 };
2354
2355 union cvmx_mio_fus_repair_res1 {
2356 uint64_t u64;
2357 struct cvmx_mio_fus_repair_res1_s {
2358 #ifdef __BIG_ENDIAN_BITFIELD
2359 uint64_t reserved_54_63:10;
2360 uint64_t repair5:18;
2361 uint64_t repair4:18;
2362 uint64_t repair3:18;
2363 #else
2364 uint64_t repair3:18;
2365 uint64_t repair4:18;
2366 uint64_t repair5:18;
2367 uint64_t reserved_54_63:10;
2368 #endif
2369 } s;
2370 };
2371
2372 union cvmx_mio_fus_repair_res2 {
2373 uint64_t u64;
2374 struct cvmx_mio_fus_repair_res2_s {
2375 #ifdef __BIG_ENDIAN_BITFIELD
2376 uint64_t reserved_18_63:46;
2377 uint64_t repair6:18;
2378 #else
2379 uint64_t repair6:18;
2380 uint64_t reserved_18_63:46;
2381 #endif
2382 } s;
2383 };
2384
2385 union cvmx_mio_fus_spr_repair_res {
2386 uint64_t u64;
2387 struct cvmx_mio_fus_spr_repair_res_s {
2388 #ifdef __BIG_ENDIAN_BITFIELD
2389 uint64_t reserved_42_63:22;
2390 uint64_t repair2:14;
2391 uint64_t repair1:14;
2392 uint64_t repair0:14;
2393 #else
2394 uint64_t repair0:14;
2395 uint64_t repair1:14;
2396 uint64_t repair2:14;
2397 uint64_t reserved_42_63:22;
2398 #endif
2399 } s;
2400 };
2401
2402 union cvmx_mio_fus_spr_repair_sum {
2403 uint64_t u64;
2404 struct cvmx_mio_fus_spr_repair_sum_s {
2405 #ifdef __BIG_ENDIAN_BITFIELD
2406 uint64_t reserved_1_63:63;
2407 uint64_t too_many:1;
2408 #else
2409 uint64_t too_many:1;
2410 uint64_t reserved_1_63:63;
2411 #endif
2412 } s;
2413 };
2414
2415 union cvmx_mio_fus_tgg {
2416 uint64_t u64;
2417 struct cvmx_mio_fus_tgg_s {
2418 #ifdef __BIG_ENDIAN_BITFIELD
2419 uint64_t val:1;
2420 uint64_t dat:63;
2421 #else
2422 uint64_t dat:63;
2423 uint64_t val:1;
2424 #endif
2425 } s;
2426 };
2427
2428 union cvmx_mio_fus_unlock {
2429 uint64_t u64;
2430 struct cvmx_mio_fus_unlock_s {
2431 #ifdef __BIG_ENDIAN_BITFIELD
2432 uint64_t reserved_24_63:40;
2433 uint64_t key:24;
2434 #else
2435 uint64_t key:24;
2436 uint64_t reserved_24_63:40;
2437 #endif
2438 } s;
2439 };
2440
2441 union cvmx_mio_fus_wadr {
2442 uint64_t u64;
2443 struct cvmx_mio_fus_wadr_s {
2444 #ifdef __BIG_ENDIAN_BITFIELD
2445 uint64_t reserved_10_63:54;
2446 uint64_t addr:10;
2447 #else
2448 uint64_t addr:10;
2449 uint64_t reserved_10_63:54;
2450 #endif
2451 } s;
2452 struct cvmx_mio_fus_wadr_cn50xx {
2453 #ifdef __BIG_ENDIAN_BITFIELD
2454 uint64_t reserved_2_63:62;
2455 uint64_t addr:2;
2456 #else
2457 uint64_t addr:2;
2458 uint64_t reserved_2_63:62;
2459 #endif
2460 } cn50xx;
2461 struct cvmx_mio_fus_wadr_cn52xx {
2462 #ifdef __BIG_ENDIAN_BITFIELD
2463 uint64_t reserved_3_63:61;
2464 uint64_t addr:3;
2465 #else
2466 uint64_t addr:3;
2467 uint64_t reserved_3_63:61;
2468 #endif
2469 } cn52xx;
2470 struct cvmx_mio_fus_wadr_cn61xx {
2471 #ifdef __BIG_ENDIAN_BITFIELD
2472 uint64_t reserved_4_63:60;
2473 uint64_t addr:4;
2474 #else
2475 uint64_t addr:4;
2476 uint64_t reserved_4_63:60;
2477 #endif
2478 } cn61xx;
2479 };
2480
2481 union cvmx_mio_gpio_comp {
2482 uint64_t u64;
2483 struct cvmx_mio_gpio_comp_s {
2484 #ifdef __BIG_ENDIAN_BITFIELD
2485 uint64_t reserved_12_63:52;
2486 uint64_t pctl:6;
2487 uint64_t nctl:6;
2488 #else
2489 uint64_t nctl:6;
2490 uint64_t pctl:6;
2491 uint64_t reserved_12_63:52;
2492 #endif
2493 } s;
2494 };
2495
2496 union cvmx_mio_ndf_dma_cfg {
2497 uint64_t u64;
2498 struct cvmx_mio_ndf_dma_cfg_s {
2499 #ifdef __BIG_ENDIAN_BITFIELD
2500 uint64_t en:1;
2501 uint64_t rw:1;
2502 uint64_t clr:1;
2503 uint64_t reserved_60_60:1;
2504 uint64_t swap32:1;
2505 uint64_t swap16:1;
2506 uint64_t swap8:1;
2507 uint64_t endian:1;
2508 uint64_t size:20;
2509 uint64_t adr:36;
2510 #else
2511 uint64_t adr:36;
2512 uint64_t size:20;
2513 uint64_t endian:1;
2514 uint64_t swap8:1;
2515 uint64_t swap16:1;
2516 uint64_t swap32:1;
2517 uint64_t reserved_60_60:1;
2518 uint64_t clr:1;
2519 uint64_t rw:1;
2520 uint64_t en:1;
2521 #endif
2522 } s;
2523 };
2524
2525 union cvmx_mio_ndf_dma_int {
2526 uint64_t u64;
2527 struct cvmx_mio_ndf_dma_int_s {
2528 #ifdef __BIG_ENDIAN_BITFIELD
2529 uint64_t reserved_1_63:63;
2530 uint64_t done:1;
2531 #else
2532 uint64_t done:1;
2533 uint64_t reserved_1_63:63;
2534 #endif
2535 } s;
2536 };
2537
2538 union cvmx_mio_ndf_dma_int_en {
2539 uint64_t u64;
2540 struct cvmx_mio_ndf_dma_int_en_s {
2541 #ifdef __BIG_ENDIAN_BITFIELD
2542 uint64_t reserved_1_63:63;
2543 uint64_t done:1;
2544 #else
2545 uint64_t done:1;
2546 uint64_t reserved_1_63:63;
2547 #endif
2548 } s;
2549 };
2550
2551 union cvmx_mio_pll_ctl {
2552 uint64_t u64;
2553 struct cvmx_mio_pll_ctl_s {
2554 #ifdef __BIG_ENDIAN_BITFIELD
2555 uint64_t reserved_5_63:59;
2556 uint64_t bw_ctl:5;
2557 #else
2558 uint64_t bw_ctl:5;
2559 uint64_t reserved_5_63:59;
2560 #endif
2561 } s;
2562 };
2563
2564 union cvmx_mio_pll_setting {
2565 uint64_t u64;
2566 struct cvmx_mio_pll_setting_s {
2567 #ifdef __BIG_ENDIAN_BITFIELD
2568 uint64_t reserved_17_63:47;
2569 uint64_t setting:17;
2570 #else
2571 uint64_t setting:17;
2572 uint64_t reserved_17_63:47;
2573 #endif
2574 } s;
2575 };
2576
2577 union cvmx_mio_ptp_ckout_hi_incr {
2578 uint64_t u64;
2579 struct cvmx_mio_ptp_ckout_hi_incr_s {
2580 #ifdef __BIG_ENDIAN_BITFIELD
2581 uint64_t nanosec:32;
2582 uint64_t frnanosec:32;
2583 #else
2584 uint64_t frnanosec:32;
2585 uint64_t nanosec:32;
2586 #endif
2587 } s;
2588 };
2589
2590 union cvmx_mio_ptp_ckout_lo_incr {
2591 uint64_t u64;
2592 struct cvmx_mio_ptp_ckout_lo_incr_s {
2593 #ifdef __BIG_ENDIAN_BITFIELD
2594 uint64_t nanosec:32;
2595 uint64_t frnanosec:32;
2596 #else
2597 uint64_t frnanosec:32;
2598 uint64_t nanosec:32;
2599 #endif
2600 } s;
2601 };
2602
2603 union cvmx_mio_ptp_ckout_thresh_hi {
2604 uint64_t u64;
2605 struct cvmx_mio_ptp_ckout_thresh_hi_s {
2606 #ifdef __BIG_ENDIAN_BITFIELD
2607 uint64_t nanosec:64;
2608 #else
2609 uint64_t nanosec:64;
2610 #endif
2611 } s;
2612 };
2613
2614 union cvmx_mio_ptp_ckout_thresh_lo {
2615 uint64_t u64;
2616 struct cvmx_mio_ptp_ckout_thresh_lo_s {
2617 #ifdef __BIG_ENDIAN_BITFIELD
2618 uint64_t reserved_32_63:32;
2619 uint64_t frnanosec:32;
2620 #else
2621 uint64_t frnanosec:32;
2622 uint64_t reserved_32_63:32;
2623 #endif
2624 } s;
2625 };
2626
2627 union cvmx_mio_ptp_clock_cfg {
2628 uint64_t u64;
2629 struct cvmx_mio_ptp_clock_cfg_s {
2630 #ifdef __BIG_ENDIAN_BITFIELD
2631 uint64_t reserved_42_63:22;
2632 uint64_t pps:1;
2633 uint64_t ckout:1;
2634 uint64_t ext_clk_edge:2;
2635 uint64_t ckout_out4:1;
2636 uint64_t pps_out:5;
2637 uint64_t pps_inv:1;
2638 uint64_t pps_en:1;
2639 uint64_t ckout_out:4;
2640 uint64_t ckout_inv:1;
2641 uint64_t ckout_en:1;
2642 uint64_t evcnt_in:6;
2643 uint64_t evcnt_edge:1;
2644 uint64_t evcnt_en:1;
2645 uint64_t tstmp_in:6;
2646 uint64_t tstmp_edge:1;
2647 uint64_t tstmp_en:1;
2648 uint64_t ext_clk_in:6;
2649 uint64_t ext_clk_en:1;
2650 uint64_t ptp_en:1;
2651 #else
2652 uint64_t ptp_en:1;
2653 uint64_t ext_clk_en:1;
2654 uint64_t ext_clk_in:6;
2655 uint64_t tstmp_en:1;
2656 uint64_t tstmp_edge:1;
2657 uint64_t tstmp_in:6;
2658 uint64_t evcnt_en:1;
2659 uint64_t evcnt_edge:1;
2660 uint64_t evcnt_in:6;
2661 uint64_t ckout_en:1;
2662 uint64_t ckout_inv:1;
2663 uint64_t ckout_out:4;
2664 uint64_t pps_en:1;
2665 uint64_t pps_inv:1;
2666 uint64_t pps_out:5;
2667 uint64_t ckout_out4:1;
2668 uint64_t ext_clk_edge:2;
2669 uint64_t ckout:1;
2670 uint64_t pps:1;
2671 uint64_t reserved_42_63:22;
2672 #endif
2673 } s;
2674 struct cvmx_mio_ptp_clock_cfg_cn63xx {
2675 #ifdef __BIG_ENDIAN_BITFIELD
2676 uint64_t reserved_24_63:40;
2677 uint64_t evcnt_in:6;
2678 uint64_t evcnt_edge:1;
2679 uint64_t evcnt_en:1;
2680 uint64_t tstmp_in:6;
2681 uint64_t tstmp_edge:1;
2682 uint64_t tstmp_en:1;
2683 uint64_t ext_clk_in:6;
2684 uint64_t ext_clk_en:1;
2685 uint64_t ptp_en:1;
2686 #else
2687 uint64_t ptp_en:1;
2688 uint64_t ext_clk_en:1;
2689 uint64_t ext_clk_in:6;
2690 uint64_t tstmp_en:1;
2691 uint64_t tstmp_edge:1;
2692 uint64_t tstmp_in:6;
2693 uint64_t evcnt_en:1;
2694 uint64_t evcnt_edge:1;
2695 uint64_t evcnt_in:6;
2696 uint64_t reserved_24_63:40;
2697 #endif
2698 } cn63xx;
2699 struct cvmx_mio_ptp_clock_cfg_cn66xx {
2700 #ifdef __BIG_ENDIAN_BITFIELD
2701 uint64_t reserved_40_63:24;
2702 uint64_t ext_clk_edge:2;
2703 uint64_t ckout_out4:1;
2704 uint64_t pps_out:5;
2705 uint64_t pps_inv:1;
2706 uint64_t pps_en:1;
2707 uint64_t ckout_out:4;
2708 uint64_t ckout_inv:1;
2709 uint64_t ckout_en:1;
2710 uint64_t evcnt_in:6;
2711 uint64_t evcnt_edge:1;
2712 uint64_t evcnt_en:1;
2713 uint64_t tstmp_in:6;
2714 uint64_t tstmp_edge:1;
2715 uint64_t tstmp_en:1;
2716 uint64_t ext_clk_in:6;
2717 uint64_t ext_clk_en:1;
2718 uint64_t ptp_en:1;
2719 #else
2720 uint64_t ptp_en:1;
2721 uint64_t ext_clk_en:1;
2722 uint64_t ext_clk_in:6;
2723 uint64_t tstmp_en:1;
2724 uint64_t tstmp_edge:1;
2725 uint64_t tstmp_in:6;
2726 uint64_t evcnt_en:1;
2727 uint64_t evcnt_edge:1;
2728 uint64_t evcnt_in:6;
2729 uint64_t ckout_en:1;
2730 uint64_t ckout_inv:1;
2731 uint64_t ckout_out:4;
2732 uint64_t pps_en:1;
2733 uint64_t pps_inv:1;
2734 uint64_t pps_out:5;
2735 uint64_t ckout_out4:1;
2736 uint64_t ext_clk_edge:2;
2737 uint64_t reserved_40_63:24;
2738 #endif
2739 } cn66xx;
2740 };
2741
2742 union cvmx_mio_ptp_clock_comp {
2743 uint64_t u64;
2744 struct cvmx_mio_ptp_clock_comp_s {
2745 #ifdef __BIG_ENDIAN_BITFIELD
2746 uint64_t nanosec:32;
2747 uint64_t frnanosec:32;
2748 #else
2749 uint64_t frnanosec:32;
2750 uint64_t nanosec:32;
2751 #endif
2752 } s;
2753 };
2754
2755 union cvmx_mio_ptp_clock_hi {
2756 uint64_t u64;
2757 struct cvmx_mio_ptp_clock_hi_s {
2758 #ifdef __BIG_ENDIAN_BITFIELD
2759 uint64_t nanosec:64;
2760 #else
2761 uint64_t nanosec:64;
2762 #endif
2763 } s;
2764 };
2765
2766 union cvmx_mio_ptp_clock_lo {
2767 uint64_t u64;
2768 struct cvmx_mio_ptp_clock_lo_s {
2769 #ifdef __BIG_ENDIAN_BITFIELD
2770 uint64_t reserved_32_63:32;
2771 uint64_t frnanosec:32;
2772 #else
2773 uint64_t frnanosec:32;
2774 uint64_t reserved_32_63:32;
2775 #endif
2776 } s;
2777 };
2778
2779 union cvmx_mio_ptp_evt_cnt {
2780 uint64_t u64;
2781 struct cvmx_mio_ptp_evt_cnt_s {
2782 #ifdef __BIG_ENDIAN_BITFIELD
2783 uint64_t cntr:64;
2784 #else
2785 uint64_t cntr:64;
2786 #endif
2787 } s;
2788 };
2789
2790 union cvmx_mio_ptp_phy_1pps_in {
2791 uint64_t u64;
2792 struct cvmx_mio_ptp_phy_1pps_in_s {
2793 #ifdef __BIG_ENDIAN_BITFIELD
2794 uint64_t reserved_5_63:59;
2795 uint64_t sel:5;
2796 #else
2797 uint64_t sel:5;
2798 uint64_t reserved_5_63:59;
2799 #endif
2800 } s;
2801 };
2802
2803 union cvmx_mio_ptp_pps_hi_incr {
2804 uint64_t u64;
2805 struct cvmx_mio_ptp_pps_hi_incr_s {
2806 #ifdef __BIG_ENDIAN_BITFIELD
2807 uint64_t nanosec:32;
2808 uint64_t frnanosec:32;
2809 #else
2810 uint64_t frnanosec:32;
2811 uint64_t nanosec:32;
2812 #endif
2813 } s;
2814 };
2815
2816 union cvmx_mio_ptp_pps_lo_incr {
2817 uint64_t u64;
2818 struct cvmx_mio_ptp_pps_lo_incr_s {
2819 #ifdef __BIG_ENDIAN_BITFIELD
2820 uint64_t nanosec:32;
2821 uint64_t frnanosec:32;
2822 #else
2823 uint64_t frnanosec:32;
2824 uint64_t nanosec:32;
2825 #endif
2826 } s;
2827 };
2828
2829 union cvmx_mio_ptp_pps_thresh_hi {
2830 uint64_t u64;
2831 struct cvmx_mio_ptp_pps_thresh_hi_s {
2832 #ifdef __BIG_ENDIAN_BITFIELD
2833 uint64_t nanosec:64;
2834 #else
2835 uint64_t nanosec:64;
2836 #endif
2837 } s;
2838 };
2839
2840 union cvmx_mio_ptp_pps_thresh_lo {
2841 uint64_t u64;
2842 struct cvmx_mio_ptp_pps_thresh_lo_s {
2843 #ifdef __BIG_ENDIAN_BITFIELD
2844 uint64_t reserved_32_63:32;
2845 uint64_t frnanosec:32;
2846 #else
2847 uint64_t frnanosec:32;
2848 uint64_t reserved_32_63:32;
2849 #endif
2850 } s;
2851 };
2852
2853 union cvmx_mio_ptp_timestamp {
2854 uint64_t u64;
2855 struct cvmx_mio_ptp_timestamp_s {
2856 #ifdef __BIG_ENDIAN_BITFIELD
2857 uint64_t nanosec:64;
2858 #else
2859 uint64_t nanosec:64;
2860 #endif
2861 } s;
2862 };
2863
2864 union cvmx_mio_qlmx_cfg {
2865 uint64_t u64;
2866 struct cvmx_mio_qlmx_cfg_s {
2867 #ifdef __BIG_ENDIAN_BITFIELD
2868 uint64_t reserved_15_63:49;
2869 uint64_t prtmode:1;
2870 uint64_t reserved_12_13:2;
2871 uint64_t qlm_spd:4;
2872 uint64_t reserved_4_7:4;
2873 uint64_t qlm_cfg:4;
2874 #else
2875 uint64_t qlm_cfg:4;
2876 uint64_t reserved_4_7:4;
2877 uint64_t qlm_spd:4;
2878 uint64_t reserved_12_13:2;
2879 uint64_t prtmode:1;
2880 uint64_t reserved_15_63:49;
2881 #endif
2882 } s;
2883 struct cvmx_mio_qlmx_cfg_cn61xx {
2884 #ifdef __BIG_ENDIAN_BITFIELD
2885 uint64_t reserved_15_63:49;
2886 uint64_t prtmode:1;
2887 uint64_t reserved_12_13:2;
2888 uint64_t qlm_spd:4;
2889 uint64_t reserved_2_7:6;
2890 uint64_t qlm_cfg:2;
2891 #else
2892 uint64_t qlm_cfg:2;
2893 uint64_t reserved_2_7:6;
2894 uint64_t qlm_spd:4;
2895 uint64_t reserved_12_13:2;
2896 uint64_t prtmode:1;
2897 uint64_t reserved_15_63:49;
2898 #endif
2899 } cn61xx;
2900 struct cvmx_mio_qlmx_cfg_cn66xx {
2901 #ifdef __BIG_ENDIAN_BITFIELD
2902 uint64_t reserved_12_63:52;
2903 uint64_t qlm_spd:4;
2904 uint64_t reserved_4_7:4;
2905 uint64_t qlm_cfg:4;
2906 #else
2907 uint64_t qlm_cfg:4;
2908 uint64_t reserved_4_7:4;
2909 uint64_t qlm_spd:4;
2910 uint64_t reserved_12_63:52;
2911 #endif
2912 } cn66xx;
2913 struct cvmx_mio_qlmx_cfg_cn68xx {
2914 #ifdef __BIG_ENDIAN_BITFIELD
2915 uint64_t reserved_12_63:52;
2916 uint64_t qlm_spd:4;
2917 uint64_t reserved_3_7:5;
2918 uint64_t qlm_cfg:3;
2919 #else
2920 uint64_t qlm_cfg:3;
2921 uint64_t reserved_3_7:5;
2922 uint64_t qlm_spd:4;
2923 uint64_t reserved_12_63:52;
2924 #endif
2925 } cn68xx;
2926 };
2927
2928 union cvmx_mio_rst_boot {
2929 uint64_t u64;
2930 struct cvmx_mio_rst_boot_s {
2931 #ifdef __BIG_ENDIAN_BITFIELD
2932 uint64_t chipkill:1;
2933 uint64_t jtcsrdis:1;
2934 uint64_t ejtagdis:1;
2935 uint64_t romen:1;
2936 uint64_t ckill_ppdis:1;
2937 uint64_t jt_tstmode:1;
2938 uint64_t reserved_50_57:8;
2939 uint64_t lboot_ext:2;
2940 uint64_t reserved_44_47:4;
2941 uint64_t qlm4_spd:4;
2942 uint64_t qlm3_spd:4;
2943 uint64_t c_mul:6;
2944 uint64_t pnr_mul:6;
2945 uint64_t qlm2_spd:4;
2946 uint64_t qlm1_spd:4;
2947 uint64_t qlm0_spd:4;
2948 uint64_t lboot:10;
2949 uint64_t rboot:1;
2950 uint64_t rboot_pin:1;
2951 #else
2952 uint64_t rboot_pin:1;
2953 uint64_t rboot:1;
2954 uint64_t lboot:10;
2955 uint64_t qlm0_spd:4;
2956 uint64_t qlm1_spd:4;
2957 uint64_t qlm2_spd:4;
2958 uint64_t pnr_mul:6;
2959 uint64_t c_mul:6;
2960 uint64_t qlm3_spd:4;
2961 uint64_t qlm4_spd:4;
2962 uint64_t reserved_44_47:4;
2963 uint64_t lboot_ext:2;
2964 uint64_t reserved_50_57:8;
2965 uint64_t jt_tstmode:1;
2966 uint64_t ckill_ppdis:1;
2967 uint64_t romen:1;
2968 uint64_t ejtagdis:1;
2969 uint64_t jtcsrdis:1;
2970 uint64_t chipkill:1;
2971 #endif
2972 } s;
2973 struct cvmx_mio_rst_boot_cn61xx {
2974 #ifdef __BIG_ENDIAN_BITFIELD
2975 uint64_t chipkill:1;
2976 uint64_t jtcsrdis:1;
2977 uint64_t ejtagdis:1;
2978 uint64_t romen:1;
2979 uint64_t ckill_ppdis:1;
2980 uint64_t jt_tstmode:1;
2981 uint64_t reserved_50_57:8;
2982 uint64_t lboot_ext:2;
2983 uint64_t reserved_36_47:12;
2984 uint64_t c_mul:6;
2985 uint64_t pnr_mul:6;
2986 uint64_t qlm2_spd:4;
2987 uint64_t qlm1_spd:4;
2988 uint64_t qlm0_spd:4;
2989 uint64_t lboot:10;
2990 uint64_t rboot:1;
2991 uint64_t rboot_pin:1;
2992 #else
2993 uint64_t rboot_pin:1;
2994 uint64_t rboot:1;
2995 uint64_t lboot:10;
2996 uint64_t qlm0_spd:4;
2997 uint64_t qlm1_spd:4;
2998 uint64_t qlm2_spd:4;
2999 uint64_t pnr_mul:6;
3000 uint64_t c_mul:6;
3001 uint64_t reserved_36_47:12;
3002 uint64_t lboot_ext:2;
3003 uint64_t reserved_50_57:8;
3004 uint64_t jt_tstmode:1;
3005 uint64_t ckill_ppdis:1;
3006 uint64_t romen:1;
3007 uint64_t ejtagdis:1;
3008 uint64_t jtcsrdis:1;
3009 uint64_t chipkill:1;
3010 #endif
3011 } cn61xx;
3012 struct cvmx_mio_rst_boot_cn63xx {
3013 #ifdef __BIG_ENDIAN_BITFIELD
3014 uint64_t reserved_36_63:28;
3015 uint64_t c_mul:6;
3016 uint64_t pnr_mul:6;
3017 uint64_t qlm2_spd:4;
3018 uint64_t qlm1_spd:4;
3019 uint64_t qlm0_spd:4;
3020 uint64_t lboot:10;
3021 uint64_t rboot:1;
3022 uint64_t rboot_pin:1;
3023 #else
3024 uint64_t rboot_pin:1;
3025 uint64_t rboot:1;
3026 uint64_t lboot:10;
3027 uint64_t qlm0_spd:4;
3028 uint64_t qlm1_spd:4;
3029 uint64_t qlm2_spd:4;
3030 uint64_t pnr_mul:6;
3031 uint64_t c_mul:6;
3032 uint64_t reserved_36_63:28;
3033 #endif
3034 } cn63xx;
3035 struct cvmx_mio_rst_boot_cn66xx {
3036 #ifdef __BIG_ENDIAN_BITFIELD
3037 uint64_t chipkill:1;
3038 uint64_t jtcsrdis:1;
3039 uint64_t ejtagdis:1;
3040 uint64_t romen:1;
3041 uint64_t ckill_ppdis:1;
3042 uint64_t reserved_50_58:9;
3043 uint64_t lboot_ext:2;
3044 uint64_t reserved_36_47:12;
3045 uint64_t c_mul:6;
3046 uint64_t pnr_mul:6;
3047 uint64_t qlm2_spd:4;
3048 uint64_t qlm1_spd:4;
3049 uint64_t qlm0_spd:4;
3050 uint64_t lboot:10;
3051 uint64_t rboot:1;
3052 uint64_t rboot_pin:1;
3053 #else
3054 uint64_t rboot_pin:1;
3055 uint64_t rboot:1;
3056 uint64_t lboot:10;
3057 uint64_t qlm0_spd:4;
3058 uint64_t qlm1_spd:4;
3059 uint64_t qlm2_spd:4;
3060 uint64_t pnr_mul:6;
3061 uint64_t c_mul:6;
3062 uint64_t reserved_36_47:12;
3063 uint64_t lboot_ext:2;
3064 uint64_t reserved_50_58:9;
3065 uint64_t ckill_ppdis:1;
3066 uint64_t romen:1;
3067 uint64_t ejtagdis:1;
3068 uint64_t jtcsrdis:1;
3069 uint64_t chipkill:1;
3070 #endif
3071 } cn66xx;
3072 struct cvmx_mio_rst_boot_cn68xx {
3073 #ifdef __BIG_ENDIAN_BITFIELD
3074 uint64_t reserved_59_63:5;
3075 uint64_t jt_tstmode:1;
3076 uint64_t reserved_44_57:14;
3077 uint64_t qlm4_spd:4;
3078 uint64_t qlm3_spd:4;
3079 uint64_t c_mul:6;
3080 uint64_t pnr_mul:6;
3081 uint64_t qlm2_spd:4;
3082 uint64_t qlm1_spd:4;
3083 uint64_t qlm0_spd:4;
3084 uint64_t lboot:10;
3085 uint64_t rboot:1;
3086 uint64_t rboot_pin:1;
3087 #else
3088 uint64_t rboot_pin:1;
3089 uint64_t rboot:1;
3090 uint64_t lboot:10;
3091 uint64_t qlm0_spd:4;
3092 uint64_t qlm1_spd:4;
3093 uint64_t qlm2_spd:4;
3094 uint64_t pnr_mul:6;
3095 uint64_t c_mul:6;
3096 uint64_t qlm3_spd:4;
3097 uint64_t qlm4_spd:4;
3098 uint64_t reserved_44_57:14;
3099 uint64_t jt_tstmode:1;
3100 uint64_t reserved_59_63:5;
3101 #endif
3102 } cn68xx;
3103 struct cvmx_mio_rst_boot_cn68xxp1 {
3104 #ifdef __BIG_ENDIAN_BITFIELD
3105 uint64_t reserved_44_63:20;
3106 uint64_t qlm4_spd:4;
3107 uint64_t qlm3_spd:4;
3108 uint64_t c_mul:6;
3109 uint64_t pnr_mul:6;
3110 uint64_t qlm2_spd:4;
3111 uint64_t qlm1_spd:4;
3112 uint64_t qlm0_spd:4;
3113 uint64_t lboot:10;
3114 uint64_t rboot:1;
3115 uint64_t rboot_pin:1;
3116 #else
3117 uint64_t rboot_pin:1;
3118 uint64_t rboot:1;
3119 uint64_t lboot:10;
3120 uint64_t qlm0_spd:4;
3121 uint64_t qlm1_spd:4;
3122 uint64_t qlm2_spd:4;
3123 uint64_t pnr_mul:6;
3124 uint64_t c_mul:6;
3125 uint64_t qlm3_spd:4;
3126 uint64_t qlm4_spd:4;
3127 uint64_t reserved_44_63:20;
3128 #endif
3129 } cn68xxp1;
3130 };
3131
3132 union cvmx_mio_rst_cfg {
3133 uint64_t u64;
3134 struct cvmx_mio_rst_cfg_s {
3135 #ifdef __BIG_ENDIAN_BITFIELD
3136 uint64_t reserved_3_63:61;
3137 uint64_t cntl_clr_bist:1;
3138 uint64_t warm_clr_bist:1;
3139 uint64_t soft_clr_bist:1;
3140 #else
3141 uint64_t soft_clr_bist:1;
3142 uint64_t warm_clr_bist:1;
3143 uint64_t cntl_clr_bist:1;
3144 uint64_t reserved_3_63:61;
3145 #endif
3146 } s;
3147 struct cvmx_mio_rst_cfg_cn61xx {
3148 #ifdef __BIG_ENDIAN_BITFIELD
3149 uint64_t bist_delay:58;
3150 uint64_t reserved_3_5:3;
3151 uint64_t cntl_clr_bist:1;
3152 uint64_t warm_clr_bist:1;
3153 uint64_t soft_clr_bist:1;
3154 #else
3155 uint64_t soft_clr_bist:1;
3156 uint64_t warm_clr_bist:1;
3157 uint64_t cntl_clr_bist:1;
3158 uint64_t reserved_3_5:3;
3159 uint64_t bist_delay:58;
3160 #endif
3161 } cn61xx;
3162 struct cvmx_mio_rst_cfg_cn63xxp1 {
3163 #ifdef __BIG_ENDIAN_BITFIELD
3164 uint64_t bist_delay:58;
3165 uint64_t reserved_2_5:4;
3166 uint64_t warm_clr_bist:1;
3167 uint64_t soft_clr_bist:1;
3168 #else
3169 uint64_t soft_clr_bist:1;
3170 uint64_t warm_clr_bist:1;
3171 uint64_t reserved_2_5:4;
3172 uint64_t bist_delay:58;
3173 #endif
3174 } cn63xxp1;
3175 struct cvmx_mio_rst_cfg_cn68xx {
3176 #ifdef __BIG_ENDIAN_BITFIELD
3177 uint64_t bist_delay:56;
3178 uint64_t reserved_3_7:5;
3179 uint64_t cntl_clr_bist:1;
3180 uint64_t warm_clr_bist:1;
3181 uint64_t soft_clr_bist:1;
3182 #else
3183 uint64_t soft_clr_bist:1;
3184 uint64_t warm_clr_bist:1;
3185 uint64_t cntl_clr_bist:1;
3186 uint64_t reserved_3_7:5;
3187 uint64_t bist_delay:56;
3188 #endif
3189 } cn68xx;
3190 };
3191
3192 union cvmx_mio_rst_ckill {
3193 uint64_t u64;
3194 struct cvmx_mio_rst_ckill_s {
3195 #ifdef __BIG_ENDIAN_BITFIELD
3196 uint64_t reserved_47_63:17;
3197 uint64_t timer:47;
3198 #else
3199 uint64_t timer:47;
3200 uint64_t reserved_47_63:17;
3201 #endif
3202 } s;
3203 };
3204
3205 union cvmx_mio_rst_cntlx {
3206 uint64_t u64;
3207 struct cvmx_mio_rst_cntlx_s {
3208 #ifdef __BIG_ENDIAN_BITFIELD
3209 uint64_t reserved_13_63:51;
3210 uint64_t in_rev_ln:1;
3211 uint64_t rev_lanes:1;
3212 uint64_t gen1_only:1;
3213 uint64_t prst_link:1;
3214 uint64_t rst_done:1;
3215 uint64_t rst_link:1;
3216 uint64_t host_mode:1;
3217 uint64_t prtmode:2;
3218 uint64_t rst_drv:1;
3219 uint64_t rst_rcv:1;
3220 uint64_t rst_chip:1;
3221 uint64_t rst_val:1;
3222 #else
3223 uint64_t rst_val:1;
3224 uint64_t rst_chip:1;
3225 uint64_t rst_rcv:1;
3226 uint64_t rst_drv:1;
3227 uint64_t prtmode:2;
3228 uint64_t host_mode:1;
3229 uint64_t rst_link:1;
3230 uint64_t rst_done:1;
3231 uint64_t prst_link:1;
3232 uint64_t gen1_only:1;
3233 uint64_t rev_lanes:1;
3234 uint64_t in_rev_ln:1;
3235 uint64_t reserved_13_63:51;
3236 #endif
3237 } s;
3238 struct cvmx_mio_rst_cntlx_cn66xx {
3239 #ifdef __BIG_ENDIAN_BITFIELD
3240 uint64_t reserved_10_63:54;
3241 uint64_t prst_link:1;
3242 uint64_t rst_done:1;
3243 uint64_t rst_link:1;
3244 uint64_t host_mode:1;
3245 uint64_t prtmode:2;
3246 uint64_t rst_drv:1;
3247 uint64_t rst_rcv:1;
3248 uint64_t rst_chip:1;
3249 uint64_t rst_val:1;
3250 #else
3251 uint64_t rst_val:1;
3252 uint64_t rst_chip:1;
3253 uint64_t rst_rcv:1;
3254 uint64_t rst_drv:1;
3255 uint64_t prtmode:2;
3256 uint64_t host_mode:1;
3257 uint64_t rst_link:1;
3258 uint64_t rst_done:1;
3259 uint64_t prst_link:1;
3260 uint64_t reserved_10_63:54;
3261 #endif
3262 } cn66xx;
3263 };
3264
3265 union cvmx_mio_rst_ctlx {
3266 uint64_t u64;
3267 struct cvmx_mio_rst_ctlx_s {
3268 #ifdef __BIG_ENDIAN_BITFIELD
3269 uint64_t reserved_13_63:51;
3270 uint64_t in_rev_ln:1;
3271 uint64_t rev_lanes:1;
3272 uint64_t gen1_only:1;
3273 uint64_t prst_link:1;
3274 uint64_t rst_done:1;
3275 uint64_t rst_link:1;
3276 uint64_t host_mode:1;
3277 uint64_t prtmode:2;
3278 uint64_t rst_drv:1;
3279 uint64_t rst_rcv:1;
3280 uint64_t rst_chip:1;
3281 uint64_t rst_val:1;
3282 #else
3283 uint64_t rst_val:1;
3284 uint64_t rst_chip:1;
3285 uint64_t rst_rcv:1;
3286 uint64_t rst_drv:1;
3287 uint64_t prtmode:2;
3288 uint64_t host_mode:1;
3289 uint64_t rst_link:1;
3290 uint64_t rst_done:1;
3291 uint64_t prst_link:1;
3292 uint64_t gen1_only:1;
3293 uint64_t rev_lanes:1;
3294 uint64_t in_rev_ln:1;
3295 uint64_t reserved_13_63:51;
3296 #endif
3297 } s;
3298 struct cvmx_mio_rst_ctlx_cn63xx {
3299 #ifdef __BIG_ENDIAN_BITFIELD
3300 uint64_t reserved_10_63:54;
3301 uint64_t prst_link:1;
3302 uint64_t rst_done:1;
3303 uint64_t rst_link:1;
3304 uint64_t host_mode:1;
3305 uint64_t prtmode:2;
3306 uint64_t rst_drv:1;
3307 uint64_t rst_rcv:1;
3308 uint64_t rst_chip:1;
3309 uint64_t rst_val:1;
3310 #else
3311 uint64_t rst_val:1;
3312 uint64_t rst_chip:1;
3313 uint64_t rst_rcv:1;
3314 uint64_t rst_drv:1;
3315 uint64_t prtmode:2;
3316 uint64_t host_mode:1;
3317 uint64_t rst_link:1;
3318 uint64_t rst_done:1;
3319 uint64_t prst_link:1;
3320 uint64_t reserved_10_63:54;
3321 #endif
3322 } cn63xx;
3323 struct cvmx_mio_rst_ctlx_cn63xxp1 {
3324 #ifdef __BIG_ENDIAN_BITFIELD
3325 uint64_t reserved_9_63:55;
3326 uint64_t rst_done:1;
3327 uint64_t rst_link:1;
3328 uint64_t host_mode:1;
3329 uint64_t prtmode:2;
3330 uint64_t rst_drv:1;
3331 uint64_t rst_rcv:1;
3332 uint64_t rst_chip:1;
3333 uint64_t rst_val:1;
3334 #else
3335 uint64_t rst_val:1;
3336 uint64_t rst_chip:1;
3337 uint64_t rst_rcv:1;
3338 uint64_t rst_drv:1;
3339 uint64_t prtmode:2;
3340 uint64_t host_mode:1;
3341 uint64_t rst_link:1;
3342 uint64_t rst_done:1;
3343 uint64_t reserved_9_63:55;
3344 #endif
3345 } cn63xxp1;
3346 };
3347
3348 union cvmx_mio_rst_delay {
3349 uint64_t u64;
3350 struct cvmx_mio_rst_delay_s {
3351 #ifdef __BIG_ENDIAN_BITFIELD
3352 uint64_t reserved_32_63:32;
3353 uint64_t warm_rst_dly:16;
3354 uint64_t soft_rst_dly:16;
3355 #else
3356 uint64_t soft_rst_dly:16;
3357 uint64_t warm_rst_dly:16;
3358 uint64_t reserved_32_63:32;
3359 #endif
3360 } s;
3361 };
3362
3363 union cvmx_mio_rst_int {
3364 uint64_t u64;
3365 struct cvmx_mio_rst_int_s {
3366 #ifdef __BIG_ENDIAN_BITFIELD
3367 uint64_t reserved_10_63:54;
3368 uint64_t perst1:1;
3369 uint64_t perst0:1;
3370 uint64_t reserved_4_7:4;
3371 uint64_t rst_link3:1;
3372 uint64_t rst_link2:1;
3373 uint64_t rst_link1:1;
3374 uint64_t rst_link0:1;
3375 #else
3376 uint64_t rst_link0:1;
3377 uint64_t rst_link1:1;
3378 uint64_t rst_link2:1;
3379 uint64_t rst_link3:1;
3380 uint64_t reserved_4_7:4;
3381 uint64_t perst0:1;
3382 uint64_t perst1:1;
3383 uint64_t reserved_10_63:54;
3384 #endif
3385 } s;
3386 struct cvmx_mio_rst_int_cn61xx {
3387 #ifdef __BIG_ENDIAN_BITFIELD
3388 uint64_t reserved_10_63:54;
3389 uint64_t perst1:1;
3390 uint64_t perst0:1;
3391 uint64_t reserved_2_7:6;
3392 uint64_t rst_link1:1;
3393 uint64_t rst_link0:1;
3394 #else
3395 uint64_t rst_link0:1;
3396 uint64_t rst_link1:1;
3397 uint64_t reserved_2_7:6;
3398 uint64_t perst0:1;
3399 uint64_t perst1:1;
3400 uint64_t reserved_10_63:54;
3401 #endif
3402 } cn61xx;
3403 };
3404
3405 union cvmx_mio_rst_int_en {
3406 uint64_t u64;
3407 struct cvmx_mio_rst_int_en_s {
3408 #ifdef __BIG_ENDIAN_BITFIELD
3409 uint64_t reserved_10_63:54;
3410 uint64_t perst1:1;
3411 uint64_t perst0:1;
3412 uint64_t reserved_4_7:4;
3413 uint64_t rst_link3:1;
3414 uint64_t rst_link2:1;
3415 uint64_t rst_link1:1;
3416 uint64_t rst_link0:1;
3417 #else
3418 uint64_t rst_link0:1;
3419 uint64_t rst_link1:1;
3420 uint64_t rst_link2:1;
3421 uint64_t rst_link3:1;
3422 uint64_t reserved_4_7:4;
3423 uint64_t perst0:1;
3424 uint64_t perst1:1;
3425 uint64_t reserved_10_63:54;
3426 #endif
3427 } s;
3428 struct cvmx_mio_rst_int_en_cn61xx {
3429 #ifdef __BIG_ENDIAN_BITFIELD
3430 uint64_t reserved_10_63:54;
3431 uint64_t perst1:1;
3432 uint64_t perst0:1;
3433 uint64_t reserved_2_7:6;
3434 uint64_t rst_link1:1;
3435 uint64_t rst_link0:1;
3436 #else
3437 uint64_t rst_link0:1;
3438 uint64_t rst_link1:1;
3439 uint64_t reserved_2_7:6;
3440 uint64_t perst0:1;
3441 uint64_t perst1:1;
3442 uint64_t reserved_10_63:54;
3443 #endif
3444 } cn61xx;
3445 };
3446
3447 union cvmx_mio_twsx_int {
3448 uint64_t u64;
3449 struct cvmx_mio_twsx_int_s {
3450 #ifdef __BIG_ENDIAN_BITFIELD
3451 uint64_t reserved_12_63:52;
3452 uint64_t scl:1;
3453 uint64_t sda:1;
3454 uint64_t scl_ovr:1;
3455 uint64_t sda_ovr:1;
3456 uint64_t reserved_7_7:1;
3457 uint64_t core_en:1;
3458 uint64_t ts_en:1;
3459 uint64_t st_en:1;
3460 uint64_t reserved_3_3:1;
3461 uint64_t core_int:1;
3462 uint64_t ts_int:1;
3463 uint64_t st_int:1;
3464 #else
3465 uint64_t st_int:1;
3466 uint64_t ts_int:1;
3467 uint64_t core_int:1;
3468 uint64_t reserved_3_3:1;
3469 uint64_t st_en:1;
3470 uint64_t ts_en:1;
3471 uint64_t core_en:1;
3472 uint64_t reserved_7_7:1;
3473 uint64_t sda_ovr:1;
3474 uint64_t scl_ovr:1;
3475 uint64_t sda:1;
3476 uint64_t scl:1;
3477 uint64_t reserved_12_63:52;
3478 #endif
3479 } s;
3480 struct cvmx_mio_twsx_int_cn38xxp2 {
3481 #ifdef __BIG_ENDIAN_BITFIELD
3482 uint64_t reserved_7_63:57;
3483 uint64_t core_en:1;
3484 uint64_t ts_en:1;
3485 uint64_t st_en:1;
3486 uint64_t reserved_3_3:1;
3487 uint64_t core_int:1;
3488 uint64_t ts_int:1;
3489 uint64_t st_int:1;
3490 #else
3491 uint64_t st_int:1;
3492 uint64_t ts_int:1;
3493 uint64_t core_int:1;
3494 uint64_t reserved_3_3:1;
3495 uint64_t st_en:1;
3496 uint64_t ts_en:1;
3497 uint64_t core_en:1;
3498 uint64_t reserved_7_63:57;
3499 #endif
3500 } cn38xxp2;
3501 };
3502
3503 union cvmx_mio_twsx_sw_twsi {
3504 uint64_t u64;
3505 struct cvmx_mio_twsx_sw_twsi_s {
3506 #ifdef __BIG_ENDIAN_BITFIELD
3507 uint64_t v:1;
3508 uint64_t slonly:1;
3509 uint64_t eia:1;
3510 uint64_t op:4;
3511 uint64_t r:1;
3512 uint64_t sovr:1;
3513 uint64_t size:3;
3514 uint64_t scr:2;
3515 uint64_t a:10;
3516 uint64_t ia:5;
3517 uint64_t eop_ia:3;
3518 uint64_t d:32;
3519 #else
3520 uint64_t d:32;
3521 uint64_t eop_ia:3;
3522 uint64_t ia:5;
3523 uint64_t a:10;
3524 uint64_t scr:2;
3525 uint64_t size:3;
3526 uint64_t sovr:1;
3527 uint64_t r:1;
3528 uint64_t op:4;
3529 uint64_t eia:1;
3530 uint64_t slonly:1;
3531 uint64_t v:1;
3532 #endif
3533 } s;
3534 };
3535
3536 union cvmx_mio_twsx_sw_twsi_ext {
3537 uint64_t u64;
3538 struct cvmx_mio_twsx_sw_twsi_ext_s {
3539 #ifdef __BIG_ENDIAN_BITFIELD
3540 uint64_t reserved_40_63:24;
3541 uint64_t ia:8;
3542 uint64_t d:32;
3543 #else
3544 uint64_t d:32;
3545 uint64_t ia:8;
3546 uint64_t reserved_40_63:24;
3547 #endif
3548 } s;
3549 };
3550
3551 union cvmx_mio_twsx_twsi_sw {
3552 uint64_t u64;
3553 struct cvmx_mio_twsx_twsi_sw_s {
3554 #ifdef __BIG_ENDIAN_BITFIELD
3555 uint64_t v:2;
3556 uint64_t reserved_32_61:30;
3557 uint64_t d:32;
3558 #else
3559 uint64_t d:32;
3560 uint64_t reserved_32_61:30;
3561 uint64_t v:2;
3562 #endif
3563 } s;
3564 };
3565
3566 union cvmx_mio_uartx_dlh {
3567 uint64_t u64;
3568 struct cvmx_mio_uartx_dlh_s {
3569 #ifdef __BIG_ENDIAN_BITFIELD
3570 uint64_t reserved_8_63:56;
3571 uint64_t dlh:8;
3572 #else
3573 uint64_t dlh:8;
3574 uint64_t reserved_8_63:56;
3575 #endif
3576 } s;
3577 };
3578
3579 union cvmx_mio_uartx_dll {
3580 uint64_t u64;
3581 struct cvmx_mio_uartx_dll_s {
3582 #ifdef __BIG_ENDIAN_BITFIELD
3583 uint64_t reserved_8_63:56;
3584 uint64_t dll:8;
3585 #else
3586 uint64_t dll:8;
3587 uint64_t reserved_8_63:56;
3588 #endif
3589 } s;
3590 };
3591
3592 union cvmx_mio_uartx_far {
3593 uint64_t u64;
3594 struct cvmx_mio_uartx_far_s {
3595 #ifdef __BIG_ENDIAN_BITFIELD
3596 uint64_t reserved_1_63:63;
3597 uint64_t far:1;
3598 #else
3599 uint64_t far:1;
3600 uint64_t reserved_1_63:63;
3601 #endif
3602 } s;
3603 };
3604
3605 union cvmx_mio_uartx_fcr {
3606 uint64_t u64;
3607 struct cvmx_mio_uartx_fcr_s {
3608 #ifdef __BIG_ENDIAN_BITFIELD
3609 uint64_t reserved_8_63:56;
3610 uint64_t rxtrig:2;
3611 uint64_t txtrig:2;
3612 uint64_t reserved_3_3:1;
3613 uint64_t txfr:1;
3614 uint64_t rxfr:1;
3615 uint64_t en:1;
3616 #else
3617 uint64_t en:1;
3618 uint64_t rxfr:1;
3619 uint64_t txfr:1;
3620 uint64_t reserved_3_3:1;
3621 uint64_t txtrig:2;
3622 uint64_t rxtrig:2;
3623 uint64_t reserved_8_63:56;
3624 #endif
3625 } s;
3626 };
3627
3628 union cvmx_mio_uartx_htx {
3629 uint64_t u64;
3630 struct cvmx_mio_uartx_htx_s {
3631 #ifdef __BIG_ENDIAN_BITFIELD
3632 uint64_t reserved_1_63:63;
3633 uint64_t htx:1;
3634 #else
3635 uint64_t htx:1;
3636 uint64_t reserved_1_63:63;
3637 #endif
3638 } s;
3639 };
3640
3641 union cvmx_mio_uartx_ier {
3642 uint64_t u64;
3643 struct cvmx_mio_uartx_ier_s {
3644 #ifdef __BIG_ENDIAN_BITFIELD
3645 uint64_t reserved_8_63:56;
3646 uint64_t ptime:1;
3647 uint64_t reserved_4_6:3;
3648 uint64_t edssi:1;
3649 uint64_t elsi:1;
3650 uint64_t etbei:1;
3651 uint64_t erbfi:1;
3652 #else
3653 uint64_t erbfi:1;
3654 uint64_t etbei:1;
3655 uint64_t elsi:1;
3656 uint64_t edssi:1;
3657 uint64_t reserved_4_6:3;
3658 uint64_t ptime:1;
3659 uint64_t reserved_8_63:56;
3660 #endif
3661 } s;
3662 };
3663
3664 union cvmx_mio_uartx_iir {
3665 uint64_t u64;
3666 struct cvmx_mio_uartx_iir_s {
3667 #ifdef __BIG_ENDIAN_BITFIELD
3668 uint64_t reserved_8_63:56;
3669 uint64_t fen:2;
3670 uint64_t reserved_4_5:2;
3671 uint64_t iid:4;
3672 #else
3673 uint64_t iid:4;
3674 uint64_t reserved_4_5:2;
3675 uint64_t fen:2;
3676 uint64_t reserved_8_63:56;
3677 #endif
3678 } s;
3679 };
3680
3681 union cvmx_mio_uartx_lcr {
3682 uint64_t u64;
3683 struct cvmx_mio_uartx_lcr_s {
3684 #ifdef __BIG_ENDIAN_BITFIELD
3685 uint64_t reserved_8_63:56;
3686 uint64_t dlab:1;
3687 uint64_t brk:1;
3688 uint64_t reserved_5_5:1;
3689 uint64_t eps:1;
3690 uint64_t pen:1;
3691 uint64_t stop:1;
3692 uint64_t cls:2;
3693 #else
3694 uint64_t cls:2;
3695 uint64_t stop:1;
3696 uint64_t pen:1;
3697 uint64_t eps:1;
3698 uint64_t reserved_5_5:1;
3699 uint64_t brk:1;
3700 uint64_t dlab:1;
3701 uint64_t reserved_8_63:56;
3702 #endif
3703 } s;
3704 };
3705
3706 union cvmx_mio_uartx_lsr {
3707 uint64_t u64;
3708 struct cvmx_mio_uartx_lsr_s {
3709 #ifdef __BIG_ENDIAN_BITFIELD
3710 uint64_t reserved_8_63:56;
3711 uint64_t ferr:1;
3712 uint64_t temt:1;
3713 uint64_t thre:1;
3714 uint64_t bi:1;
3715 uint64_t fe:1;
3716 uint64_t pe:1;
3717 uint64_t oe:1;
3718 uint64_t dr:1;
3719 #else
3720 uint64_t dr:1;
3721 uint64_t oe:1;
3722 uint64_t pe:1;
3723 uint64_t fe:1;
3724 uint64_t bi:1;
3725 uint64_t thre:1;
3726 uint64_t temt:1;
3727 uint64_t ferr:1;
3728 uint64_t reserved_8_63:56;
3729 #endif
3730 } s;
3731 };
3732
3733 union cvmx_mio_uartx_mcr {
3734 uint64_t u64;
3735 struct cvmx_mio_uartx_mcr_s {
3736 #ifdef __BIG_ENDIAN_BITFIELD
3737 uint64_t reserved_6_63:58;
3738 uint64_t afce:1;
3739 uint64_t loop:1;
3740 uint64_t out2:1;
3741 uint64_t out1:1;
3742 uint64_t rts:1;
3743 uint64_t dtr:1;
3744 #else
3745 uint64_t dtr:1;
3746 uint64_t rts:1;
3747 uint64_t out1:1;
3748 uint64_t out2:1;
3749 uint64_t loop:1;
3750 uint64_t afce:1;
3751 uint64_t reserved_6_63:58;
3752 #endif
3753 } s;
3754 };
3755
3756 union cvmx_mio_uartx_msr {
3757 uint64_t u64;
3758 struct cvmx_mio_uartx_msr_s {
3759 #ifdef __BIG_ENDIAN_BITFIELD
3760 uint64_t reserved_8_63:56;
3761 uint64_t dcd:1;
3762 uint64_t ri:1;
3763 uint64_t dsr:1;
3764 uint64_t cts:1;
3765 uint64_t ddcd:1;
3766 uint64_t teri:1;
3767 uint64_t ddsr:1;
3768 uint64_t dcts:1;
3769 #else
3770 uint64_t dcts:1;
3771 uint64_t ddsr:1;
3772 uint64_t teri:1;
3773 uint64_t ddcd:1;
3774 uint64_t cts:1;
3775 uint64_t dsr:1;
3776 uint64_t ri:1;
3777 uint64_t dcd:1;
3778 uint64_t reserved_8_63:56;
3779 #endif
3780 } s;
3781 };
3782
3783 union cvmx_mio_uartx_rbr {
3784 uint64_t u64;
3785 struct cvmx_mio_uartx_rbr_s {
3786 #ifdef __BIG_ENDIAN_BITFIELD
3787 uint64_t reserved_8_63:56;
3788 uint64_t rbr:8;
3789 #else
3790 uint64_t rbr:8;
3791 uint64_t reserved_8_63:56;
3792 #endif
3793 } s;
3794 };
3795
3796 union cvmx_mio_uartx_rfl {
3797 uint64_t u64;
3798 struct cvmx_mio_uartx_rfl_s {
3799 #ifdef __BIG_ENDIAN_BITFIELD
3800 uint64_t reserved_7_63:57;
3801 uint64_t rfl:7;
3802 #else
3803 uint64_t rfl:7;
3804 uint64_t reserved_7_63:57;
3805 #endif
3806 } s;
3807 };
3808
3809 union cvmx_mio_uartx_rfw {
3810 uint64_t u64;
3811 struct cvmx_mio_uartx_rfw_s {
3812 #ifdef __BIG_ENDIAN_BITFIELD
3813 uint64_t reserved_10_63:54;
3814 uint64_t rffe:1;
3815 uint64_t rfpe:1;
3816 uint64_t rfwd:8;
3817 #else
3818 uint64_t rfwd:8;
3819 uint64_t rfpe:1;
3820 uint64_t rffe:1;
3821 uint64_t reserved_10_63:54;
3822 #endif
3823 } s;
3824 };
3825
3826 union cvmx_mio_uartx_sbcr {
3827 uint64_t u64;
3828 struct cvmx_mio_uartx_sbcr_s {
3829 #ifdef __BIG_ENDIAN_BITFIELD
3830 uint64_t reserved_1_63:63;
3831 uint64_t sbcr:1;
3832 #else
3833 uint64_t sbcr:1;
3834 uint64_t reserved_1_63:63;
3835 #endif
3836 } s;
3837 };
3838
3839 union cvmx_mio_uartx_scr {
3840 uint64_t u64;
3841 struct cvmx_mio_uartx_scr_s {
3842 #ifdef __BIG_ENDIAN_BITFIELD
3843 uint64_t reserved_8_63:56;
3844 uint64_t scr:8;
3845 #else
3846 uint64_t scr:8;
3847 uint64_t reserved_8_63:56;
3848 #endif
3849 } s;
3850 };
3851
3852 union cvmx_mio_uartx_sfe {
3853 uint64_t u64;
3854 struct cvmx_mio_uartx_sfe_s {
3855 #ifdef __BIG_ENDIAN_BITFIELD
3856 uint64_t reserved_1_63:63;
3857 uint64_t sfe:1;
3858 #else
3859 uint64_t sfe:1;
3860 uint64_t reserved_1_63:63;
3861 #endif
3862 } s;
3863 };
3864
3865 union cvmx_mio_uartx_srr {
3866 uint64_t u64;
3867 struct cvmx_mio_uartx_srr_s {
3868 #ifdef __BIG_ENDIAN_BITFIELD
3869 uint64_t reserved_3_63:61;
3870 uint64_t stfr:1;
3871 uint64_t srfr:1;
3872 uint64_t usr:1;
3873 #else
3874 uint64_t usr:1;
3875 uint64_t srfr:1;
3876 uint64_t stfr:1;
3877 uint64_t reserved_3_63:61;
3878 #endif
3879 } s;
3880 };
3881
3882 union cvmx_mio_uartx_srt {
3883 uint64_t u64;
3884 struct cvmx_mio_uartx_srt_s {
3885 #ifdef __BIG_ENDIAN_BITFIELD
3886 uint64_t reserved_2_63:62;
3887 uint64_t srt:2;
3888 #else
3889 uint64_t srt:2;
3890 uint64_t reserved_2_63:62;
3891 #endif
3892 } s;
3893 };
3894
3895 union cvmx_mio_uartx_srts {
3896 uint64_t u64;
3897 struct cvmx_mio_uartx_srts_s {
3898 #ifdef __BIG_ENDIAN_BITFIELD
3899 uint64_t reserved_1_63:63;
3900 uint64_t srts:1;
3901 #else
3902 uint64_t srts:1;
3903 uint64_t reserved_1_63:63;
3904 #endif
3905 } s;
3906 };
3907
3908 union cvmx_mio_uartx_stt {
3909 uint64_t u64;
3910 struct cvmx_mio_uartx_stt_s {
3911 #ifdef __BIG_ENDIAN_BITFIELD
3912 uint64_t reserved_2_63:62;
3913 uint64_t stt:2;
3914 #else
3915 uint64_t stt:2;
3916 uint64_t reserved_2_63:62;
3917 #endif
3918 } s;
3919 };
3920
3921 union cvmx_mio_uartx_tfl {
3922 uint64_t u64;
3923 struct cvmx_mio_uartx_tfl_s {
3924 #ifdef __BIG_ENDIAN_BITFIELD
3925 uint64_t reserved_7_63:57;
3926 uint64_t tfl:7;
3927 #else
3928 uint64_t tfl:7;
3929 uint64_t reserved_7_63:57;
3930 #endif
3931 } s;
3932 };
3933
3934 union cvmx_mio_uartx_tfr {
3935 uint64_t u64;
3936 struct cvmx_mio_uartx_tfr_s {
3937 #ifdef __BIG_ENDIAN_BITFIELD
3938 uint64_t reserved_8_63:56;
3939 uint64_t tfr:8;
3940 #else
3941 uint64_t tfr:8;
3942 uint64_t reserved_8_63:56;
3943 #endif
3944 } s;
3945 };
3946
3947 union cvmx_mio_uartx_thr {
3948 uint64_t u64;
3949 struct cvmx_mio_uartx_thr_s {
3950 #ifdef __BIG_ENDIAN_BITFIELD
3951 uint64_t reserved_8_63:56;
3952 uint64_t thr:8;
3953 #else
3954 uint64_t thr:8;
3955 uint64_t reserved_8_63:56;
3956 #endif
3957 } s;
3958 };
3959
3960 union cvmx_mio_uartx_usr {
3961 uint64_t u64;
3962 struct cvmx_mio_uartx_usr_s {
3963 #ifdef __BIG_ENDIAN_BITFIELD
3964 uint64_t reserved_5_63:59;
3965 uint64_t rff:1;
3966 uint64_t rfne:1;
3967 uint64_t tfe:1;
3968 uint64_t tfnf:1;
3969 uint64_t busy:1;
3970 #else
3971 uint64_t busy:1;
3972 uint64_t tfnf:1;
3973 uint64_t tfe:1;
3974 uint64_t rfne:1;
3975 uint64_t rff:1;
3976 uint64_t reserved_5_63:59;
3977 #endif
3978 } s;
3979 };
3980
3981 union cvmx_mio_uart2_dlh {
3982 uint64_t u64;
3983 struct cvmx_mio_uart2_dlh_s {
3984 #ifdef __BIG_ENDIAN_BITFIELD
3985 uint64_t reserved_8_63:56;
3986 uint64_t dlh:8;
3987 #else
3988 uint64_t dlh:8;
3989 uint64_t reserved_8_63:56;
3990 #endif
3991 } s;
3992 };
3993
3994 union cvmx_mio_uart2_dll {
3995 uint64_t u64;
3996 struct cvmx_mio_uart2_dll_s {
3997 #ifdef __BIG_ENDIAN_BITFIELD
3998 uint64_t reserved_8_63:56;
3999 uint64_t dll:8;
4000 #else
4001 uint64_t dll:8;
4002 uint64_t reserved_8_63:56;
4003 #endif
4004 } s;
4005 };
4006
4007 union cvmx_mio_uart2_far {
4008 uint64_t u64;
4009 struct cvmx_mio_uart2_far_s {
4010 #ifdef __BIG_ENDIAN_BITFIELD
4011 uint64_t reserved_1_63:63;
4012 uint64_t far:1;
4013 #else
4014 uint64_t far:1;
4015 uint64_t reserved_1_63:63;
4016 #endif
4017 } s;
4018 };
4019
4020 union cvmx_mio_uart2_fcr {
4021 uint64_t u64;
4022 struct cvmx_mio_uart2_fcr_s {
4023 #ifdef __BIG_ENDIAN_BITFIELD
4024 uint64_t reserved_8_63:56;
4025 uint64_t rxtrig:2;
4026 uint64_t txtrig:2;
4027 uint64_t reserved_3_3:1;
4028 uint64_t txfr:1;
4029 uint64_t rxfr:1;
4030 uint64_t en:1;
4031 #else
4032 uint64_t en:1;
4033 uint64_t rxfr:1;
4034 uint64_t txfr:1;
4035 uint64_t reserved_3_3:1;
4036 uint64_t txtrig:2;
4037 uint64_t rxtrig:2;
4038 uint64_t reserved_8_63:56;
4039 #endif
4040 } s;
4041 };
4042
4043 union cvmx_mio_uart2_htx {
4044 uint64_t u64;
4045 struct cvmx_mio_uart2_htx_s {
4046 #ifdef __BIG_ENDIAN_BITFIELD
4047 uint64_t reserved_1_63:63;
4048 uint64_t htx:1;
4049 #else
4050 uint64_t htx:1;
4051 uint64_t reserved_1_63:63;
4052 #endif
4053 } s;
4054 };
4055
4056 union cvmx_mio_uart2_ier {
4057 uint64_t u64;
4058 struct cvmx_mio_uart2_ier_s {
4059 #ifdef __BIG_ENDIAN_BITFIELD
4060 uint64_t reserved_8_63:56;
4061 uint64_t ptime:1;
4062 uint64_t reserved_4_6:3;
4063 uint64_t edssi:1;
4064 uint64_t elsi:1;
4065 uint64_t etbei:1;
4066 uint64_t erbfi:1;
4067 #else
4068 uint64_t erbfi:1;
4069 uint64_t etbei:1;
4070 uint64_t elsi:1;
4071 uint64_t edssi:1;
4072 uint64_t reserved_4_6:3;
4073 uint64_t ptime:1;
4074 uint64_t reserved_8_63:56;
4075 #endif
4076 } s;
4077 };
4078
4079 union cvmx_mio_uart2_iir {
4080 uint64_t u64;
4081 struct cvmx_mio_uart2_iir_s {
4082 #ifdef __BIG_ENDIAN_BITFIELD
4083 uint64_t reserved_8_63:56;
4084 uint64_t fen:2;
4085 uint64_t reserved_4_5:2;
4086 uint64_t iid:4;
4087 #else
4088 uint64_t iid:4;
4089 uint64_t reserved_4_5:2;
4090 uint64_t fen:2;
4091 uint64_t reserved_8_63:56;
4092 #endif
4093 } s;
4094 };
4095
4096 union cvmx_mio_uart2_lcr {
4097 uint64_t u64;
4098 struct cvmx_mio_uart2_lcr_s {
4099 #ifdef __BIG_ENDIAN_BITFIELD
4100 uint64_t reserved_8_63:56;
4101 uint64_t dlab:1;
4102 uint64_t brk:1;
4103 uint64_t reserved_5_5:1;
4104 uint64_t eps:1;
4105 uint64_t pen:1;
4106 uint64_t stop:1;
4107 uint64_t cls:2;
4108 #else
4109 uint64_t cls:2;
4110 uint64_t stop:1;
4111 uint64_t pen:1;
4112 uint64_t eps:1;
4113 uint64_t reserved_5_5:1;
4114 uint64_t brk:1;
4115 uint64_t dlab:1;
4116 uint64_t reserved_8_63:56;
4117 #endif
4118 } s;
4119 };
4120
4121 union cvmx_mio_uart2_lsr {
4122 uint64_t u64;
4123 struct cvmx_mio_uart2_lsr_s {
4124 #ifdef __BIG_ENDIAN_BITFIELD
4125 uint64_t reserved_8_63:56;
4126 uint64_t ferr:1;
4127 uint64_t temt:1;
4128 uint64_t thre:1;
4129 uint64_t bi:1;
4130 uint64_t fe:1;
4131 uint64_t pe:1;
4132 uint64_t oe:1;
4133 uint64_t dr:1;
4134 #else
4135 uint64_t dr:1;
4136 uint64_t oe:1;
4137 uint64_t pe:1;
4138 uint64_t fe:1;
4139 uint64_t bi:1;
4140 uint64_t thre:1;
4141 uint64_t temt:1;
4142 uint64_t ferr:1;
4143 uint64_t reserved_8_63:56;
4144 #endif
4145 } s;
4146 };
4147
4148 union cvmx_mio_uart2_mcr {
4149 uint64_t u64;
4150 struct cvmx_mio_uart2_mcr_s {
4151 #ifdef __BIG_ENDIAN_BITFIELD
4152 uint64_t reserved_6_63:58;
4153 uint64_t afce:1;
4154 uint64_t loop:1;
4155 uint64_t out2:1;
4156 uint64_t out1:1;
4157 uint64_t rts:1;
4158 uint64_t dtr:1;
4159 #else
4160 uint64_t dtr:1;
4161 uint64_t rts:1;
4162 uint64_t out1:1;
4163 uint64_t out2:1;
4164 uint64_t loop:1;
4165 uint64_t afce:1;
4166 uint64_t reserved_6_63:58;
4167 #endif
4168 } s;
4169 };
4170
4171 union cvmx_mio_uart2_msr {
4172 uint64_t u64;
4173 struct cvmx_mio_uart2_msr_s {
4174 #ifdef __BIG_ENDIAN_BITFIELD
4175 uint64_t reserved_8_63:56;
4176 uint64_t dcd:1;
4177 uint64_t ri:1;
4178 uint64_t dsr:1;
4179 uint64_t cts:1;
4180 uint64_t ddcd:1;
4181 uint64_t teri:1;
4182 uint64_t ddsr:1;
4183 uint64_t dcts:1;
4184 #else
4185 uint64_t dcts:1;
4186 uint64_t ddsr:1;
4187 uint64_t teri:1;
4188 uint64_t ddcd:1;
4189 uint64_t cts:1;
4190 uint64_t dsr:1;
4191 uint64_t ri:1;
4192 uint64_t dcd:1;
4193 uint64_t reserved_8_63:56;
4194 #endif
4195 } s;
4196 };
4197
4198 union cvmx_mio_uart2_rbr {
4199 uint64_t u64;
4200 struct cvmx_mio_uart2_rbr_s {
4201 #ifdef __BIG_ENDIAN_BITFIELD
4202 uint64_t reserved_8_63:56;
4203 uint64_t rbr:8;
4204 #else
4205 uint64_t rbr:8;
4206 uint64_t reserved_8_63:56;
4207 #endif
4208 } s;
4209 };
4210
4211 union cvmx_mio_uart2_rfl {
4212 uint64_t u64;
4213 struct cvmx_mio_uart2_rfl_s {
4214 #ifdef __BIG_ENDIAN_BITFIELD
4215 uint64_t reserved_7_63:57;
4216 uint64_t rfl:7;
4217 #else
4218 uint64_t rfl:7;
4219 uint64_t reserved_7_63:57;
4220 #endif
4221 } s;
4222 };
4223
4224 union cvmx_mio_uart2_rfw {
4225 uint64_t u64;
4226 struct cvmx_mio_uart2_rfw_s {
4227 #ifdef __BIG_ENDIAN_BITFIELD
4228 uint64_t reserved_10_63:54;
4229 uint64_t rffe:1;
4230 uint64_t rfpe:1;
4231 uint64_t rfwd:8;
4232 #else
4233 uint64_t rfwd:8;
4234 uint64_t rfpe:1;
4235 uint64_t rffe:1;
4236 uint64_t reserved_10_63:54;
4237 #endif
4238 } s;
4239 };
4240
4241 union cvmx_mio_uart2_sbcr {
4242 uint64_t u64;
4243 struct cvmx_mio_uart2_sbcr_s {
4244 #ifdef __BIG_ENDIAN_BITFIELD
4245 uint64_t reserved_1_63:63;
4246 uint64_t sbcr:1;
4247 #else
4248 uint64_t sbcr:1;
4249 uint64_t reserved_1_63:63;
4250 #endif
4251 } s;
4252 };
4253
4254 union cvmx_mio_uart2_scr {
4255 uint64_t u64;
4256 struct cvmx_mio_uart2_scr_s {
4257 #ifdef __BIG_ENDIAN_BITFIELD
4258 uint64_t reserved_8_63:56;
4259 uint64_t scr:8;
4260 #else
4261 uint64_t scr:8;
4262 uint64_t reserved_8_63:56;
4263 #endif
4264 } s;
4265 };
4266
4267 union cvmx_mio_uart2_sfe {
4268 uint64_t u64;
4269 struct cvmx_mio_uart2_sfe_s {
4270 #ifdef __BIG_ENDIAN_BITFIELD
4271 uint64_t reserved_1_63:63;
4272 uint64_t sfe:1;
4273 #else
4274 uint64_t sfe:1;
4275 uint64_t reserved_1_63:63;
4276 #endif
4277 } s;
4278 };
4279
4280 union cvmx_mio_uart2_srr {
4281 uint64_t u64;
4282 struct cvmx_mio_uart2_srr_s {
4283 #ifdef __BIG_ENDIAN_BITFIELD
4284 uint64_t reserved_3_63:61;
4285 uint64_t stfr:1;
4286 uint64_t srfr:1;
4287 uint64_t usr:1;
4288 #else
4289 uint64_t usr:1;
4290 uint64_t srfr:1;
4291 uint64_t stfr:1;
4292 uint64_t reserved_3_63:61;
4293 #endif
4294 } s;
4295 };
4296
4297 union cvmx_mio_uart2_srt {
4298 uint64_t u64;
4299 struct cvmx_mio_uart2_srt_s {
4300 #ifdef __BIG_ENDIAN_BITFIELD
4301 uint64_t reserved_2_63:62;
4302 uint64_t srt:2;
4303 #else
4304 uint64_t srt:2;
4305 uint64_t reserved_2_63:62;
4306 #endif
4307 } s;
4308 };
4309
4310 union cvmx_mio_uart2_srts {
4311 uint64_t u64;
4312 struct cvmx_mio_uart2_srts_s {
4313 #ifdef __BIG_ENDIAN_BITFIELD
4314 uint64_t reserved_1_63:63;
4315 uint64_t srts:1;
4316 #else
4317 uint64_t srts:1;
4318 uint64_t reserved_1_63:63;
4319 #endif
4320 } s;
4321 };
4322
4323 union cvmx_mio_uart2_stt {
4324 uint64_t u64;
4325 struct cvmx_mio_uart2_stt_s {
4326 #ifdef __BIG_ENDIAN_BITFIELD
4327 uint64_t reserved_2_63:62;
4328 uint64_t stt:2;
4329 #else
4330 uint64_t stt:2;
4331 uint64_t reserved_2_63:62;
4332 #endif
4333 } s;
4334 };
4335
4336 union cvmx_mio_uart2_tfl {
4337 uint64_t u64;
4338 struct cvmx_mio_uart2_tfl_s {
4339 #ifdef __BIG_ENDIAN_BITFIELD
4340 uint64_t reserved_7_63:57;
4341 uint64_t tfl:7;
4342 #else
4343 uint64_t tfl:7;
4344 uint64_t reserved_7_63:57;
4345 #endif
4346 } s;
4347 };
4348
4349 union cvmx_mio_uart2_tfr {
4350 uint64_t u64;
4351 struct cvmx_mio_uart2_tfr_s {
4352 #ifdef __BIG_ENDIAN_BITFIELD
4353 uint64_t reserved_8_63:56;
4354 uint64_t tfr:8;
4355 #else
4356 uint64_t tfr:8;
4357 uint64_t reserved_8_63:56;
4358 #endif
4359 } s;
4360 };
4361
4362 union cvmx_mio_uart2_thr {
4363 uint64_t u64;
4364 struct cvmx_mio_uart2_thr_s {
4365 #ifdef __BIG_ENDIAN_BITFIELD
4366 uint64_t reserved_8_63:56;
4367 uint64_t thr:8;
4368 #else
4369 uint64_t thr:8;
4370 uint64_t reserved_8_63:56;
4371 #endif
4372 } s;
4373 };
4374
4375 union cvmx_mio_uart2_usr {
4376 uint64_t u64;
4377 struct cvmx_mio_uart2_usr_s {
4378 #ifdef __BIG_ENDIAN_BITFIELD
4379 uint64_t reserved_5_63:59;
4380 uint64_t rff:1;
4381 uint64_t rfne:1;
4382 uint64_t tfe:1;
4383 uint64_t tfnf:1;
4384 uint64_t busy:1;
4385 #else
4386 uint64_t busy:1;
4387 uint64_t tfnf:1;
4388 uint64_t tfe:1;
4389 uint64_t rfne:1;
4390 uint64_t rff:1;
4391 uint64_t reserved_5_63:59;
4392 #endif
4393 } s;
4394 };
4395
4396 #endif
Kernel DRM miscellaneous fixes and cross-tree changes